target/armv4_5_cache: change prototype of armv4_5_handle_cache_info_command()
[openocd.git] / src / target / armv4_5_cache.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "armv4_5_cache.h"
24 #include <helper/log.h>
25
26 int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common *cache)
27 {
28 int size, assoc, M, len, multiplier;
29
30 cache->ctype = (cache_type_reg & 0x1e000000U) >> 25;
31 cache->separate = (cache_type_reg & 0x01000000U) >> 24;
32
33 size = (cache_type_reg & 0x1c0000) >> 18;
34 assoc = (cache_type_reg & 0x38000) >> 15;
35 M = (cache_type_reg & 0x4000) >> 14;
36 len = (cache_type_reg & 0x3000) >> 12;
37 multiplier = 2 + M;
38
39 if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */ {
40 /* cache is present */
41 cache->d_u_size.linelen = 1 << (len + 3);
42 cache->d_u_size.associativity = multiplier << (assoc - 1);
43 cache->d_u_size.nsets = 1 << (size + 6 - assoc - len);
44 cache->d_u_size.cachesize = multiplier << (size + 8);
45 } else {
46 /* cache is absent */
47 cache->d_u_size.linelen = -1;
48 cache->d_u_size.associativity = -1;
49 cache->d_u_size.nsets = -1;
50 cache->d_u_size.cachesize = -1;
51 }
52
53 if (cache->separate) {
54 size = (cache_type_reg & 0x1c0) >> 6;
55 assoc = (cache_type_reg & 0x38) >> 3;
56 M = (cache_type_reg & 0x4) >> 2;
57 len = (cache_type_reg & 0x3);
58 multiplier = 2 + M;
59
60 if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */ {
61 /* cache is present */
62 cache->i_size.linelen = 1 << (len + 3);
63 cache->i_size.associativity = multiplier << (assoc - 1);
64 cache->i_size.nsets = 1 << (size + 6 - assoc - len);
65 cache->i_size.cachesize = multiplier << (size + 8);
66 } else {
67 /* cache is absent */
68 cache->i_size.linelen = -1;
69 cache->i_size.associativity = -1;
70 cache->i_size.nsets = -1;
71 cache->i_size.cachesize = -1;
72 }
73 } else
74 cache->i_size = cache->d_u_size;
75
76 return ERROR_OK;
77 }
78
79 int armv4_5_handle_cache_info_command(struct command_invocation *cmd, struct armv4_5_cache_common *armv4_5_cache)
80 {
81 if (armv4_5_cache->ctype == -1) {
82 command_print(cmd->ctx, "cache not yet identified");
83 return ERROR_OK;
84 }
85
86 command_print(cmd->ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
87 (armv4_5_cache->separate) ? "separate caches" : "unified cache");
88
89 command_print(cmd->ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
90 armv4_5_cache->d_u_size.linelen,
91 armv4_5_cache->d_u_size.associativity,
92 armv4_5_cache->d_u_size.nsets,
93 armv4_5_cache->d_u_size.cachesize);
94
95 command_print(cmd->ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
96 armv4_5_cache->i_size.linelen,
97 armv4_5_cache->i_size.associativity,
98 armv4_5_cache->i_size.nsets,
99 armv4_5_cache->i_size.cachesize);
100
101 return ERROR_OK;
102 }