src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include <target/target.h>
  30 #include <helper/command.h>
  31
  32
  33 typedef enum arm_mode
  34 {
  35         ARM_MODE_USR = 16,
  36         ARM_MODE_FIQ = 17,
  37         ARM_MODE_IRQ = 18,
  38         ARM_MODE_SVC = 19,
  39         ARM_MODE_ABT = 23,
  40         ARM_MODE_MON = 26,
  41         ARM_MODE_UND = 27,
  42         ARM_MODE_SYS = 31,
  43         ARM_MODE_ANY = -1
  44 } arm_mode_t;
  45
  46 const char *arm_mode_name(unsigned psr_mode);
  47 bool is_arm_mode(unsigned psr_mode);
  48
  49 int arm_mode_to_number(enum arm_mode mode);
  50 enum arm_mode armv4_5_number_to_mode(int number);
  51
  52 typedef enum arm_state
  53 {
  54         ARM_STATE_ARM,
  55         ARM_STATE_THUMB,
  56         ARM_STATE_JAZELLE,
  57         ARM_STATE_THUMB_EE,
  58 } arm_state_t;
  59
  60 extern const char *arm_state_strings[];
  61
  62 extern const int armv4_5_core_reg_map[8][17];
  63
  64 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  65                 cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
  66
  67 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
  68 enum { ARMV4_5_CPSR = 31, };
  69
  70 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  71
  72 /**
  73  * Represents a generic ARM core, with standard application registers.
  74  *
  75  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  76  * Cortex-M series cores do not support as many core states or shadowed
  77  * registers as traditional ARM cores, and only support Thumb2 instructions.
  78  */
  79 struct arm
  80 {
  81         int common_magic;
  82         struct reg_cache *core_cache;
  83
  84         /** Handle to the CPSR; valid in all core modes. */
  85         struct reg *cpsr;
  86
  87         /** Handle to the SPSR; valid only in core modes with an SPSR. */
  88         struct reg *spsr;
  89
  90         const int *map;
  91
  92         /**
  93          * Indicates what registers are in the ARM state core register set.
  94          * ARM_MODE_ANY indicates the standard set of 37 registers,
  95          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
  96          * more registers are shadowed, for "Secure Monitor" mode.
  97          */
  98         enum arm_mode core_type;
  99
 100         enum arm_mode core_mode;
 101         enum arm_state core_state;
 102
 103         /** Flag reporting unavailability of the BKPT instruction. */
 104         bool is_armv4;
 105
 106         /** Flag reporting whether semihosting is active. */
 107         bool is_semihosting;
 108
 109         /** Value to be returned by semihosting SYS_ERRNO request. */
 110         int semihosting_errno;
 111
 112         /** Backpointer to the target. */
 113         struct target *target;
 114
 115         /** Handle for the debug module, if one is present. */
 116         struct arm_dpm *dpm;
 117
 118         /** Handle for the Embedded Trace Module, if one is present. */
 119         struct etm_context *etm;
 120
 121         /* FIXME all these methods should take "struct arm *" not target */
 122
 123         int (*full_context)(struct target *target);
 124         int (*read_core_reg)(struct target *target, struct reg *reg,
 125                         int num, enum arm_mode mode);
 126         int (*write_core_reg)(struct target *target, struct reg *reg,
 127                         int num, enum arm_mode mode, uint32_t value);
 128
 129         /** Read coprocessor register.  */
 130         int (*mrc)(struct target *target, int cpnum,
 131                         uint32_t op1, uint32_t op2,
 132                         uint32_t CRn, uint32_t CRm,
 133                         uint32_t *value);
 134
 135         /* Write coprocessor register.  */
 136         int (*mcr)(struct target *target, int cpnum,
 137                         uint32_t op1, uint32_t op2,
 138                         uint32_t CRn, uint32_t CRm,
 139                         uint32_t value);
 140
 141         void *arch_info;
 142 };
 143
 144 /** Convert target handle to generic ARM target state handle. */
 145 static inline struct arm *target_to_arm(struct target *target)
 146 {
 147         return target->arch_info;
 148 }
 149
 150 static inline bool is_arm(struct arm *arm)
 151 {
 152         return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
 153 }
 154
 155 struct armv4_5_algorithm
 156 {
 157         int common_magic;
 158
 159         enum arm_mode core_mode;
 160         enum arm_state core_state;
 161 };
 162
 163 struct arm_reg
 164 {
 165         int num;
 166         enum arm_mode mode;
 167         struct target *target;
 168         struct arm *armv4_5_common;
 169         uint32_t value;
 170 };
 171
 172 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
 173                 struct arm *armv4_5_common);
 174
 175 int armv4_5_arch_state(struct target *target);
 176 int armv4_5_get_gdb_reg_list(struct target *target,
 177                 struct reg **reg_list[], int *reg_list_size);
 178
 179 extern const struct command_registration arm_command_handlers[];
 180
 181 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 182
 183 int armv4_5_run_algorithm(struct target *target,
 184                 int num_mem_params, struct mem_param *mem_params,
 185                 int num_reg_params, struct reg_param *reg_params,
 186                 uint32_t entry_point, uint32_t exit_point,
 187                 int timeout_ms, void *arch_info);
 188
 189 int arm_checksum_memory(struct target *target,
 190                 uint32_t address, uint32_t count, uint32_t *checksum);
 191 int arm_blank_check_memory(struct target *target,
 192                 uint32_t address, uint32_t count, uint32_t *blank);
 193
 194 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 195 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 196
 197 extern struct reg arm_gdb_dummy_fp_reg;
 198 extern struct reg arm_gdb_dummy_fps_reg;
 199
 200 /* ARM mode instructions
 201  */
 202
 203 /* Store multiple increment after
 204  * Rn: base register
 205  * List: for each bit in list: store register
 206  * S: in priviledged mode: store user-mode registers
 207  * W = 1: update the base register. W = 0: leave the base register untouched
 208  */
 209 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 210
 211 /* Load multiple increment after
 212  * Rn: base register
 213  * List: for each bit in list: store register
 214  * S: in priviledged mode: store user-mode registers
 215  * W = 1: update the base register. W = 0: leave the base register untouched
 216  */
 217 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 218
 219 /* MOV r8, r8 */
 220 #define ARMV4_5_NOP                                     (0xe1a08008)
 221
 222 /* Move PSR to general purpose register
 223  * R = 1: SPSR R = 0: CPSR
 224  * Rn: target register
 225  */
 226 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 227
 228 /* Store register
 229  * Rd: register to store
 230  * Rn: base register
 231  */
 232 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 233
 234 /* Load register
 235  * Rd: register to load
 236  * Rn: base register
 237  */
 238 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 239
 240 /* Move general purpose register to PSR
 241  * R = 1: SPSR R = 0: CPSR
 242  * Field: Field mask
 243  * 1: control field 2: extension field 4: status field 8: flags field
 244  * Rm: source register
 245  */
 246 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 247 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 248
 249 /* Load Register Halfword Immediate Post-Index
 250  * Rd: register to load
 251  * Rn: base register
 252  */
 253 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 254
 255 /* Load Register Byte Immediate Post-Index
 256  * Rd: register to load
 257  * Rn: base register
 258  */
 259 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 260
 261 /* Store register Halfword Immediate Post-Index
 262  * Rd: register to store
 263  * Rn: base register
 264  */
 265 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 266
 267 /* Store register Byte Immediate Post-Index
 268  * Rd: register to store
 269  * Rn: base register
 270  */
 271 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 272
 273 /* Branch (and Link)
 274  * Im: Branch target (left-shifted by 2 bits, added to PC)
 275  * L: 1: branch and link 0: branch only
 276  */
 277 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 278
 279 /* Branch and exchange (ARM state)
 280  * Rm: register holding branch target address
 281  */
 282 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 283
 284 /* Move to ARM register from coprocessor
 285  * CP: Coprocessor number
 286  * op1: Coprocessor opcode
 287  * Rd: destination register
 288  * CRn: first coprocessor operand
 289  * CRm: second coprocessor operand
 290  * op2: Second coprocessor opcode
 291  */
 292 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 293
 294 /* Move to coprocessor from ARM register
 295  * CP: Coprocessor number
 296  * op1: Coprocessor opcode
 297  * Rd: destination register
 298  * CRn: first coprocessor operand
 299  * CRm: second coprocessor operand
 300  * op2: Second coprocessor opcode
 301  */
 302 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 303
 304 /* Breakpoint instruction (ARMv5)
 305  * Im: 16-bit immediate
 306  */
 307 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 308
 309
 310 /* Thumb mode instructions
 311  */
 312
 313 /* Store register (Thumb mode)
 314  * Rd: source register
 315  * Rn: base register
 316  */
 317 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 318
 319 /* Load register (Thumb state)
 320  * Rd: destination register
 321  * Rn: base register
 322  */
 323 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 324
 325 /* Load multiple (Thumb state)
 326  * Rn: base register
 327  * List: for each bit in list: store register
 328  */
 329 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 330
 331 /* Load register with PC relative addressing
 332  * Rd: register to load
 333  */
 334 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 335
 336 /* Move hi register (Thumb mode)
 337  * Rd: destination register
 338  * Rm: source register
 339  */
 340 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 341
 342 /* No operation (Thumb mode)
 343  */
 344 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 345
 346 /* Move immediate to register (Thumb state)
 347  * Rd: destination register
 348  * Im: 8-bit immediate value
 349  */
 350 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 351
 352 /* Branch and Exchange
 353  * Rm: register containing branch target
 354  */
 355 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 356
 357 /* Branch (Thumb state)
 358  * Imm: Branch target
 359  */
 360 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 361
 362 /* Breakpoint instruction (ARMv5) (Thumb state)
 363  * Im: 8-bit immediate
 364  */
 365 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 366
 367 /* build basic mrc/mcr opcode */
 368
 369 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 370 {
 371         uint32_t t = 0;
 372         t|=op1<<21;
 373         t|=op2<<5;
 374         t|=CRn<<16;
 375         t|=CRm<<0;
 376         return t;
 377 }
 378
 379 #endif /* ARMV4_5_H */