1 /***************************************************************************
2 * Copyright (C) 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Hongtao Zheng *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "arm_disassembler.h"
29 #include "arm_simulator.h"
31 #include "binarybuffer.h"
34 uint32_t arm_shift(uint8_t shift
, uint32_t Rm
, uint32_t shift_amount
, uint8_t *carry
)
36 uint32_t return_value
= 0;
39 if (shift
== 0x0) /* LSL */
41 if ((shift_amount
> 0) && (shift_amount
<= 32))
43 return_value
= Rm
<< shift_amount
;
44 *carry
= Rm
>> (32 - shift_amount
);
46 else if (shift_amount
> 32)
51 else /* (shift_amount == 0) */
56 else if (shift
== 0x1) /* LSR */
58 if ((shift_amount
> 0) && (shift_amount
<= 32))
60 return_value
= Rm
>> shift_amount
;
61 *carry
= (Rm
>> (shift_amount
- 1)) & 1;
63 else if (shift_amount
> 32)
68 else /* (shift_amount == 0) */
73 else if (shift
== 0x2) /* ASR */
75 if ((shift_amount
> 0) && (shift_amount
<= 32))
77 /* right shifts of unsigned values are guaranteed to be logical (shift in zeroes)
78 * simulate an arithmetic shift (shift in signed-bit) by adding the signed-bit manually */
79 return_value
= Rm
>> shift_amount
;
81 return_value
|= 0xffffffff << (32 - shift_amount
);
83 else if (shift_amount
> 32)
87 return_value
= 0xffffffff;
96 else /* (shift_amount == 0) */
101 else if (shift
== 0x3) /* ROR */
103 if (shift_amount
== 0)
109 shift_amount
= shift_amount
% 32;
110 return_value
= (Rm
>> shift_amount
) | (Rm
<< (32 - shift_amount
));
111 *carry
= (return_value
>> 31) & 0x1;
114 else if (shift
== 0x4) /* RRX */
116 return_value
= Rm
>> 1;
126 uint32_t arm_shifter_operand(struct arm_sim_interface
*sim
, int variant
, union arm_shifter_operand shifter_operand
, uint8_t *shifter_carry_out
)
128 uint32_t return_value
;
129 int instruction_size
;
131 if (sim
->get_state(sim
) == ARMV4_5_STATE_ARM
)
132 instruction_size
= 4;
134 instruction_size
= 2;
136 *shifter_carry_out
= sim
->get_cpsr(sim
, 29, 1);
138 if (variant
== 0) /* 32-bit immediate */
140 return_value
= shifter_operand
.immediate
.immediate
;
142 else if (variant
== 1) /* immediate shift */
144 uint32_t Rm
= sim
->get_reg_mode(sim
, shifter_operand
.immediate_shift
.Rm
);
146 /* adjust RM in case the PC is being read */
147 if (shifter_operand
.immediate_shift
.Rm
== 15)
148 Rm
+= 2 * instruction_size
;
150 return_value
= arm_shift(shifter_operand
.immediate_shift
.shift
, Rm
, shifter_operand
.immediate_shift
.shift_imm
, shifter_carry_out
);
152 else if (variant
== 2) /* register shift */
154 uint32_t Rm
= sim
->get_reg_mode(sim
, shifter_operand
.register_shift
.Rm
);
155 uint32_t Rs
= sim
->get_reg_mode(sim
, shifter_operand
.register_shift
.Rs
);
157 /* adjust RM in case the PC is being read */
158 if (shifter_operand
.register_shift
.Rm
== 15)
159 Rm
+= 2 * instruction_size
;
161 return_value
= arm_shift(shifter_operand
.immediate_shift
.shift
, Rm
, Rs
, shifter_carry_out
);
165 LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
166 return_value
= 0xffffffff;
172 int pass_condition(uint32_t cpsr
, uint32_t opcode
)
174 switch ((opcode
& 0xf0000000) >> 28)
177 if (cpsr
& 0x40000000)
182 if (!(cpsr
& 0x40000000))
187 if (cpsr
& 0x20000000)
192 if (!(cpsr
& 0x20000000))
197 if (cpsr
& 0x80000000)
202 if (!(cpsr
& 0x80000000))
207 if (cpsr
& 0x10000000)
212 if (!(cpsr
& 0x10000000))
217 if ((cpsr
& 0x20000000) && !(cpsr
& 0x40000000))
222 if (!(cpsr
& 0x20000000) || (cpsr
& 0x40000000))
227 if (((cpsr
& 0x80000000) && (cpsr
& 0x10000000))
228 || (!(cpsr
& 0x80000000) && !(cpsr
& 0x10000000)))
233 if (((cpsr
& 0x80000000) && !(cpsr
& 0x10000000))
234 || (!(cpsr
& 0x80000000) && (cpsr
& 0x10000000)))
239 if (!(cpsr
& 0x40000000) &&
240 (((cpsr
& 0x80000000) && (cpsr
& 0x10000000))
241 || (!(cpsr
& 0x80000000) && !(cpsr
& 0x10000000))))
246 if ((cpsr
& 0x40000000) &&
247 (((cpsr
& 0x80000000) && !(cpsr
& 0x10000000))
248 || (!(cpsr
& 0x80000000) && (cpsr
& 0x10000000))))
258 LOG_ERROR("BUG: should never get here");
262 int thumb_pass_branch_condition(uint32_t cpsr
, uint16_t opcode
)
264 return pass_condition(cpsr
, (opcode
& 0x0f00) << 20);
267 /* simulate a single step (if possible)
268 * if the dry_run_pc argument is provided, no state is changed,
269 * but the new pc is stored in the variable pointed at by the argument
271 int arm_simulate_step_core(target_t
*target
, uint32_t *dry_run_pc
, struct arm_sim_interface
*sim
)
273 uint32_t current_pc
= sim
->get_reg(sim
, 15);
274 arm_instruction_t instruction
;
275 int instruction_size
;
276 int retval
= ERROR_OK
;
278 if (sim
->get_state(sim
) == ARMV4_5_STATE_ARM
)
282 /* get current instruction, and identify it */
283 if ((retval
= target_read_u32(target
, current_pc
, &opcode
)) != ERROR_OK
)
287 if ((retval
= arm_evaluate_opcode(opcode
, current_pc
, &instruction
)) != ERROR_OK
)
291 instruction_size
= 4;
293 /* check condition code (for all instructions) */
294 if (!pass_condition(sim
->get_cpsr(sim
, 0, 32), opcode
))
298 *dry_run_pc
= current_pc
+ instruction_size
;
302 sim
->set_reg(sim
, 15, current_pc
+ instruction_size
);
312 if ((retval
= target_read_u16(target
, current_pc
, &opcode
)) != ERROR_OK
)
316 if ((retval
= thumb_evaluate_opcode(opcode
, current_pc
, &instruction
)) != ERROR_OK
)
320 instruction_size
= 2;
322 /* check condition code (only for branch instructions) */
323 if ((!thumb_pass_branch_condition(sim
->get_cpsr(sim
, 0, 32), opcode
)) &&
324 (instruction
.type
== ARM_B
))
328 *dry_run_pc
= current_pc
+ instruction_size
;
332 sim
->set_reg(sim
, 15, current_pc
+ instruction_size
);
339 /* examine instruction type */
341 /* branch instructions */
342 if ((instruction
.type
>= ARM_B
) && (instruction
.type
<= ARM_BLX
))
346 if (instruction
.info
.b_bl_bx_blx
.reg_operand
== -1)
348 target
= instruction
.info
.b_bl_bx_blx
.target_address
;
352 target
= sim
->get_reg_mode(sim
, instruction
.info
.b_bl_bx_blx
.reg_operand
);
353 if (instruction
.info
.b_bl_bx_blx
.reg_operand
== 15)
355 target
+= 2 * instruction_size
;
361 *dry_run_pc
= target
;
366 if (instruction
.type
== ARM_B
)
368 sim
->set_reg(sim
, 15, target
);
370 else if (instruction
.type
== ARM_BL
)
372 uint32_t old_pc
= sim
->get_reg(sim
, 15);
373 sim
->set_reg_mode(sim
, 14, old_pc
+ 4);
374 sim
->set_reg(sim
, 15, target
);
376 else if (instruction
.type
== ARM_BX
)
380 sim
->set_state(sim
, ARMV4_5_STATE_THUMB
);
384 sim
->set_state(sim
, ARMV4_5_STATE_ARM
);
386 sim
->set_reg(sim
, 15, target
& 0xfffffffe);
388 else if (instruction
.type
== ARM_BLX
)
390 uint32_t old_pc
= sim
->get_reg(sim
, 15);
391 sim
->set_reg_mode(sim
, 14, old_pc
+ 4);
395 sim
->set_state(sim
, ARMV4_5_STATE_THUMB
);
399 sim
->set_state(sim
, ARMV4_5_STATE_ARM
);
401 sim
->set_reg(sim
, 15, target
& 0xfffffffe);
407 /* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */
408 else if (((instruction
.type
>= ARM_AND
) && (instruction
.type
<= ARM_RSC
))
409 || ((instruction
.type
>= ARM_ORR
) && (instruction
.type
<= ARM_MVN
)))
411 uint32_t Rd
, Rn
, shifter_operand
;
412 uint8_t C
= sim
->get_cpsr(sim
, 29, 1);
416 /* ARM_MOV and ARM_MVN does not use Rn */
417 if ((instruction
.type
!= ARM_MOV
) && (instruction
.type
!= ARM_MVN
))
418 Rn
= sim
->get_reg_mode(sim
, instruction
.info
.data_proc
.Rn
);
422 shifter_operand
= arm_shifter_operand(sim
, instruction
.info
.data_proc
.variant
, instruction
.info
.data_proc
.shifter_operand
, &carry_out
);
424 /* adjust Rn in case the PC is being read */
425 if (instruction
.info
.data_proc
.Rn
== 15)
426 Rn
+= 2 * instruction_size
;
428 if (instruction
.type
== ARM_AND
)
429 Rd
= Rn
& shifter_operand
;
430 else if (instruction
.type
== ARM_EOR
)
431 Rd
= Rn
^ shifter_operand
;
432 else if (instruction
.type
== ARM_SUB
)
433 Rd
= Rn
- shifter_operand
;
434 else if (instruction
.type
== ARM_RSB
)
435 Rd
= shifter_operand
- Rn
;
436 else if (instruction
.type
== ARM_ADD
)
437 Rd
= Rn
+ shifter_operand
;
438 else if (instruction
.type
== ARM_ADC
)
439 Rd
= Rn
+ shifter_operand
+ (C
& 1);
440 else if (instruction
.type
== ARM_SBC
)
441 Rd
= Rn
- shifter_operand
- (C
& 1) ? 0 : 1;
442 else if (instruction
.type
== ARM_RSC
)
443 Rd
= shifter_operand
- Rn
- (C
& 1) ? 0 : 1;
444 else if (instruction
.type
== ARM_ORR
)
445 Rd
= Rn
| shifter_operand
;
446 else if (instruction
.type
== ARM_BIC
)
447 Rd
= Rn
& ~(shifter_operand
);
448 else if (instruction
.type
== ARM_MOV
)
449 Rd
= shifter_operand
;
450 else if (instruction
.type
== ARM_MVN
)
451 Rd
= ~shifter_operand
;
453 LOG_WARNING("unhandled instruction type");
457 if (instruction
.info
.data_proc
.Rd
== 15)
464 *dry_run_pc
= current_pc
+ instruction_size
;
471 sim
->set_reg_mode(sim
, instruction
.info
.data_proc
.Rd
, Rd
);
472 LOG_WARNING("no updating of flags yet");
474 if (instruction
.info
.data_proc
.Rd
== 15)
478 /* compare instructions (CMP, CMN, TST, TEQ) */
479 else if ((instruction
.type
>= ARM_TST
) && (instruction
.type
<= ARM_CMN
))
483 *dry_run_pc
= current_pc
+ instruction_size
;
488 LOG_WARNING("no updating of flags yet");
491 /* load register instructions */
492 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
494 uint32_t load_address
= 0, modified_address
= 0, load_value
;
495 uint32_t Rn
= sim
->get_reg_mode(sim
, instruction
.info
.load_store
.Rn
);
497 /* adjust Rn in case the PC is being read */
498 if (instruction
.info
.load_store
.Rn
== 15)
499 Rn
+= 2 * instruction_size
;
501 if (instruction
.info
.load_store
.offset_mode
== 0)
503 if (instruction
.info
.load_store
.U
)
504 modified_address
= Rn
+ instruction
.info
.load_store
.offset
.offset
;
506 modified_address
= Rn
- instruction
.info
.load_store
.offset
.offset
;
508 else if (instruction
.info
.load_store
.offset_mode
== 1)
511 uint32_t Rm
= sim
->get_reg_mode(sim
, instruction
.info
.load_store
.offset
.reg
.Rm
);
512 uint8_t shift
= instruction
.info
.load_store
.offset
.reg
.shift
;
513 uint8_t shift_imm
= instruction
.info
.load_store
.offset
.reg
.shift_imm
;
514 uint8_t carry
= sim
->get_cpsr(sim
, 29, 1);
516 offset
= arm_shift(shift
, Rm
, shift_imm
, &carry
);
518 if (instruction
.info
.load_store
.U
)
519 modified_address
= Rn
+ offset
;
521 modified_address
= Rn
- offset
;
525 LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
528 if (instruction
.info
.load_store
.index_mode
== 0)
531 * we load from the modified address, but don't change the base address register */
532 load_address
= modified_address
;
533 modified_address
= Rn
;
535 else if (instruction
.info
.load_store
.index_mode
== 1)
538 * we load from the modified address, and write it back to the base address register */
539 load_address
= modified_address
;
541 else if (instruction
.info
.load_store
.index_mode
== 2)
544 * we load from the unmodified address, and write the modified address back */
548 if ((!dry_run_pc
) || (instruction
.info
.load_store
.Rd
== 15))
550 if ((retval
= target_read_u32(target
, load_address
, &load_value
)) != ERROR_OK
)
558 if (instruction
.info
.load_store
.Rd
== 15)
560 *dry_run_pc
= load_value
;
565 *dry_run_pc
= current_pc
+ instruction_size
;
572 if ((instruction
.info
.load_store
.index_mode
== 1) ||
573 (instruction
.info
.load_store
.index_mode
== 2))
575 sim
->set_reg_mode(sim
, instruction
.info
.load_store
.Rn
, modified_address
);
577 sim
->set_reg_mode(sim
, instruction
.info
.load_store
.Rd
, load_value
);
579 if (instruction
.info
.load_store
.Rd
== 15)
583 /* load multiple instruction */
584 else if (instruction
.type
== ARM_LDM
)
587 uint32_t Rn
= sim
->get_reg_mode(sim
, instruction
.info
.load_store_multiple
.Rn
);
588 uint32_t load_values
[16];
591 for (i
= 0; i
< 16; i
++)
593 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
597 switch (instruction
.info
.load_store_multiple
.addressing_mode
)
599 case 0: /* Increment after */
602 case 1: /* Increment before */
605 case 2: /* Decrement after */
606 Rn
= Rn
- (bits_set
* 4) + 4;
608 case 3: /* Decrement before */
609 Rn
= Rn
- (bits_set
* 4);
613 for (i
= 0; i
< 16; i
++)
615 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
617 if ((!dry_run_pc
) || (i
== 15))
619 target_read_u32(target
, Rn
, &load_values
[i
]);
627 if (instruction
.info
.load_store_multiple
.register_list
& 0x8000)
629 *dry_run_pc
= load_values
[15];
635 enum armv4_5_mode mode
= sim
->get_mode(sim
);
638 if (instruction
.info
.load_store_multiple
.S
)
640 if (instruction
.info
.load_store_multiple
.register_list
& 0x8000)
643 mode
= ARMV4_5_MODE_USR
;
646 for (i
= 0; i
< 16; i
++)
648 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
650 sim
->set_reg_mode(sim
, i
, load_values
[i
]);
656 uint32_t spsr
= sim
->get_reg_mode(sim
, 16);
657 sim
->set_reg(sim
, ARMV4_5_CPSR
, spsr
);
660 /* base register writeback */
661 if (instruction
.info
.load_store_multiple
.W
)
662 sim
->set_reg_mode(sim
, instruction
.info
.load_store_multiple
.Rn
, Rn
);
664 if (instruction
.info
.load_store_multiple
.register_list
& 0x8000)
668 /* store multiple instruction */
669 else if (instruction
.type
== ARM_STM
)
675 /* STM wont affect PC (advance by instruction size */
679 uint32_t Rn
= sim
->get_reg_mode(sim
, instruction
.info
.load_store_multiple
.Rn
);
681 enum armv4_5_mode mode
= sim
->get_mode(sim
);
683 for (i
= 0; i
< 16; i
++)
685 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
689 if (instruction
.info
.load_store_multiple
.S
)
691 mode
= ARMV4_5_MODE_USR
;
694 switch (instruction
.info
.load_store_multiple
.addressing_mode
)
696 case 0: /* Increment after */
699 case 1: /* Increment before */
702 case 2: /* Decrement after */
703 Rn
= Rn
- (bits_set
* 4) + 4;
705 case 3: /* Decrement before */
706 Rn
= Rn
- (bits_set
* 4);
710 for (i
= 0; i
< 16; i
++)
712 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
714 target_write_u32(target
, Rn
, sim
->get_reg_mode(sim
, i
));
719 /* base register writeback */
720 if (instruction
.info
.load_store_multiple
.W
)
721 sim
->set_reg_mode(sim
, instruction
.info
.load_store_multiple
.Rn
, Rn
);
725 else if (!dry_run_pc
)
727 /* the instruction wasn't handled, but we're supposed to simulate it
729 LOG_ERROR("Unimplemented instruction, could not simulate it.");
735 *dry_run_pc
= current_pc
+ instruction_size
;
740 sim
->set_reg(sim
, 15, current_pc
+ instruction_size
);
746 static uint32_t armv4_5_get_reg(struct arm_sim_interface
*sim
, int reg
)
748 armv4_5_common_t
*armv4_5
= (armv4_5_common_t
*)sim
->user_data
;
750 return buf_get_u32(armv4_5
->core_cache
->reg_list
[reg
].value
, 0, 32);
753 static void armv4_5_set_reg(struct arm_sim_interface
*sim
, int reg
, uint32_t value
)
755 armv4_5_common_t
*armv4_5
= (armv4_5_common_t
*)sim
->user_data
;
757 buf_set_u32(armv4_5
->core_cache
->reg_list
[reg
].value
, 0, 32, value
);
760 static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface
*sim
, int reg
)
762 armv4_5_common_t
*armv4_5
= (armv4_5_common_t
*)sim
->user_data
;
764 return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, reg
).value
, 0, 32);
767 static void armv4_5_set_reg_mode(struct arm_sim_interface
*sim
, int reg
, uint32_t value
)
769 armv4_5_common_t
*armv4_5
= (armv4_5_common_t
*)sim
->user_data
;
771 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, reg
).value
, 0, 32, value
);
774 static uint32_t armv4_5_get_cpsr(struct arm_sim_interface
*sim
, int pos
, int bits
)
776 armv4_5_common_t
*armv4_5
= (armv4_5_common_t
*)sim
->user_data
;
778 return buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, pos
, bits
);
781 static enum armv4_5_state
armv4_5_get_state(struct arm_sim_interface
*sim
)
783 armv4_5_common_t
*armv4_5
= (armv4_5_common_t
*)sim
->user_data
;
785 return armv4_5
->core_state
;
788 static void armv4_5_set_state(struct arm_sim_interface
*sim
, enum armv4_5_state mode
)
790 armv4_5_common_t
*armv4_5
= (armv4_5_common_t
*)sim
->user_data
;
792 armv4_5
->core_state
= mode
;
796 static enum armv4_5_mode
armv4_5_get_mode(struct arm_sim_interface
*sim
)
798 armv4_5_common_t
*armv4_5
= (armv4_5_common_t
*)sim
->user_data
;
800 return armv4_5
->core_mode
;
805 int arm_simulate_step(target_t
*target
, uint32_t *dry_run_pc
)
807 armv4_5_common_t
*armv4_5
= target
->arch_info
;
809 struct arm_sim_interface sim
;
811 sim
.user_data
=armv4_5
;
812 sim
.get_reg
=&armv4_5_get_reg
;
813 sim
.set_reg
=&armv4_5_set_reg
;
814 sim
.get_reg_mode
=&armv4_5_get_reg_mode
;
815 sim
.set_reg_mode
=&armv4_5_set_reg_mode
;
816 sim
.get_cpsr
=&armv4_5_get_cpsr
;
817 sim
.get_mode
=&armv4_5_get_mode
;
818 sim
.get_state
=&armv4_5_get_state
;
819 sim
.set_state
=&armv4_5_set_state
;
821 return arm_simulate_step_core(target
, dry_run_pc
, &sim
);
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