1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
60 * Relevant specifications from ARM include:
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "jtag/interface.h"
75 #include "arm_adi_v5.h"
77 #include "transport/transport.h"
78 #include <helper/jep106.h>
79 #include <helper/time_support.h>
80 #include <helper/list.h>
81 #include <helper/jim-nvp.h>
83 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
86 uint32_t tar_block_size(uint32_t address)
87 Return the largest block starting at address that does not cross a tar block size alignment boundary
89 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
91 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
94 /***************************************************************************
96 * DP and MEM-AP register access through APACC and DPACC *
98 ***************************************************************************/
100 static int mem_ap_setup_csw(struct adiv5_ap
*ap
, uint32_t csw
)
102 csw
|= ap
->csw_default
;
104 if (csw
!= ap
->csw_value
) {
105 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
106 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_CSW
, csw
);
107 if (retval
!= ERROR_OK
) {
116 static int mem_ap_setup_tar(struct adiv5_ap
*ap
, uint32_t tar
)
118 if (!ap
->tar_valid
|| tar
!= ap
->tar_value
) {
119 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
120 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR
, tar
);
121 if (retval
!= ERROR_OK
) {
122 ap
->tar_valid
= false;
126 ap
->tar_valid
= true;
131 static int mem_ap_read_tar(struct adiv5_ap
*ap
, uint32_t *tar
)
133 int retval
= dap_queue_ap_read(ap
, MEM_AP_REG_TAR
, tar
);
134 if (retval
!= ERROR_OK
) {
135 ap
->tar_valid
= false;
139 retval
= dap_run(ap
->dap
);
140 if (retval
!= ERROR_OK
) {
141 ap
->tar_valid
= false;
145 ap
->tar_value
= *tar
;
146 ap
->tar_valid
= true;
150 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap
*ap
)
152 switch (ap
->csw_value
& CSW_ADDRINC_MASK
) {
153 case CSW_ADDRINC_SINGLE
:
154 switch (ap
->csw_value
& CSW_SIZE_MASK
) {
164 case CSW_ADDRINC_PACKED
:
170 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
172 static void mem_ap_update_tar_cache(struct adiv5_ap
*ap
)
177 uint32_t inc
= mem_ap_get_tar_increment(ap
);
178 if (inc
>= max_tar_block_size(ap
->tar_autoincr_block
, ap
->tar_value
))
179 ap
->tar_valid
= false;
181 ap
->tar_value
+= inc
;
185 * Queue transactions setting up transfer parameters for the
186 * currently selected MEM-AP.
188 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
189 * initiate data reads or writes using memory or peripheral addresses.
190 * If the CSW is configured for it, the TAR may be automatically
191 * incremented after each transfer.
193 * @param ap The MEM-AP.
194 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
195 * matches the cached value, the register is not changed.
196 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
197 * matches the cached address, the register is not changed.
199 * @return ERROR_OK if the transaction was properly queued, else a fault code.
201 static int mem_ap_setup_transfer(struct adiv5_ap
*ap
, uint32_t csw
, uint32_t tar
)
204 retval
= mem_ap_setup_csw(ap
, csw
);
205 if (retval
!= ERROR_OK
)
207 retval
= mem_ap_setup_tar(ap
, tar
);
208 if (retval
!= ERROR_OK
)
214 * Asynchronous (queued) read of a word from memory or a system register.
216 * @param ap The MEM-AP to access.
217 * @param address Address of the 32-bit word to read; it must be
218 * readable by the currently selected MEM-AP.
219 * @param value points to where the word will be stored when the
220 * transaction queue is flushed (assuming no errors).
222 * @return ERROR_OK for success. Otherwise a fault code.
224 int mem_ap_read_u32(struct adiv5_ap
*ap
, uint32_t address
,
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when reading several consecutive addresses.
232 retval
= mem_ap_setup_transfer(ap
,
233 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
234 address
& 0xFFFFFFF0);
235 if (retval
!= ERROR_OK
)
238 return dap_queue_ap_read(ap
, MEM_AP_REG_BD0
| (address
& 0xC), value
);
242 * Synchronous read of a word from memory or a system register.
243 * As a side effect, this flushes any queued transactions.
245 * @param ap The MEM-AP to access.
246 * @param address Address of the 32-bit word to read; it must be
247 * readable by the currently selected MEM-AP.
248 * @param value points to where the result will be stored.
250 * @return ERROR_OK for success; *value holds the result.
251 * Otherwise a fault code.
253 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
258 retval
= mem_ap_read_u32(ap
, address
, value
);
259 if (retval
!= ERROR_OK
)
262 return dap_run(ap
->dap
);
266 * Asynchronous (queued) write of a word to memory or a system register.
268 * @param ap The MEM-AP to access.
269 * @param address Address to be written; it must be writable by
270 * the currently selected MEM-AP.
271 * @param value Word that will be written to the address when transaction
272 * queue is flushed (assuming no errors).
274 * @return ERROR_OK for success. Otherwise a fault code.
276 int mem_ap_write_u32(struct adiv5_ap
*ap
, uint32_t address
,
281 /* Use banked addressing (REG_BDx) to avoid some link traffic
282 * (updating TAR) when writing several consecutive addresses.
284 retval
= mem_ap_setup_transfer(ap
,
285 CSW_32BIT
| (ap
->csw_value
& CSW_ADDRINC_MASK
),
286 address
& 0xFFFFFFF0);
287 if (retval
!= ERROR_OK
)
290 return dap_queue_ap_write(ap
, MEM_AP_REG_BD0
| (address
& 0xC),
295 * Synchronous write of a word to memory or a system register.
296 * As a side effect, this flushes any queued transactions.
298 * @param ap The MEM-AP to access.
299 * @param address Address to be written; it must be writable by
300 * the currently selected MEM-AP.
301 * @param value Word that will be written.
303 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
305 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
308 int retval
= mem_ap_write_u32(ap
, address
, value
);
310 if (retval
!= ERROR_OK
)
313 return dap_run(ap
->dap
);
317 * Synchronous write of a block of memory, using a specific access size.
319 * @param ap The MEM-AP to access.
320 * @param buffer The data buffer to write. No particular alignment is assumed.
321 * @param size Which access size to use, in bytes. 1, 2 or 4.
322 * @param count The number of writes to do (in size units, not bytes).
323 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
324 * @param addrinc Whether the target address should be increased for each write or not. This
325 * should normally be true, except when writing to e.g. a FIFO.
326 * @return ERROR_OK on success, otherwise an error code.
328 static int mem_ap_write(struct adiv5_ap
*ap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
329 uint32_t address
, bool addrinc
)
331 struct adiv5_dap
*dap
= ap
->dap
;
332 size_t nbytes
= size
* count
;
333 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
336 int retval
= ERROR_OK
;
338 /* TI BE-32 Quirks mode:
339 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
340 * size write address bytes written in order
341 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
342 * 2 TAR ^ 2 (val >> 8), (val)
344 * For example, if you attempt to write a single byte to address 0, the processor
345 * will actually write a byte to address 3.
347 * To make writes of size < 4 work as expected, we xor a value with the address before
348 * setting the TAP, and we set the TAP after every transfer rather then relying on
349 * address increment. */
352 csw_size
= CSW_32BIT
;
354 } else if (size
== 2) {
355 csw_size
= CSW_16BIT
;
356 addr_xor
= dap
->ti_be_32_quirks
? 2 : 0;
357 } else if (size
== 1) {
359 addr_xor
= dap
->ti_be_32_quirks
? 3 : 0;
361 return ERROR_TARGET_UNALIGNED_ACCESS
;
364 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
365 return ERROR_TARGET_UNALIGNED_ACCESS
;
368 uint32_t this_size
= size
;
370 /* Select packed transfer if possible */
371 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
372 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
374 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
376 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
379 if (retval
!= ERROR_OK
)
382 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
383 if (retval
!= ERROR_OK
)
386 /* How many source bytes each transfer will consume, and their location in the DRW,
387 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
388 uint32_t outvalue
= 0;
389 uint32_t drw_byte_idx
= address
;
390 if (dap
->ti_be_32_quirks
) {
393 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
394 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
395 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
396 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (drw_byte_idx
& 3) ^ addr_xor
);
399 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (drw_byte_idx
++ & 3) ^ addr_xor
);
400 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (drw_byte_idx
& 3) ^ addr_xor
);
403 outvalue
|= (uint32_t)*buffer
++ << 8 * (0 ^ (drw_byte_idx
& 3) ^ addr_xor
);
409 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
410 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
413 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
++ & 3);
416 outvalue
|= (uint32_t)*buffer
++ << 8 * (drw_byte_idx
& 3);
422 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_DRW
, outvalue
);
423 if (retval
!= ERROR_OK
)
426 mem_ap_update_tar_cache(ap
);
428 address
+= this_size
;
431 /* REVISIT: Might want to have a queued version of this function that does not run. */
432 if (retval
== ERROR_OK
)
433 retval
= dap_run(dap
);
435 if (retval
!= ERROR_OK
) {
437 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
)
438 LOG_ERROR("Failed to write memory at 0x%08"PRIx32
, tar
);
440 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
447 * Synchronous read of a block of memory, using a specific access size.
449 * @param ap The MEM-AP to access.
450 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
451 * @param size Which access size to use, in bytes. 1, 2 or 4.
452 * @param count The number of reads to do (in size units, not bytes).
453 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
454 * @param addrinc Whether the target address should be increased after each read or not. This
455 * should normally be true, except when reading from e.g. a FIFO.
456 * @return ERROR_OK on success, otherwise an error code.
458 static int mem_ap_read(struct adiv5_ap
*ap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
459 uint32_t adr
, bool addrinc
)
461 struct adiv5_dap
*dap
= ap
->dap
;
462 size_t nbytes
= size
* count
;
463 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
465 uint32_t address
= adr
;
466 int retval
= ERROR_OK
;
468 /* TI BE-32 Quirks mode:
469 * Reads on big-endian TMS570 behave strangely differently than writes.
470 * They read from the physical address requested, but with DRW byte-reversed.
471 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
472 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
476 csw_size
= CSW_32BIT
;
478 csw_size
= CSW_16BIT
;
482 return ERROR_TARGET_UNALIGNED_ACCESS
;
484 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
485 return ERROR_TARGET_UNALIGNED_ACCESS
;
487 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
488 * over-allocation if packed transfers are going to be used, but determining the real need at
489 * this point would be messy. */
490 uint32_t *read_buf
= calloc(count
, sizeof(uint32_t));
491 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
492 uint32_t *read_ptr
= read_buf
;
493 if (read_buf
== NULL
) {
494 LOG_ERROR("Failed to allocate read buffer");
498 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
499 * useful bytes it contains, and their location in the word, depends on the type of transfer
502 uint32_t this_size
= size
;
504 /* Select packed transfer if possible */
505 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
506 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
508 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
510 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
512 if (retval
!= ERROR_OK
)
515 retval
= mem_ap_setup_tar(ap
, address
);
516 if (retval
!= ERROR_OK
)
519 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_DRW
, read_ptr
++);
520 if (retval
!= ERROR_OK
)
525 address
+= this_size
;
527 mem_ap_update_tar_cache(ap
);
530 if (retval
== ERROR_OK
)
531 retval
= dap_run(dap
);
535 nbytes
= size
* count
;
538 /* If something failed, read TAR to find out how much data was successfully read, so we can
539 * at least give the caller what we have. */
540 if (retval
!= ERROR_OK
) {
542 if (mem_ap_read_tar(ap
, &tar
) == ERROR_OK
) {
543 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
544 LOG_ERROR("Failed to read memory at 0x%08"PRIx32
, tar
);
545 if (nbytes
> tar
- address
)
546 nbytes
= tar
- address
;
548 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
553 /* Replay loop to populate caller's buffer from the correct word and byte lane */
555 uint32_t this_size
= size
;
557 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
558 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
562 if (dap
->ti_be_32_quirks
) {
565 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
566 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
569 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
572 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
577 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
578 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
581 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
584 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
596 int mem_ap_read_buf(struct adiv5_ap
*ap
,
597 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
599 return mem_ap_read(ap
, buffer
, size
, count
, address
, true);
602 int mem_ap_write_buf(struct adiv5_ap
*ap
,
603 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
605 return mem_ap_write(ap
, buffer
, size
, count
, address
, true);
608 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
609 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
611 return mem_ap_read(ap
, buffer
, size
, count
, address
, false);
614 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
615 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
617 return mem_ap_write(ap
, buffer
, size
, count
, address
, false);
620 /*--------------------------------------------------------------------------*/
623 #define DAP_POWER_DOMAIN_TIMEOUT (10)
625 /*--------------------------------------------------------------------------*/
628 * Invalidate cached DP select and cached TAR and CSW of all APs
630 void dap_invalidate_cache(struct adiv5_dap
*dap
)
632 dap
->select
= DP_SELECT_INVALID
;
633 dap
->last_read
= NULL
;
636 for (i
= 0; i
<= 255; i
++) {
637 /* force csw and tar write on the next mem-ap access */
638 dap
->ap
[i
].tar_valid
= false;
639 dap
->ap
[i
].csw_value
= 0;
644 * Initialize a DAP. This sets up the power domains, prepares the DP
645 * for further use and activates overrun checking.
647 * @param dap The DAP being initialized.
649 int dap_dp_init(struct adiv5_dap
*dap
)
653 LOG_DEBUG("%s", adiv5_dap_name(dap
));
655 dap_invalidate_cache(dap
);
658 * Early initialize dap->dp_ctrl_stat.
659 * In jtag mode only, if the following atomic reads fail and set the
660 * sticky error, it will trigger the clearing of the sticky. Without this
661 * initialization system and debug power would be disabled while clearing
662 * the sticky error bit.
664 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
666 for (size_t i
= 0; i
< 30; i
++) {
667 /* DP initialization */
669 retval
= dap_dp_read_atomic(dap
, DP_CTRL_STAT
, NULL
);
670 if (retval
== ERROR_OK
)
675 * This write operation clears the sticky error bit in jtag mode only and
676 * is ignored in swd mode. It also powers-up system and debug domains in
677 * both jtag and swd modes, if not done before.
678 * Actually we do not need to clear the sticky error here because it has
679 * been already cleared (if it was set) in the previous atomic read. This
680 * write could be removed, but this initial part of dap_dp_init() is the
681 * result of years of fine tuning and there are strong concerns about any
682 * unnecessary code change. It doesn't harm, so let's keep it here and
683 * preserve the historical sequence of read/write operations!
685 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
| SSTICKYERR
);
686 if (retval
!= ERROR_OK
)
689 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
690 if (retval
!= ERROR_OK
)
693 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
694 if (retval
!= ERROR_OK
)
697 /* Check that we have debug power domains activated */
698 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
699 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
700 CDBGPWRUPACK
, CDBGPWRUPACK
,
701 DAP_POWER_DOMAIN_TIMEOUT
);
702 if (retval
!= ERROR_OK
)
705 if (!dap
->ignore_syspwrupack
) {
706 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
707 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
708 CSYSPWRUPACK
, CSYSPWRUPACK
,
709 DAP_POWER_DOMAIN_TIMEOUT
);
710 if (retval
!= ERROR_OK
)
714 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
715 if (retval
!= ERROR_OK
)
718 /* With debug power on we can activate OVERRUN checking */
719 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
720 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
721 if (retval
!= ERROR_OK
)
723 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
724 if (retval
!= ERROR_OK
)
727 retval
= dap_run(dap
);
728 if (retval
!= ERROR_OK
)
735 * Initialize a DAP. This sets up the power domains, prepares the DP
736 * for further use, and arranges to use AP #0 for all AP operations
737 * until dap_ap-select() changes that policy.
739 * @param ap The MEM-AP being initialized.
741 int mem_ap_init(struct adiv5_ap
*ap
)
743 /* check that we support packed transfers */
746 struct adiv5_dap
*dap
= ap
->dap
;
748 ap
->tar_valid
= false;
749 ap
->csw_value
= 0; /* force csw and tar write */
750 retval
= mem_ap_setup_transfer(ap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, 0);
751 if (retval
!= ERROR_OK
)
754 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CSW
, &csw
);
755 if (retval
!= ERROR_OK
)
758 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG
, &cfg
);
759 if (retval
!= ERROR_OK
)
762 retval
= dap_run(dap
);
763 if (retval
!= ERROR_OK
)
766 if (csw
& CSW_ADDRINC_PACKED
)
767 ap
->packed_transfers
= true;
769 ap
->packed_transfers
= false;
771 /* Packed transfers on TI BE-32 processors do not work correctly in
773 if (dap
->ti_be_32_quirks
)
774 ap
->packed_transfers
= false;
776 LOG_DEBUG("MEM_AP Packed Transfers: %s",
777 ap
->packed_transfers
? "enabled" : "disabled");
779 /* The ARM ADI spec leaves implementation-defined whether unaligned
780 * memory accesses work, only work partially, or cause a sticky error.
781 * On TI BE-32 processors, reads seem to return garbage in some bytes
782 * and unaligned writes seem to cause a sticky error.
783 * TODO: it would be nice to have a way to detect whether unaligned
784 * operations are supported on other processors. */
785 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
787 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
788 !!(cfg
& 0x04), !!(cfg
& 0x02), !!(cfg
& 0x01));
794 * Put the debug link into SWD mode, if the target supports it.
795 * The link's initial mode may be either JTAG (for example,
796 * with SWJ-DP after reset) or SWD.
798 * Note that targets using the JTAG-DP do not support SWD, and that
799 * some targets which could otherwise support it may have been
800 * configured to disable SWD signaling
802 * @param dap The DAP used
803 * @return ERROR_OK or else a fault code.
805 int dap_to_swd(struct adiv5_dap
*dap
)
809 LOG_DEBUG("Enter SWD mode");
811 if (transport_is_jtag()) {
812 retval
= jtag_add_tms_seq(swd_seq_jtag_to_swd_len
,
813 swd_seq_jtag_to_swd
, TAP_INVALID
);
814 if (retval
== ERROR_OK
)
815 retval
= jtag_execute_queue();
819 if (transport_is_swd()) {
820 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
822 return swd
->switch_seq(JTAG_TO_SWD
);
825 LOG_ERROR("Nor JTAG nor SWD transport");
830 * Put the debug link into JTAG mode, if the target supports it.
831 * The link's initial mode may be either SWD or JTAG.
833 * Note that targets implemented with SW-DP do not support JTAG, and
834 * that some targets which could otherwise support it may have been
835 * configured to disable JTAG signaling
837 * @param dap The DAP used
838 * @return ERROR_OK or else a fault code.
840 int dap_to_jtag(struct adiv5_dap
*dap
)
844 LOG_DEBUG("Enter JTAG mode");
846 if (transport_is_jtag()) {
847 retval
= jtag_add_tms_seq(swd_seq_swd_to_jtag_len
,
848 swd_seq_swd_to_jtag
, TAP_RESET
);
849 if (retval
== ERROR_OK
)
850 retval
= jtag_execute_queue();
854 if (transport_is_swd()) {
855 const struct swd_driver
*swd
= adiv5_dap_swd_driver(dap
);
857 return swd
->switch_seq(SWD_TO_JTAG
);
860 LOG_ERROR("Nor JTAG nor SWD transport");
864 /* CID interpretation -- see ARM IHI 0029B section 3
865 * and ARM IHI 0031A table 13-3.
867 static const char *class_description
[16] = {
868 "Reserved", "ROM table", "Reserved", "Reserved",
869 "Reserved", "Reserved", "Reserved", "Reserved",
870 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
871 "Reserved", "OptimoDE DESS",
872 "Generic IP component", "PrimeCell or System component"
875 static bool is_dap_cid_ok(uint32_t cid
)
877 return (cid
& 0xffff0fff) == 0xb105000d;
881 * This function checks the ID for each access port to find the requested Access Port type
883 int dap_find_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, struct adiv5_ap
**ap_out
)
887 /* Maximum AP number is 255 since the SELECT register is 8 bits */
888 for (ap_num
= 0; ap_num
<= DP_APSEL_MAX
; ap_num
++) {
890 /* read the IDR register of the Access Port */
893 int retval
= dap_queue_ap_read(dap_ap(dap
, ap_num
), AP_REG_IDR
, &id_val
);
894 if (retval
!= ERROR_OK
)
897 retval
= dap_run(dap
);
901 * 27-24 : JEDEC bank (0x4 for ARM)
902 * 23-17 : JEDEC code (0x3B for ARM)
903 * 16-13 : Class (0b1000=Mem-AP)
905 * 7-4 : AP Variant (non-zero for JTAG-AP)
906 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
909 /* Reading register for a non-existant AP should not cause an error,
910 * but just to be sure, try to continue searching if an error does happen.
912 if ((retval
== ERROR_OK
) && /* Register read success */
913 ((id_val
& IDR_JEP106
) == IDR_JEP106_ARM
) && /* Jedec codes match */
914 ((id_val
& IDR_TYPE
) == type_to_find
)) { /* type matches*/
916 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
917 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
918 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
919 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
920 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown",
923 *ap_out
= &dap
->ap
[ap_num
];
928 LOG_DEBUG("No %s found",
929 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
930 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
931 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
932 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown");
936 int dap_get_debugbase(struct adiv5_ap
*ap
,
937 uint32_t *dbgbase
, uint32_t *apid
)
939 struct adiv5_dap
*dap
= ap
->dap
;
942 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE
, dbgbase
);
943 if (retval
!= ERROR_OK
)
945 retval
= dap_queue_ap_read(ap
, AP_REG_IDR
, apid
);
946 if (retval
!= ERROR_OK
)
948 retval
= dap_run(dap
);
949 if (retval
!= ERROR_OK
)
955 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
956 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
)
958 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
964 retval
= mem_ap_read_atomic_u32(ap
, (dbgbase
&0xFFFFF000) |
965 entry_offset
, &romentry
);
966 if (retval
!= ERROR_OK
)
969 component_base
= (dbgbase
& 0xFFFFF000)
970 + (romentry
& 0xFFFFF000);
972 if (romentry
& 0x1) {
974 retval
= mem_ap_read_atomic_u32(ap
, component_base
| 0xff4, &c_cid1
);
975 if (retval
!= ERROR_OK
) {
976 LOG_ERROR("Can't read component with base address 0x%" PRIx32
977 ", the corresponding core might be turned off", component_base
);
980 if (((c_cid1
>> 4) & 0x0f) == 1) {
981 retval
= dap_lookup_cs_component(ap
, component_base
,
983 if (retval
== ERROR_OK
)
985 if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
989 retval
= mem_ap_read_atomic_u32(ap
,
990 (component_base
& 0xfffff000) | 0xfcc,
992 if (retval
!= ERROR_OK
)
994 if ((devtype
& 0xff) == type
) {
996 *addr
= component_base
;
1003 } while (romentry
> 0);
1006 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1011 static int dap_read_part_id(struct adiv5_ap
*ap
, uint32_t component_base
, uint32_t *cid
, uint64_t *pid
)
1013 assert((component_base
& 0xFFF) == 0);
1014 assert(ap
!= NULL
&& cid
!= NULL
&& pid
!= NULL
);
1016 uint32_t cid0
, cid1
, cid2
, cid3
;
1017 uint32_t pid0
, pid1
, pid2
, pid3
, pid4
;
1020 /* IDs are in last 4K section */
1021 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE0, &pid0
);
1022 if (retval
!= ERROR_OK
)
1024 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE4, &pid1
);
1025 if (retval
!= ERROR_OK
)
1027 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFE8, &pid2
);
1028 if (retval
!= ERROR_OK
)
1030 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFEC, &pid3
);
1031 if (retval
!= ERROR_OK
)
1033 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFD0, &pid4
);
1034 if (retval
!= ERROR_OK
)
1036 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF0, &cid0
);
1037 if (retval
!= ERROR_OK
)
1039 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF4, &cid1
);
1040 if (retval
!= ERROR_OK
)
1042 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFF8, &cid2
);
1043 if (retval
!= ERROR_OK
)
1045 retval
= mem_ap_read_u32(ap
, component_base
+ 0xFFC, &cid3
);
1046 if (retval
!= ERROR_OK
)
1049 retval
= dap_run(ap
->dap
);
1050 if (retval
!= ERROR_OK
)
1053 *cid
= (cid3
& 0xff) << 24
1054 | (cid2
& 0xff) << 16
1055 | (cid1
& 0xff) << 8
1057 *pid
= (uint64_t)(pid4
& 0xff) << 32
1058 | (pid3
& 0xff) << 24
1059 | (pid2
& 0xff) << 16
1060 | (pid1
& 0xff) << 8
1066 /* The designer identity code is encoded as:
1067 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
1068 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
1069 * a legacy ASCII Identity Code.
1070 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
1071 * JEP106 is a standard available from jedec.org
1074 /* Part number interpretations are from Cortex
1075 * core specs, the CoreSight components TRM
1076 * (ARM DDI 0314H), CoreSight System Design
1077 * Guide (ARM DGI 0012D) and ETM specs; also
1078 * from chip observation (e.g. TI SDTI).
1081 /* The legacy code only used the part number field to identify CoreSight peripherals.
1082 * This meant that the same part number from two different manufacturers looked the same.
1083 * It is desirable for all future additions to identify with both part number and JEP106.
1084 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
1087 #define ANY_ID 0x1000
1089 #define ARM_ID 0x4BB
1091 static const struct {
1092 uint16_t designer_id
;
1096 } dap_partnums
[] = {
1097 { ARM_ID
, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1098 { ARM_ID
, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1099 { ARM_ID
, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1100 { ARM_ID
, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1101 { ARM_ID
, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1102 { ARM_ID
, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1103 { ARM_ID
, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1104 { ARM_ID
, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1105 { ARM_ID
, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1106 { ARM_ID
, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1107 { ARM_ID
, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1108 { ARM_ID
, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1109 { ARM_ID
, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1110 { ARM_ID
, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1111 { ARM_ID
, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1112 { ARM_ID
, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1113 { ARM_ID
, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1114 { ARM_ID
, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1115 { ARM_ID
, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1116 { ARM_ID
, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1117 { ARM_ID
, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1118 { ARM_ID
, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1119 { ARM_ID
, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1120 { ARM_ID
, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1121 { ARM_ID
, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1122 { ARM_ID
, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1123 { ARM_ID
, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1124 { ARM_ID
, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1125 { ARM_ID
, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1126 { ARM_ID
, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1127 { ARM_ID
, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1128 { ARM_ID
, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1129 { ARM_ID
, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1130 { ARM_ID
, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1131 { ARM_ID
, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1132 { ARM_ID
, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1133 { ARM_ID
, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1134 { ARM_ID
, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1135 { ARM_ID
, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1136 { ARM_ID
, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1137 { ARM_ID
, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1138 { ARM_ID
, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1139 { ARM_ID
, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1140 { ARM_ID
, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1141 { ARM_ID
, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1142 { ARM_ID
, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1143 { ARM_ID
, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1144 { ARM_ID
, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1145 { ARM_ID
, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1146 { ARM_ID
, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1147 { ARM_ID
, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1148 { ARM_ID
, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1149 { ARM_ID
, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1150 { ARM_ID
, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1151 { ARM_ID
, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1152 { ARM_ID
, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1153 { ARM_ID
, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1154 { ARM_ID
, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1155 { ARM_ID
, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1156 { ARM_ID
, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1157 { ARM_ID
, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1158 { ARM_ID
, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1159 { ARM_ID
, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1160 { ARM_ID
, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1161 { ARM_ID
, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1162 { ARM_ID
, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1163 { ARM_ID
, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1164 { ARM_ID
, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1165 { ARM_ID
, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1166 { ARM_ID
, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1167 { ARM_ID
, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1168 { ARM_ID
, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1169 { ARM_ID
, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1170 { ARM_ID
, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1171 { ARM_ID
, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1172 { ARM_ID
, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1173 { ARM_ID
, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1174 { ARM_ID
, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1175 { ARM_ID
, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1176 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1177 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1178 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1179 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1180 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1181 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1182 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1183 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1184 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1185 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1186 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1187 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1188 /* legacy comment: 0x113: what? */
1189 { ANY_ID
, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1190 { ANY_ID
, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1193 static int dap_rom_display(struct command_invocation
*cmd
,
1194 struct adiv5_ap
*ap
, uint32_t dbgbase
, int depth
)
1202 command_print(cmd
, "\tTables too deep");
1207 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
1209 uint32_t base_addr
= dbgbase
& 0xFFFFF000;
1210 command_print(cmd
, "\t\tComponent base address 0x%08" PRIx32
, base_addr
);
1212 retval
= dap_read_part_id(ap
, base_addr
, &cid
, &pid
);
1213 if (retval
!= ERROR_OK
) {
1214 command_print(cmd
, "\t\tCan't read component, the corresponding core might be turned off");
1215 return ERROR_OK
; /* Don't abort recursion */
1218 if (!is_dap_cid_ok(cid
)) {
1219 command_print(cmd
, "\t\tInvalid CID 0x%08" PRIx32
, cid
);
1220 return ERROR_OK
; /* Don't abort recursion */
1223 /* component may take multiple 4K pages */
1224 uint32_t size
= (pid
>> 36) & 0xf;
1226 command_print(cmd
, "\t\tStart address 0x%08" PRIx32
, (uint32_t)(base_addr
- 0x1000 * size
));
1228 command_print(cmd
, "\t\tPeripheral ID 0x%010" PRIx64
, pid
);
1230 uint8_t class = (cid
>> 12) & 0xf;
1231 uint16_t part_num
= pid
& 0xfff;
1232 uint16_t designer_id
= ((pid
>> 32) & 0xf) << 8 | ((pid
>> 12) & 0xff);
1234 if (designer_id
& 0x80) {
1236 command_print(cmd
, "\t\tDesigner is 0x%03" PRIx16
", %s",
1237 designer_id
, jep106_manufacturer(designer_id
>> 8, designer_id
& 0x7f));
1239 /* Legacy ASCII ID, clear invalid bits */
1240 designer_id
&= 0x7f;
1241 command_print(cmd
, "\t\tDesigner ASCII code 0x%02" PRIx16
", %s",
1242 designer_id
, designer_id
== 0x41 ? "ARM" : "<unknown>");
1245 /* default values to be overwritten upon finding a match */
1246 const char *type
= "Unrecognized";
1247 const char *full
= "";
1249 /* search dap_partnums[] array for a match */
1250 for (unsigned entry
= 0; entry
< ARRAY_SIZE(dap_partnums
); entry
++) {
1252 if ((dap_partnums
[entry
].designer_id
!= designer_id
) && (dap_partnums
[entry
].designer_id
!= ANY_ID
))
1255 if (dap_partnums
[entry
].part_num
!= part_num
)
1258 type
= dap_partnums
[entry
].type
;
1259 full
= dap_partnums
[entry
].full
;
1263 command_print(cmd
, "\t\tPart is 0x%" PRIx16
", %s %s", part_num
, type
, full
);
1264 command_print(cmd
, "\t\tComponent class is 0x%" PRIx8
", %s", class, class_description
[class]);
1266 if (class == 1) { /* ROM Table */
1268 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| 0xFCC, &memtype
);
1269 if (retval
!= ERROR_OK
)
1273 command_print(cmd
, "\t\tMEMTYPE system memory present on bus");
1275 command_print(cmd
, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1277 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1278 for (uint16_t entry_offset
= 0; entry_offset
< 0xF00; entry_offset
+= 4) {
1280 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| entry_offset
, &romentry
);
1281 if (retval
!= ERROR_OK
)
1283 command_print(cmd
, "\t%sROMTABLE[0x%x] = 0x%" PRIx32
"",
1284 tabs
, entry_offset
, romentry
);
1285 if (romentry
& 0x01) {
1287 retval
= dap_rom_display(cmd
, ap
, base_addr
+ (romentry
& 0xFFFFF000), depth
+ 1);
1288 if (retval
!= ERROR_OK
)
1290 } else if (romentry
!= 0) {
1291 command_print(cmd
, "\t\tComponent not present");
1293 command_print(cmd
, "\t%s\tEnd of ROM table", tabs
);
1297 } else if (class == 9) { /* CoreSight component */
1298 const char *major
= "Reserved", *subtype
= "Reserved";
1301 retval
= mem_ap_read_atomic_u32(ap
, base_addr
| 0xFCC, &devtype
);
1302 if (retval
!= ERROR_OK
)
1304 unsigned minor
= (devtype
>> 4) & 0x0f;
1305 switch (devtype
& 0x0f) {
1307 major
= "Miscellaneous";
1313 subtype
= "Validation component";
1318 major
= "Trace Sink";
1335 major
= "Trace Link";
1341 subtype
= "Funnel, router";
1347 subtype
= "FIFO, buffer";
1352 major
= "Trace Source";
1358 subtype
= "Processor";
1364 subtype
= "Engine/Coprocessor";
1370 subtype
= "Software";
1375 major
= "Debug Control";
1381 subtype
= "Trigger Matrix";
1384 subtype
= "Debug Auth";
1387 subtype
= "Power Requestor";
1392 major
= "Debug Logic";
1398 subtype
= "Processor";
1404 subtype
= "Engine/Coprocessor";
1415 major
= "Performance Monitor";
1421 subtype
= "Processor";
1427 subtype
= "Engine/Coprocessor";
1438 command_print(cmd
, "\t\tType is 0x%02" PRIx8
", %s, %s",
1439 (uint8_t)(devtype
& 0xff),
1441 /* REVISIT also show 0xfc8 DevId */
1447 int dap_info_command(struct command_invocation
*cmd
,
1448 struct adiv5_ap
*ap
)
1451 uint32_t dbgbase
, apid
;
1454 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1455 retval
= dap_get_debugbase(ap
, &dbgbase
, &apid
);
1456 if (retval
!= ERROR_OK
)
1459 command_print(cmd
, "AP ID register 0x%8.8" PRIx32
, apid
);
1461 command_print(cmd
, "No AP found at this ap 0x%x", ap
->ap_num
);
1465 switch (apid
& (IDR_JEP106
| IDR_TYPE
)) {
1466 case IDR_JEP106_ARM
| AP_TYPE_JTAG_AP
:
1467 command_print(cmd
, "\tType is JTAG-AP");
1469 case IDR_JEP106_ARM
| AP_TYPE_AHB_AP
:
1470 command_print(cmd
, "\tType is MEM-AP AHB");
1472 case IDR_JEP106_ARM
| AP_TYPE_APB_AP
:
1473 command_print(cmd
, "\tType is MEM-AP APB");
1475 case IDR_JEP106_ARM
| AP_TYPE_AXI_AP
:
1476 command_print(cmd
, "\tType is MEM-AP AXI");
1479 command_print(cmd
, "\tUnknown AP type");
1483 /* NOTE: a MEM-AP may have a single CoreSight component that's
1484 * not a ROM table ... or have no such components at all.
1486 mem_ap
= (apid
& IDR_CLASS
) == AP_CLASS_MEM_AP
;
1488 command_print(cmd
, "MEM-AP BASE 0x%8.8" PRIx32
, dbgbase
);
1490 if (dbgbase
== 0xFFFFFFFF || (dbgbase
& 0x3) == 0x2) {
1491 command_print(cmd
, "\tNo ROM table present");
1494 command_print(cmd
, "\tValid ROM table present");
1496 command_print(cmd
, "\tROM table in legacy format");
1498 dap_rom_display(cmd
, ap
, dbgbase
& 0xFFFFF000, 0);
1505 enum adiv5_cfg_param
{
1510 static const Jim_Nvp nvp_config_opts
[] = {
1511 { .name
= "-dap", .value
= CFG_DAP
},
1512 { .name
= "-ap-num", .value
= CFG_AP_NUM
},
1513 { .name
= NULL
, .value
= -1 }
1516 int adiv5_jim_configure(struct target
*target
, Jim_GetOptInfo
*goi
)
1518 struct adiv5_private_config
*pc
;
1521 pc
= (struct adiv5_private_config
*)target
->private_config
;
1523 pc
= calloc(1, sizeof(struct adiv5_private_config
));
1524 pc
->ap_num
= DP_APSEL_INVALID
;
1525 target
->private_config
= pc
;
1528 target
->has_dap
= true;
1530 if (goi
->argc
> 0) {
1533 Jim_SetEmptyResult(goi
->interp
);
1535 /* check first if topmost item is for us */
1536 e
= Jim_Nvp_name2value_obj(goi
->interp
, nvp_config_opts
,
1539 return JIM_CONTINUE
;
1541 e
= Jim_GetOpt_Obj(goi
, NULL
);
1547 if (goi
->isconfigure
) {
1549 struct adiv5_dap
*dap
;
1550 e
= Jim_GetOpt_Obj(goi
, &o_t
);
1553 dap
= dap_instance_by_jim_obj(goi
->interp
, o_t
);
1555 Jim_SetResultString(goi
->interp
, "DAP name invalid!", -1);
1558 if (pc
->dap
!= NULL
&& pc
->dap
!= dap
) {
1559 Jim_SetResultString(goi
->interp
,
1560 "DAP assignment cannot be changed after target was created!", -1);
1563 if (target
->tap_configured
) {
1564 Jim_SetResultString(goi
->interp
,
1565 "-chain-position and -dap configparams are mutually exclusive!", -1);
1569 target
->tap
= dap
->tap
;
1570 target
->dap_configured
= true;
1572 if (goi
->argc
!= 0) {
1573 Jim_WrongNumArgs(goi
->interp
,
1574 goi
->argc
, goi
->argv
,
1579 if (pc
->dap
== NULL
) {
1580 Jim_SetResultString(goi
->interp
, "DAP not configured", -1);
1583 Jim_SetResultString(goi
->interp
, adiv5_dap_name(pc
->dap
), -1);
1588 if (goi
->isconfigure
) {
1590 e
= Jim_GetOpt_Wide(goi
, &ap_num
);
1593 if (ap_num
< 0 || ap_num
> DP_APSEL_MAX
) {
1594 Jim_SetResultString(goi
->interp
, "Invalid AP number!", -1);
1597 pc
->ap_num
= ap_num
;
1599 if (goi
->argc
!= 0) {
1600 Jim_WrongNumArgs(goi
->interp
,
1601 goi
->argc
, goi
->argv
,
1606 if (pc
->ap_num
== DP_APSEL_INVALID
) {
1607 Jim_SetResultString(goi
->interp
, "AP number not configured", -1);
1610 Jim_SetResult(goi
->interp
, Jim_NewIntObj(goi
->interp
, pc
->ap_num
));
1619 int adiv5_verify_config(struct adiv5_private_config
*pc
)
1624 if (pc
->dap
== NULL
)
1631 COMMAND_HANDLER(handle_dap_info_command
)
1633 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1641 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1642 if (apsel
> DP_APSEL_MAX
)
1643 return ERROR_COMMAND_SYNTAX_ERROR
;
1646 return ERROR_COMMAND_SYNTAX_ERROR
;
1649 return dap_info_command(CMD
, &dap
->ap
[apsel
]);
1652 COMMAND_HANDLER(dap_baseaddr_command
)
1654 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1655 uint32_t apsel
, baseaddr
;
1663 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1664 /* AP address is in bits 31:24 of DP_SELECT */
1665 if (apsel
> DP_APSEL_MAX
)
1666 return ERROR_COMMAND_SYNTAX_ERROR
;
1669 return ERROR_COMMAND_SYNTAX_ERROR
;
1672 /* NOTE: assumes we're talking to a MEM-AP, which
1673 * has a base address. There are other kinds of AP,
1674 * though they're not common for now. This should
1675 * use the ID register to verify it's a MEM-AP.
1677 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), MEM_AP_REG_BASE
, &baseaddr
);
1678 if (retval
!= ERROR_OK
)
1680 retval
= dap_run(dap
);
1681 if (retval
!= ERROR_OK
)
1684 command_print(CMD
, "0x%8.8" PRIx32
, baseaddr
);
1689 COMMAND_HANDLER(dap_memaccess_command
)
1691 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1692 uint32_t memaccess_tck
;
1696 memaccess_tck
= dap
->ap
[dap
->apsel
].memaccess_tck
;
1699 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1702 return ERROR_COMMAND_SYNTAX_ERROR
;
1704 dap
->ap
[dap
->apsel
].memaccess_tck
= memaccess_tck
;
1706 command_print(CMD
, "memory bus access delay set to %" PRIi32
" tck",
1707 dap
->ap
[dap
->apsel
].memaccess_tck
);
1712 COMMAND_HANDLER(dap_apsel_command
)
1714 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1719 command_print(CMD
, "%" PRIi32
, dap
->apsel
);
1722 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1723 /* AP address is in bits 31:24 of DP_SELECT */
1724 if (apsel
> DP_APSEL_MAX
)
1725 return ERROR_COMMAND_SYNTAX_ERROR
;
1728 return ERROR_COMMAND_SYNTAX_ERROR
;
1735 COMMAND_HANDLER(dap_apcsw_command
)
1737 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1738 uint32_t apcsw
= dap
->ap
[dap
->apsel
].csw_default
;
1739 uint32_t csw_val
, csw_mask
;
1743 command_print(CMD
, "ap %" PRIi32
" selected, csw 0x%8.8" PRIx32
,
1747 if (strcmp(CMD_ARGV
[0], "default") == 0)
1748 csw_val
= CSW_AHB_DEFAULT
;
1750 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
1752 if (csw_val
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
1753 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1754 return ERROR_COMMAND_SYNTAX_ERROR
;
1759 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], csw_val
);
1760 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], csw_mask
);
1761 if (csw_mask
& (CSW_SIZE_MASK
| CSW_ADDRINC_MASK
)) {
1762 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
1763 return ERROR_COMMAND_SYNTAX_ERROR
;
1765 apcsw
= (apcsw
& ~csw_mask
) | (csw_val
& csw_mask
);
1768 return ERROR_COMMAND_SYNTAX_ERROR
;
1770 dap
->ap
[dap
->apsel
].csw_default
= apcsw
;
1777 COMMAND_HANDLER(dap_apid_command
)
1779 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1780 uint32_t apsel
, apid
;
1788 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1789 /* AP address is in bits 31:24 of DP_SELECT */
1790 if (apsel
> DP_APSEL_MAX
)
1791 return ERROR_COMMAND_SYNTAX_ERROR
;
1794 return ERROR_COMMAND_SYNTAX_ERROR
;
1797 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), AP_REG_IDR
, &apid
);
1798 if (retval
!= ERROR_OK
)
1800 retval
= dap_run(dap
);
1801 if (retval
!= ERROR_OK
)
1804 command_print(CMD
, "0x%8.8" PRIx32
, apid
);
1809 COMMAND_HANDLER(dap_apreg_command
)
1811 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1812 uint32_t apsel
, reg
, value
;
1813 struct adiv5_ap
*ap
;
1816 if (CMD_ARGC
< 2 || CMD_ARGC
> 3)
1817 return ERROR_COMMAND_SYNTAX_ERROR
;
1819 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1820 /* AP address is in bits 31:24 of DP_SELECT */
1821 if (apsel
> DP_APSEL_MAX
)
1822 return ERROR_COMMAND_SYNTAX_ERROR
;
1823 ap
= dap_ap(dap
, apsel
);
1825 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg
);
1826 if (reg
>= 256 || (reg
& 3))
1827 return ERROR_COMMAND_SYNTAX_ERROR
;
1829 if (CMD_ARGC
== 3) {
1830 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1832 case MEM_AP_REG_CSW
:
1833 ap
->csw_value
= 0; /* invalid, in case write fails */
1834 retval
= dap_queue_ap_write(ap
, reg
, value
);
1835 if (retval
== ERROR_OK
)
1836 ap
->csw_value
= value
;
1838 case MEM_AP_REG_TAR
:
1839 ap
->tar_valid
= false; /* invalid, force write */
1840 retval
= mem_ap_setup_tar(ap
, value
);
1843 retval
= dap_queue_ap_write(ap
, reg
, value
);
1847 retval
= dap_queue_ap_read(ap
, reg
, &value
);
1849 if (retval
== ERROR_OK
)
1850 retval
= dap_run(dap
);
1852 if (retval
!= ERROR_OK
)
1856 command_print(CMD
, "0x%08" PRIx32
, value
);
1861 COMMAND_HANDLER(dap_dpreg_command
)
1863 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1864 uint32_t reg
, value
;
1867 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
1868 return ERROR_COMMAND_SYNTAX_ERROR
;
1870 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg
);
1871 if (reg
>= 256 || (reg
& 3))
1872 return ERROR_COMMAND_SYNTAX_ERROR
;
1874 if (CMD_ARGC
== 2) {
1875 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1876 retval
= dap_queue_dp_write(dap
, reg
, value
);
1878 retval
= dap_queue_dp_read(dap
, reg
, &value
);
1880 if (retval
== ERROR_OK
)
1881 retval
= dap_run(dap
);
1883 if (retval
!= ERROR_OK
)
1887 command_print(CMD
, "0x%08" PRIx32
, value
);
1892 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
1894 struct adiv5_dap
*dap
= adiv5_get_dap(CMD_DATA
);
1895 uint32_t enable
= dap
->ti_be_32_quirks
;
1901 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], enable
);
1903 return ERROR_COMMAND_SYNTAX_ERROR
;
1906 return ERROR_COMMAND_SYNTAX_ERROR
;
1908 dap
->ti_be_32_quirks
= enable
;
1909 command_print(CMD
, "TI BE-32 quirks mode %s",
1910 enable
? "enabled" : "disabled");
1915 const struct command_registration dap_instance_commands
[] = {
1918 .handler
= handle_dap_info_command
,
1919 .mode
= COMMAND_EXEC
,
1920 .help
= "display ROM table for MEM-AP "
1921 "(default currently selected AP)",
1922 .usage
= "[ap_num]",
1926 .handler
= dap_apsel_command
,
1927 .mode
= COMMAND_ANY
,
1928 .help
= "Set the currently selected AP (default 0) "
1929 "and display the result",
1930 .usage
= "[ap_num]",
1934 .handler
= dap_apcsw_command
,
1935 .mode
= COMMAND_ANY
,
1936 .help
= "Set CSW default bits",
1937 .usage
= "[value [mask]]",
1942 .handler
= dap_apid_command
,
1943 .mode
= COMMAND_EXEC
,
1944 .help
= "return ID register from AP "
1945 "(default currently selected AP)",
1946 .usage
= "[ap_num]",
1950 .handler
= dap_apreg_command
,
1951 .mode
= COMMAND_EXEC
,
1952 .help
= "read/write a register from AP "
1953 "(reg is byte address of a word register, like 0 4 8...)",
1954 .usage
= "ap_num reg [value]",
1958 .handler
= dap_dpreg_command
,
1959 .mode
= COMMAND_EXEC
,
1960 .help
= "read/write a register from DP "
1961 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
1962 .usage
= "reg [value]",
1966 .handler
= dap_baseaddr_command
,
1967 .mode
= COMMAND_EXEC
,
1968 .help
= "return debug base address from MEM-AP "
1969 "(default currently selected AP)",
1970 .usage
= "[ap_num]",
1973 .name
= "memaccess",
1974 .handler
= dap_memaccess_command
,
1975 .mode
= COMMAND_EXEC
,
1976 .help
= "set/get number of extra tck for MEM-AP memory "
1977 "bus access [0-255]",
1978 .usage
= "[cycles]",
1981 .name
= "ti_be_32_quirks",
1982 .handler
= dap_ti_be_32_quirks_command
,
1983 .mode
= COMMAND_CONFIG
,
1984 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
1985 .usage
= "[enable]",
1987 COMMAND_REGISTRATION_DONE
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