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- added support for setting JTAG frequency on ASIX PRESTO (thanks to Pavel Chromy)
[openocd.git] / src / target / arm9tdmi.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm9tdmi.h"
25
26 #include "arm7_9_common.h"
27 #include "register.h"
28 #include "target.h"
29 #include "armv4_5.h"
30 #include "embeddedice.h"
31 #include "etm.h"
32 #include "etb.h"
33 #include "log.h"
34 #include "jtag.h"
35 #include "arm_jtag.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39
40 #if 0
41 #define _DEBUG_INSTRUCTION_EXECUTION_
42 #endif
43
44 /* cli handling */
45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm9tdmi_quit();
52
53 target_type_t arm9tdmi_target =
54 {
55 .name = "arm9tdmi",
56
57 .poll = arm7_9_poll,
58 .arch_state = armv4_5_arch_state,
59
60 .target_request_data = arm7_9_target_request_data,
61
62 .halt = arm7_9_halt,
63 .resume = arm7_9_resume,
64 .step = arm7_9_step,
65
66 .assert_reset = arm7_9_assert_reset,
67 .deassert_reset = arm7_9_deassert_reset,
68 .soft_reset_halt = arm7_9_soft_reset_halt,
69 .prepare_reset_halt = arm7_9_prepare_reset_halt,
70
71 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
72
73 .read_memory = arm7_9_read_memory,
74 .write_memory = arm7_9_write_memory,
75 .bulk_write_memory = arm7_9_bulk_write_memory,
76
77 .run_algorithm = armv4_5_run_algorithm,
78
79 .add_breakpoint = arm7_9_add_breakpoint,
80 .remove_breakpoint = arm7_9_remove_breakpoint,
81 .add_watchpoint = arm7_9_add_watchpoint,
82 .remove_watchpoint = arm7_9_remove_watchpoint,
83
84 .register_commands = arm9tdmi_register_commands,
85 .target_command = arm9tdmi_target_command,
86 .init_target = arm9tdmi_init_target,
87 .quit = arm9tdmi_quit
88 };
89
90 arm9tdmi_vector_t arm9tdmi_vectors[] =
91 {
92 {"reset", ARM9TDMI_RESET_VECTOR},
93 {"undef", ARM9TDMI_UNDEF_VECTOR},
94 {"swi", ARM9TDMI_SWI_VECTOR},
95 {"pabt", ARM9TDMI_PABT_VECTOR},
96 {"dabt", ARM9TDMI_DABT_VECTOR},
97 {"reserved", ARM9TDMI_RESERVED_VECTOR},
98 {"irq", ARM9TDMI_IRQ_VECTOR},
99 {"fiq", ARM9TDMI_FIQ_VECTOR},
100 {0, 0},
101 };
102
103 int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv)
104 {
105 char *caller = priv;
106
107 DEBUG("caller: %s", caller);
108
109 return ERROR_JTAG_QUEUE_FAILED;
110 }
111
112 int arm9tdmi_examine_debug_reason(target_t *target)
113 {
114 /* get pointers to arch-specific information */
115 armv4_5_common_t *armv4_5 = target->arch_info;
116 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
117
118 /* only check the debug reason if we don't know it already */
119 if ((target->debug_reason != DBG_REASON_DBGRQ)
120 && (target->debug_reason != DBG_REASON_SINGLESTEP))
121 {
122 scan_field_t fields[3];
123 u8 databus[4];
124 u8 instructionbus[4];
125 u8 debug_reason;
126
127 jtag_add_end_state(TAP_PD);
128
129 fields[0].device = arm7_9->jtag_info.chain_pos;
130 fields[0].num_bits = 32;
131 fields[0].out_value = NULL;
132 fields[0].out_mask = NULL;
133 fields[0].in_value = databus;
134 fields[0].in_check_value = NULL;
135 fields[0].in_check_mask = NULL;
136 fields[0].in_handler = NULL;
137 fields[0].in_handler_priv = NULL;
138
139 fields[1].device = arm7_9->jtag_info.chain_pos;
140 fields[1].num_bits = 3;
141 fields[1].out_value = NULL;
142 fields[1].out_mask = NULL;
143 fields[1].in_value = &debug_reason;
144 fields[1].in_check_value = NULL;
145 fields[1].in_check_mask = NULL;
146 fields[1].in_handler = NULL;
147 fields[1].in_handler_priv = NULL;
148
149 fields[2].device = arm7_9->jtag_info.chain_pos;
150 fields[2].num_bits = 32;
151 fields[2].out_value = NULL;
152 fields[2].out_mask = NULL;
153 fields[2].in_value = instructionbus;
154 fields[2].in_check_value = NULL;
155 fields[2].in_check_mask = NULL;
156 fields[2].in_handler = NULL;
157 fields[2].in_handler_priv = NULL;
158
159 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
160 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
161
162 jtag_add_dr_scan(3, fields, TAP_PD, NULL);
163 jtag_execute_queue();
164
165 fields[0].in_value = NULL;
166 fields[0].out_value = databus;
167 fields[1].in_value = NULL;
168 fields[1].out_value = &debug_reason;
169 fields[2].in_value = NULL;
170 fields[2].out_value = instructionbus;
171
172 jtag_add_dr_scan(3, fields, TAP_PD, NULL);
173
174 if (debug_reason & 0x4)
175 if (debug_reason & 0x2)
176 target->debug_reason = DBG_REASON_WPTANDBKPT;
177 else
178 target->debug_reason = DBG_REASON_WATCHPOINT;
179 else
180 target->debug_reason = DBG_REASON_BREAKPOINT;
181 }
182
183 return ERROR_OK;
184 }
185
186 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
187 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
188 {
189 scan_field_t fields[3];
190 u8 out_buf[4];
191 u8 instr_buf[4];
192 u8 sysspeed_buf = 0x0;
193
194 /* prepare buffer */
195 buf_set_u32(out_buf, 0, 32, out);
196
197 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
198
199 if (sysspeed)
200 buf_set_u32(&sysspeed_buf, 2, 1, 1);
201
202 jtag_add_end_state(TAP_PD);
203 arm_jtag_scann(jtag_info, 0x1);
204
205 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
206
207 fields[0].device = jtag_info->chain_pos;
208 fields[0].num_bits = 32;
209 fields[0].out_value = out_buf;
210 fields[0].out_mask = NULL;
211 fields[0].in_value = NULL;
212 if (in)
213 {
214 fields[0].in_handler = arm_jtag_buf_to_u32;
215 fields[0].in_handler_priv = in;
216 }
217 else
218 {
219 fields[0].in_handler = NULL;
220 fields[0].in_handler_priv = NULL;
221 }
222 fields[0].in_check_value = NULL;
223 fields[0].in_check_mask = NULL;
224
225 fields[1].device = jtag_info->chain_pos;
226 fields[1].num_bits = 3;
227 fields[1].out_value = &sysspeed_buf;
228 fields[1].out_mask = NULL;
229 fields[1].in_value = NULL;
230 fields[1].in_check_value = NULL;
231 fields[1].in_check_mask = NULL;
232 fields[1].in_handler = NULL;
233 fields[1].in_handler_priv = NULL;
234
235 fields[2].device = jtag_info->chain_pos;
236 fields[2].num_bits = 32;
237 fields[2].out_value = instr_buf;
238 fields[2].out_mask = NULL;
239 fields[2].in_value = NULL;
240 fields[2].in_check_value = NULL;
241 fields[2].in_check_mask = NULL;
242 fields[2].in_handler = NULL;
243 fields[2].in_handler_priv = NULL;
244
245 jtag_add_dr_scan(3, fields, -1, NULL);
246
247 jtag_add_runtest(0, -1);
248
249 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
250 {
251 jtag_execute_queue();
252
253 if (in)
254 {
255 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
256 }
257 else
258 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
259 }
260 #endif
261
262 return ERROR_OK;
263 }
264
265 /* just read data (instruction and data-out = don't care) */
266 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
267 {
268 scan_field_t fields[3];
269
270 jtag_add_end_state(TAP_PD);
271 arm_jtag_scann(jtag_info, 0x1);
272
273 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
274
275 fields[0].device = jtag_info->chain_pos;
276 fields[0].num_bits = 32;
277 fields[0].out_value = NULL;
278 fields[0].out_mask = NULL;
279 fields[0].in_value = NULL;
280 fields[0].in_handler = arm_jtag_buf_to_u32;
281 fields[0].in_handler_priv = in;
282 fields[0].in_check_value = NULL;
283 fields[0].in_check_mask = NULL;
284
285 fields[1].device = jtag_info->chain_pos;
286 fields[1].num_bits = 3;
287 fields[1].out_value = NULL;
288 fields[1].out_mask = NULL;
289 fields[1].in_value = NULL;
290 fields[1].in_handler = NULL;
291 fields[1].in_handler_priv = NULL;
292 fields[1].in_check_value = NULL;
293 fields[1].in_check_mask = NULL;
294
295 fields[2].device = jtag_info->chain_pos;
296 fields[2].num_bits = 32;
297 fields[2].out_value = NULL;
298 fields[2].out_mask = NULL;
299 fields[2].in_value = NULL;
300 fields[2].in_check_value = NULL;
301 fields[2].in_check_mask = NULL;
302 fields[2].in_handler = NULL;
303 fields[2].in_handler_priv = NULL;
304
305 jtag_add_dr_scan(3, fields, -1, NULL);
306
307 jtag_add_runtest(0, -1);
308
309 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
310 {
311 jtag_execute_queue();
312
313 if (in)
314 {
315 DEBUG("in: 0x%8.8x", *in);
316 }
317 else
318 {
319 ERROR("BUG: called with in == NULL");
320 }
321 }
322 #endif
323
324 return ERROR_OK;
325 }
326
327 /* clock the target, and read the databus
328 * the *in pointer points to a buffer where elements of 'size' bytes
329 * are stored in big (be==1) or little (be==0) endianness
330 */
331 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
332 {
333 scan_field_t fields[3];
334
335 jtag_add_end_state(TAP_PD);
336 arm_jtag_scann(jtag_info, 0x1);
337
338 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
339
340 fields[0].device = jtag_info->chain_pos;
341 fields[0].num_bits = 32;
342 fields[0].out_value = NULL;
343 fields[0].out_mask = NULL;
344 fields[0].in_value = NULL;
345 switch (size)
346 {
347 case 4:
348 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
349 break;
350 case 2:
351 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
352 break;
353 case 1:
354 fields[0].in_handler = arm_jtag_buf_to_8;
355 break;
356 }
357 fields[0].in_handler_priv = in;
358 fields[0].in_check_value = NULL;
359 fields[0].in_check_mask = NULL;
360
361 fields[1].device = jtag_info->chain_pos;
362 fields[1].num_bits = 3;
363 fields[1].out_value = NULL;
364 fields[1].out_mask = NULL;
365 fields[1].in_value = NULL;
366 fields[1].in_handler = NULL;
367 fields[1].in_handler_priv = NULL;
368 fields[1].in_check_value = NULL;
369 fields[1].in_check_mask = NULL;
370
371 fields[2].device = jtag_info->chain_pos;
372 fields[2].num_bits = 32;
373 fields[2].out_value = NULL;
374 fields[2].out_mask = NULL;
375 fields[2].in_value = NULL;
376 fields[2].in_check_value = NULL;
377 fields[2].in_check_mask = NULL;
378 fields[2].in_handler = NULL;
379 fields[2].in_handler_priv = NULL;
380
381 jtag_add_dr_scan(3, fields, -1, NULL);
382
383 jtag_add_runtest(0, -1);
384
385 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
386 {
387 jtag_execute_queue();
388
389 if (in)
390 {
391 DEBUG("in: 0x%8.8x", *in);
392 }
393 else
394 {
395 ERROR("BUG: called with in == NULL");
396 }
397 }
398 #endif
399
400 return ERROR_OK;
401 }
402
403 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
404 {
405 /* get pointers to arch-specific information */
406 armv4_5_common_t *armv4_5 = target->arch_info;
407 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
408 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
409
410 /* save r0 before using it and put system in ARM state
411 * to allow common handling of ARM and THUMB debugging */
412
413 /* fetch STR r0, [r0] */
414 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
415 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
416 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
417 /* STR r0, [r0] in Memory */
418 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
419
420 /* MOV r0, r15 fetched, STR in Decode */
421 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
422 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
423 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
424 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
425 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
426 /* nothing fetched, STR r0, [r0] in Memory */
427 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
428
429 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
430 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
431 /* LDR in Decode */
432 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
433 /* LDR in Execute */
434 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
435 /* LDR in Memory (to account for interlock) */
436 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
437
438 /* fetch BX */
439 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
440 /* NOP fetched, BX in Decode, MOV in Execute */
441 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
442 /* NOP fetched, BX in Execute (1) */
443 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
444
445 jtag_execute_queue();
446
447 /* fix program counter:
448 * MOV r0, r15 was the 5th instruction (+8)
449 * reading PC in Thumb state gives address of instruction + 4
450 */
451 *pc -= 0xc;
452 }
453
454 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
455 {
456 int i;
457 /* get pointers to arch-specific information */
458 armv4_5_common_t *armv4_5 = target->arch_info;
459 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
460 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
461
462 /* STMIA r0-15, [r0] at debug speed
463 * register values will start to appear on 4th DCLK
464 */
465 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
466
467 /* fetch NOP, STM in DECODE stage */
468 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
469 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
470 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
471
472 for (i = 0; i <= 15; i++)
473 {
474 if (mask & (1 << i))
475 /* nothing fetched, STM in MEMORY (i'th cycle) */
476 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
477 }
478
479 }
480
481 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
482 {
483 int i;
484 /* get pointers to arch-specific information */
485 armv4_5_common_t *armv4_5 = target->arch_info;
486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
488 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
489 u32 *buf_u32 = buffer;
490 u16 *buf_u16 = buffer;
491 u8 *buf_u8 = buffer;
492
493 /* STMIA r0-15, [r0] at debug speed
494 * register values will start to appear on 4th DCLK
495 */
496 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
497
498 /* fetch NOP, STM in DECODE stage */
499 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
500 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
501 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
502
503 for (i = 0; i <= 15; i++)
504 {
505 if (mask & (1 << i))
506 /* nothing fetched, STM in MEMORY (i'th cycle) */
507 switch (size)
508 {
509 case 4:
510 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
511 break;
512 case 2:
513 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
514 break;
515 case 1:
516 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
517 break;
518 }
519 }
520
521 }
522
523 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
524 {
525 /* get pointers to arch-specific information */
526 armv4_5_common_t *armv4_5 = target->arch_info;
527 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
528 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
529
530 /* MRS r0, cpsr */
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
534 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
535 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
536
537 /* STR r0, [r15] */
538 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
539 /* fetch NOP, STR in DECODE stage */
540 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
541 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
542 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
543 /* nothing fetched, STR in MEMORY */
544 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
545
546 }
547
548 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
549 {
550 /* get pointers to arch-specific information */
551 armv4_5_common_t *armv4_5 = target->arch_info;
552 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
553 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
554
555 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
556
557 /* MSR1 fetched */
558 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
559 /* MSR2 fetched, MSR1 in DECODE */
560 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
561 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
562 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
563 /* nothing fetched, MSR1 in EXECUTE (2) */
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
565 /* nothing fetched, MSR1 in EXECUTE (3) */
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
567 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
568 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
569 /* nothing fetched, MSR2 in EXECUTE (2) */
570 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
571 /* nothing fetched, MSR2 in EXECUTE (3) */
572 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
573 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
574 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
575 /* nothing fetched, MSR3 in EXECUTE (2) */
576 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
577 /* nothing fetched, MSR3 in EXECUTE (3) */
578 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
579 /* NOP fetched, MSR4 in EXECUTE (1) */
580 /* last MSR writes flags, which takes only one cycle */
581 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
582 }
583
584 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
585 {
586 /* get pointers to arch-specific information */
587 armv4_5_common_t *armv4_5 = target->arch_info;
588 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
589 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
590
591 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
592
593 /* MSR fetched */
594 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
595 /* NOP fetched, MSR in DECODE */
596 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
597 /* NOP fetched, MSR in EXECUTE (1) */
598 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
599
600 /* rot == 4 writes flags, which takes only one cycle */
601 if (rot != 4)
602 {
603 /* nothing fetched, MSR in EXECUTE (2) */
604 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
605 /* nothing fetched, MSR in EXECUTE (3) */
606 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
607 }
608 }
609
610 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
611 {
612 int i;
613 /* get pointers to arch-specific information */
614 armv4_5_common_t *armv4_5 = target->arch_info;
615 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
616 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
617
618 /* LDMIA r0-15, [r0] at debug speed
619 * register values will start to appear on 4th DCLK
620 */
621 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
622
623 /* fetch NOP, LDM in DECODE stage */
624 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
625 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
626 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
627
628 for (i = 0; i <= 15; i++)
629 {
630 if (mask & (1 << i))
631 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
632 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
633 }
634 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
635
636 }
637
638 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
639 {
640 /* get pointers to arch-specific information */
641 armv4_5_common_t *armv4_5 = target->arch_info;
642 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
643 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
644
645 /* put system-speed load-multiple into the pipeline */
646 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
647 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
648
649 }
650
651 void arm9tdmi_load_hword_reg(target_t *target, int num)
652 {
653 /* get pointers to arch-specific information */
654 armv4_5_common_t *armv4_5 = target->arch_info;
655 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
656 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
657
658 /* put system-speed load half-word into the pipeline */
659 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
660 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
661 }
662
663 void arm9tdmi_load_byte_reg(target_t *target, int num)
664 {
665 /* get pointers to arch-specific information */
666 armv4_5_common_t *armv4_5 = target->arch_info;
667 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
668 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
669
670 /* put system-speed load byte into the pipeline */
671 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
672 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
673
674 }
675
676 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
677 {
678 /* get pointers to arch-specific information */
679 armv4_5_common_t *armv4_5 = target->arch_info;
680 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
681 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
682
683 /* put system-speed store-multiple into the pipeline */
684 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
685 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
686
687 }
688
689 void arm9tdmi_store_hword_reg(target_t *target, int num)
690 {
691 /* get pointers to arch-specific information */
692 armv4_5_common_t *armv4_5 = target->arch_info;
693 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
694 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
695
696 /* put system-speed store half-word into the pipeline */
697 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
698 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
699
700 }
701
702 void arm9tdmi_store_byte_reg(target_t *target, int num)
703 {
704 /* get pointers to arch-specific information */
705 armv4_5_common_t *armv4_5 = target->arch_info;
706 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
707 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
708
709 /* put system-speed store byte into the pipeline */
710 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
711 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
712
713 }
714
715 void arm9tdmi_write_pc(target_t *target, u32 pc)
716 {
717 /* get pointers to arch-specific information */
718 armv4_5_common_t *armv4_5 = target->arch_info;
719 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
720 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
721
722 /* LDMIA r0-15, [r0] at debug speed
723 * register values will start to appear on 4th DCLK
724 */
725 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
726
727 /* fetch NOP, LDM in DECODE stage */
728 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
729 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
731 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
732 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
733 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
734 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
735 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
736 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
737 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
738 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
739
740 }
741
742 void arm9tdmi_branch_resume(target_t *target)
743 {
744 /* get pointers to arch-specific information */
745 armv4_5_common_t *armv4_5 = target->arch_info;
746 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
747 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
748
749 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
750 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
751
752 }
753
754 void arm9tdmi_branch_resume_thumb(target_t *target)
755 {
756 DEBUG("-");
757
758 /* get pointers to arch-specific information */
759 armv4_5_common_t *armv4_5 = target->arch_info;
760 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
761 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
762 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
763
764 /* LDMIA r0-15, [r0] at debug speed
765 * register values will start to appear on 4th DCLK
766 */
767 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
768
769 /* fetch NOP, LDM in DECODE stage */
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
771 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
772 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
773 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
774 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
775 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
776 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
777
778 /* Branch and eXchange */
779 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
780
781 embeddedice_read_reg(dbg_stat);
782
783 /* fetch NOP, BX in DECODE stage */
784 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
785
786 embeddedice_read_reg(dbg_stat);
787
788 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
789 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
790
791 /* target is now in Thumb state */
792 embeddedice_read_reg(dbg_stat);
793
794 /* load r0 value, MOV_IM in Decode*/
795 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
796 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
797 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
798 /* fetch NOP, LDR in Execute */
799 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
800 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
801 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
802 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
803 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
804
805 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
806 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
807
808 embeddedice_read_reg(dbg_stat);
809
810 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
811 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
812
813 }
814
815 void arm9tdmi_enable_single_step(target_t *target)
816 {
817 /* get pointers to arch-specific information */
818 armv4_5_common_t *armv4_5 = target->arch_info;
819 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
820
821 if (arm7_9->has_single_step)
822 {
823 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
824 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
825 }
826 else
827 {
828 arm7_9_enable_eice_step(target);
829 }
830 }
831
832 void arm9tdmi_disable_single_step(target_t *target)
833 {
834 /* get pointers to arch-specific information */
835 armv4_5_common_t *armv4_5 = target->arch_info;
836 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
837
838 if (arm7_9->has_single_step)
839 {
840 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
841 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
842 }
843 else
844 {
845 arm7_9_disable_eice_step(target);
846 }
847 }
848
849 void arm9tdmi_build_reg_cache(target_t *target)
850 {
851 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
852 /* get pointers to arch-specific information */
853 armv4_5_common_t *armv4_5 = target->arch_info;
854 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
855 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
856
857 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
858 armv4_5->core_cache = (*cache_p);
859
860 /* one extra register (vector catch) */
861 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
862 arm7_9->eice_cache = (*cache_p)->next;
863
864 if (arm7_9->etm_ctx)
865 {
866 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
867 arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
868 }
869 }
870
871 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
872 {
873
874 arm9tdmi_build_reg_cache(target);
875
876 return ERROR_OK;
877
878 }
879
880 int arm9tdmi_quit()
881 {
882
883 return ERROR_OK;
884 }
885
886 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
887 {
888 armv4_5_common_t *armv4_5;
889 arm7_9_common_t *arm7_9;
890
891 arm7_9 = &arm9tdmi->arm7_9_common;
892 armv4_5 = &arm7_9->armv4_5_common;
893
894 /* prepare JTAG information for the new target */
895 arm7_9->jtag_info.chain_pos = chain_pos;
896 arm7_9->jtag_info.scann_size = 5;
897
898 /* register arch-specific functions */
899 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
900 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
901 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
902 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
903 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
904
905 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
906 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
907 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
908
909 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
910 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
911 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
912
913 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
914 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
915 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
916
917 arm7_9->write_pc = arm9tdmi_write_pc;
918 arm7_9->branch_resume = arm9tdmi_branch_resume;
919 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
920
921 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
922 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
923
924 arm7_9->pre_debug_entry = NULL;
925 arm7_9->post_debug_entry = NULL;
926
927 arm7_9->pre_restore_context = NULL;
928 arm7_9->post_restore_context = NULL;
929
930 /* initialize arch-specific breakpoint handling */
931 arm7_9->arm_bkpt = 0xdeeedeee;
932 arm7_9->thumb_bkpt = 0xdeee;
933
934 arm7_9->sw_bkpts_use_wp = 1;
935 arm7_9->sw_bkpts_enabled = 0;
936 arm7_9->dbgreq_adjust_pc = 3;
937 arm7_9->arch_info = arm9tdmi;
938
939 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
940 arm9tdmi->arch_info = NULL;
941
942 if (variant)
943 {
944 arm9tdmi->variant = strdup(variant);
945 }
946 else
947 {
948 arm9tdmi->variant = strdup("");
949 }
950
951 arm7_9_init_arch_info(target, arm7_9);
952
953 /* override use of DBGRQ, this is safe on ARM9TDMI */
954 arm7_9->use_dbgrq = 1;
955
956 /* all ARM9s have the vector catch register */
957 arm7_9->has_vector_catch = 1;
958
959 return ERROR_OK;
960 }
961
962 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
963 {
964 armv4_5_common_t *armv4_5 = target->arch_info;
965 arm7_9_common_t *arm7_9;
966 arm9tdmi_common_t *arm9tdmi;
967
968 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
969 {
970 return -1;
971 }
972
973 arm7_9 = armv4_5->arch_info;
974 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
975 {
976 return -1;
977 }
978
979 arm9tdmi = arm7_9->arch_info;
980 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
981 {
982 return -1;
983 }
984
985 *armv4_5_p = armv4_5;
986 *arm7_9_p = arm7_9;
987 *arm9tdmi_p = arm9tdmi;
988
989 return ERROR_OK;
990 }
991
992
993 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
994 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
995 {
996 int chain_pos;
997 char *variant = NULL;
998 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
999
1000 if (argc < 4)
1001 {
1002 ERROR("'target arm9tdmi' requires at least one additional argument");
1003 exit(-1);
1004 }
1005
1006 chain_pos = strtoul(args[3], NULL, 0);
1007
1008 if (argc >= 5)
1009 variant = args[4];
1010
1011 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
1012
1013 return ERROR_OK;
1014 }
1015
1016 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1017 {
1018 int retval;
1019
1020 command_t *arm9tdmi_cmd;
1021
1022
1023 retval = arm7_9_register_commands(cmd_ctx);
1024
1025 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1026
1027 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1028
1029
1030 return ERROR_OK;
1031
1032 }
1033
1034 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1035 {
1036 target_t *target = get_current_target(cmd_ctx);
1037 armv4_5_common_t *armv4_5;
1038 arm7_9_common_t *arm7_9;
1039 arm9tdmi_common_t *arm9tdmi;
1040 reg_t *vector_catch;
1041 u32 vector_catch_value;
1042 int i, j;
1043
1044 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1045 {
1046 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1047 return ERROR_OK;
1048 }
1049
1050 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1051
1052 /* read the vector catch register if necessary */
1053 if (!vector_catch->valid)
1054 embeddedice_read_reg(vector_catch);
1055
1056 /* get the current setting */
1057 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1058
1059 if (argc > 0)
1060 {
1061 vector_catch_value = 0x0;
1062 if (strcmp(args[0], "all") == 0)
1063 {
1064 vector_catch_value = 0xdf;
1065 }
1066 else if (strcmp(args[0], "none") == 0)
1067 {
1068 /* do nothing */
1069 }
1070 else
1071 {
1072 for (i = 0; i < argc; i++)
1073 {
1074 /* go through list of vectors */
1075 for(j = 0; arm9tdmi_vectors[j].name; j++)
1076 {
1077 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1078 {
1079 vector_catch_value |= arm9tdmi_vectors[j].value;
1080 break;
1081 }
1082 }
1083
1084 /* complain if vector wasn't found */
1085 if (!arm9tdmi_vectors[j].name)
1086 {
1087 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1088
1089 /* reread current setting */
1090 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1091
1092 break;
1093 }
1094 }
1095 }
1096
1097 /* store new settings */
1098 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1099 embeddedice_store_reg(vector_catch);
1100 }
1101
1102 /* output current settings (skip RESERVED vector) */
1103 for (i = 0; i < 8; i++)
1104 {
1105 if (i != 5)
1106 {
1107 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1108 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1109 }
1110 }
1111
1112 return ERROR_OK;
1113 }
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