bitbang: Add flush before sleep
[openocd.git] / src / jtag / drivers / bitbang.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
6 * *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
9 ***************************************************************************/
10
11 /* 2014-12: Addition of the SWD protocol support is based on the initial work
12 * by Paul Fertser and modifications by Jean-Christian de Rivaz. */
13
14 #ifdef HAVE_CONFIG_H
15 #include "config.h"
16 #endif
17
18 #include "bitbang.h"
19 #include <jtag/interface.h>
20 #include <jtag/commands.h>
21
22 /**
23 * Function bitbang_stableclocks
24 * issues a number of clock cycles while staying in a stable state.
25 * Because the TMS value required to stay in the RESET state is a 1, whereas
26 * the TMS value required to stay in any of the other stable states is a 0,
27 * this function checks the current stable state to decide on the value of TMS
28 * to use.
29 */
30 static int bitbang_stableclocks(int num_cycles);
31
32 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk);
33
34 struct bitbang_interface *bitbang_interface;
35
36 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
37 *
38 * Set this to 1 and str912 reset halt will fail.
39 *
40 * If someone can submit a patch with an explanation it will be greatly
41 * appreciated, but as far as I can tell (ØH) DCLK is generated upon
42 * clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
43 * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
44 * state". With hardware there is no such thing as *while* in a state. There
45 * are only edges. So clk => 0 is in fact a very subtle state transition that
46 * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
47 *
48 * For "reset halt" the last thing that happens before srst is asserted
49 * is that the breakpoint is set up. If DCLK is not wiggled one last
50 * time before the reset, then the breakpoint is not set up and
51 * "reset halt" will fail to halt.
52 *
53 */
54 #define CLOCK_IDLE() 0
55
56 /* The bitbang driver leaves the TCK 0 when in idle */
57 static void bitbang_end_state(tap_state_t state)
58 {
59 assert(tap_is_state_stable(state));
60 tap_set_end_state(state);
61 }
62
63 static int bitbang_state_move(int skip)
64 {
65 int i = 0, tms = 0;
66 uint8_t tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state());
67 int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
68
69 for (i = skip; i < tms_count; i++) {
70 tms = (tms_scan >> i) & 1;
71 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
72 return ERROR_FAIL;
73 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
74 return ERROR_FAIL;
75 }
76 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
77 return ERROR_FAIL;
78
79 tap_set_state(tap_get_end_state());
80 return ERROR_OK;
81 }
82
83 /**
84 * Clock a bunch of TMS (or SWDIO) transitions, to change the JTAG
85 * (or SWD) state machine.
86 */
87 static int bitbang_execute_tms(struct jtag_command *cmd)
88 {
89 unsigned num_bits = cmd->cmd.tms->num_bits;
90 const uint8_t *bits = cmd->cmd.tms->bits;
91
92 LOG_DEBUG_IO("TMS: %d bits", num_bits);
93
94 int tms = 0;
95 for (unsigned i = 0; i < num_bits; i++) {
96 tms = ((bits[i/8] >> (i % 8)) & 1);
97 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
98 return ERROR_FAIL;
99 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
100 return ERROR_FAIL;
101 }
102 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
103 return ERROR_FAIL;
104
105 return ERROR_OK;
106 }
107
108 static int bitbang_path_move(struct pathmove_command *cmd)
109 {
110 int num_states = cmd->num_states;
111 int state_count;
112 int tms = 0;
113
114 state_count = 0;
115 while (num_states) {
116 if (tap_state_transition(tap_get_state(), false) == cmd->path[state_count])
117 tms = 0;
118 else if (tap_state_transition(tap_get_state(), true) == cmd->path[state_count])
119 tms = 1;
120 else {
121 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
122 tap_state_name(tap_get_state()),
123 tap_state_name(cmd->path[state_count]));
124 exit(-1);
125 }
126
127 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
128 return ERROR_FAIL;
129 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
130 return ERROR_FAIL;
131
132 tap_set_state(cmd->path[state_count]);
133 state_count++;
134 num_states--;
135 }
136
137 if (bitbang_interface->write(CLOCK_IDLE(), tms, 0) != ERROR_OK)
138 return ERROR_FAIL;
139
140 tap_set_end_state(tap_get_state());
141 return ERROR_OK;
142 }
143
144 static int bitbang_runtest(int num_cycles)
145 {
146 int i;
147
148 tap_state_t saved_end_state = tap_get_end_state();
149
150 /* only do a state_move when we're not already in IDLE */
151 if (tap_get_state() != TAP_IDLE) {
152 bitbang_end_state(TAP_IDLE);
153 if (bitbang_state_move(0) != ERROR_OK)
154 return ERROR_FAIL;
155 }
156
157 /* execute num_cycles */
158 for (i = 0; i < num_cycles; i++) {
159 if (bitbang_interface->write(0, 0, 0) != ERROR_OK)
160 return ERROR_FAIL;
161 if (bitbang_interface->write(1, 0, 0) != ERROR_OK)
162 return ERROR_FAIL;
163 }
164 if (bitbang_interface->write(CLOCK_IDLE(), 0, 0) != ERROR_OK)
165 return ERROR_FAIL;
166
167 /* finish in end_state */
168 bitbang_end_state(saved_end_state);
169 if (tap_get_state() != tap_get_end_state())
170 if (bitbang_state_move(0) != ERROR_OK)
171 return ERROR_FAIL;
172
173 return ERROR_OK;
174 }
175
176 static int bitbang_stableclocks(int num_cycles)
177 {
178 int tms = (tap_get_state() == TAP_RESET ? 1 : 0);
179 int i;
180
181 /* send num_cycles clocks onto the cable */
182 for (i = 0; i < num_cycles; i++) {
183 if (bitbang_interface->write(1, tms, 0) != ERROR_OK)
184 return ERROR_FAIL;
185 if (bitbang_interface->write(0, tms, 0) != ERROR_OK)
186 return ERROR_FAIL;
187 }
188
189 return ERROR_OK;
190 }
191
192 static int bitbang_scan(bool ir_scan, enum scan_type type, uint8_t *buffer,
193 unsigned scan_size)
194 {
195 tap_state_t saved_end_state = tap_get_end_state();
196 unsigned bit_cnt;
197
198 if (!((!ir_scan &&
199 (tap_get_state() == TAP_DRSHIFT)) ||
200 (ir_scan && (tap_get_state() == TAP_IRSHIFT)))) {
201 if (ir_scan)
202 bitbang_end_state(TAP_IRSHIFT);
203 else
204 bitbang_end_state(TAP_DRSHIFT);
205
206 if (bitbang_state_move(0) != ERROR_OK)
207 return ERROR_FAIL;
208 bitbang_end_state(saved_end_state);
209 }
210
211 size_t buffered = 0;
212 for (bit_cnt = 0; bit_cnt < scan_size; bit_cnt++) {
213 int tms = (bit_cnt == scan_size-1) ? 1 : 0;
214 int tdi;
215 int bytec = bit_cnt/8;
216 int bcval = 1 << (bit_cnt % 8);
217
218 /* if we're just reading the scan, but don't care about the output
219 * default to outputting 'low', this also makes valgrind traces more readable,
220 * as it removes the dependency on an uninitialised value
221 */
222 tdi = 0;
223 if ((type != SCAN_IN) && (buffer[bytec] & bcval))
224 tdi = 1;
225
226 if (bitbang_interface->write(0, tms, tdi) != ERROR_OK)
227 return ERROR_FAIL;
228
229 if (type != SCAN_OUT) {
230 if (bitbang_interface->buf_size) {
231 if (bitbang_interface->sample() != ERROR_OK)
232 return ERROR_FAIL;
233 buffered++;
234 } else {
235 switch (bitbang_interface->read()) {
236 case BB_LOW:
237 buffer[bytec] &= ~bcval;
238 break;
239 case BB_HIGH:
240 buffer[bytec] |= bcval;
241 break;
242 default:
243 return ERROR_FAIL;
244 }
245 }
246 }
247
248 if (bitbang_interface->write(1, tms, tdi) != ERROR_OK)
249 return ERROR_FAIL;
250
251 if (type != SCAN_OUT && bitbang_interface->buf_size &&
252 (buffered == bitbang_interface->buf_size ||
253 bit_cnt == scan_size - 1)) {
254 for (unsigned i = bit_cnt + 1 - buffered; i <= bit_cnt; i++) {
255 switch (bitbang_interface->read_sample()) {
256 case BB_LOW:
257 buffer[i/8] &= ~(1 << (i % 8));
258 break;
259 case BB_HIGH:
260 buffer[i/8] |= 1 << (i % 8);
261 break;
262 default:
263 return ERROR_FAIL;
264 }
265 }
266 buffered = 0;
267 }
268 }
269
270 if (tap_get_state() != tap_get_end_state()) {
271 /* we *KNOW* the above loop transitioned out of
272 * the shift state, so we skip the first state
273 * and move directly to the end state.
274 */
275 if (bitbang_state_move(1) != ERROR_OK)
276 return ERROR_FAIL;
277 }
278 return ERROR_OK;
279 }
280
281 static void bitbang_sleep(unsigned int microseconds)
282 {
283 if (bitbang_interface->sleep) {
284 bitbang_interface->sleep(microseconds);
285 } else {
286 jtag_sleep(microseconds);
287 }
288 }
289
290 int bitbang_execute_queue(void)
291 {
292 struct jtag_command *cmd = jtag_command_queue; /* currently processed command */
293 int scan_size;
294 enum scan_type type;
295 uint8_t *buffer;
296 int retval;
297
298 if (!bitbang_interface) {
299 LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
300 exit(-1);
301 }
302
303 /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
304 * that wasn't handled by a caller-provided error handler
305 */
306 retval = ERROR_OK;
307
308 if (bitbang_interface->blink) {
309 if (bitbang_interface->blink(1) != ERROR_OK)
310 return ERROR_FAIL;
311 }
312
313 while (cmd) {
314 switch (cmd->type) {
315 case JTAG_RUNTEST:
316 LOG_DEBUG_IO("runtest %i cycles, end in %s",
317 cmd->cmd.runtest->num_cycles,
318 tap_state_name(cmd->cmd.runtest->end_state));
319 bitbang_end_state(cmd->cmd.runtest->end_state);
320 if (bitbang_runtest(cmd->cmd.runtest->num_cycles) != ERROR_OK)
321 return ERROR_FAIL;
322 break;
323
324 case JTAG_STABLECLOCKS:
325 /* this is only allowed while in a stable state. A check for a stable
326 * state was done in jtag_add_clocks()
327 */
328 if (bitbang_stableclocks(cmd->cmd.stableclocks->num_cycles) != ERROR_OK)
329 return ERROR_FAIL;
330 break;
331
332 case JTAG_TLR_RESET:
333 LOG_DEBUG_IO("statemove end in %s",
334 tap_state_name(cmd->cmd.statemove->end_state));
335 bitbang_end_state(cmd->cmd.statemove->end_state);
336 if (bitbang_state_move(0) != ERROR_OK)
337 return ERROR_FAIL;
338 break;
339 case JTAG_PATHMOVE:
340 LOG_DEBUG_IO("pathmove: %i states, end in %s",
341 cmd->cmd.pathmove->num_states,
342 tap_state_name(cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]));
343 if (bitbang_path_move(cmd->cmd.pathmove) != ERROR_OK)
344 return ERROR_FAIL;
345 break;
346 case JTAG_SCAN:
347 bitbang_end_state(cmd->cmd.scan->end_state);
348 scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
349 LOG_DEBUG_IO("%s scan %d bits; end in %s",
350 (cmd->cmd.scan->ir_scan) ? "IR" : "DR",
351 scan_size,
352 tap_state_name(cmd->cmd.scan->end_state));
353 type = jtag_scan_type(cmd->cmd.scan);
354 if (bitbang_scan(cmd->cmd.scan->ir_scan, type, buffer,
355 scan_size) != ERROR_OK)
356 return ERROR_FAIL;
357 if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
358 retval = ERROR_JTAG_QUEUE_FAILED;
359 free(buffer);
360 break;
361 case JTAG_SLEEP:
362 LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
363 if (bitbang_interface->flush && (bitbang_interface->flush() != ERROR_OK))
364 return ERROR_FAIL;
365 bitbang_sleep(cmd->cmd.sleep->us);
366 break;
367 case JTAG_TMS:
368 retval = bitbang_execute_tms(cmd);
369 break;
370 default:
371 LOG_ERROR("BUG: unknown JTAG command type encountered");
372 exit(-1);
373 }
374 cmd = cmd->next;
375 }
376 if (bitbang_interface->blink) {
377 if (bitbang_interface->blink(0) != ERROR_OK)
378 return ERROR_FAIL;
379 }
380
381 return retval;
382 }
383
384 static int queued_retval;
385
386 static int bitbang_swd_init(void)
387 {
388 LOG_DEBUG("bitbang_swd_init");
389 return ERROR_OK;
390 }
391
392 static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt)
393 {
394 if (bitbang_interface->blink) {
395 /* FIXME: we should manage errors */
396 bitbang_interface->blink(1);
397 }
398
399 for (unsigned int i = offset; i < bit_cnt + offset; i++) {
400 int bytec = i/8;
401 int bcval = 1 << (i % 8);
402 int swdio = !rnw && (buf[bytec] & bcval);
403
404 bitbang_interface->swd_write(0, swdio);
405
406 if (rnw && buf) {
407 if (bitbang_interface->swdio_read())
408 buf[bytec] |= bcval;
409 else
410 buf[bytec] &= ~bcval;
411 }
412
413 bitbang_interface->swd_write(1, swdio);
414 }
415
416 if (bitbang_interface->blink) {
417 /* FIXME: we should manage errors */
418 bitbang_interface->blink(0);
419 }
420 }
421
422 static int bitbang_swd_switch_seq(enum swd_special_seq seq)
423 {
424 switch (seq) {
425 case LINE_RESET:
426 LOG_DEBUG_IO("SWD line reset");
427 bitbang_swd_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len);
428 break;
429 case JTAG_TO_SWD:
430 LOG_DEBUG("JTAG-to-SWD");
431 bitbang_swd_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
432 break;
433 case JTAG_TO_DORMANT:
434 LOG_DEBUG("JTAG-to-DORMANT");
435 bitbang_swd_exchange(false, (uint8_t *)swd_seq_jtag_to_dormant, 0, swd_seq_jtag_to_dormant_len);
436 break;
437 case SWD_TO_JTAG:
438 LOG_DEBUG("SWD-to-JTAG");
439 bitbang_swd_exchange(false, (uint8_t *)swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len);
440 break;
441 case SWD_TO_DORMANT:
442 LOG_DEBUG("SWD-to-DORMANT");
443 bitbang_swd_exchange(false, (uint8_t *)swd_seq_swd_to_dormant, 0, swd_seq_swd_to_dormant_len);
444 break;
445 case DORMANT_TO_SWD:
446 LOG_DEBUG("DORMANT-to-SWD");
447 bitbang_swd_exchange(false, (uint8_t *)swd_seq_dormant_to_swd, 0, swd_seq_dormant_to_swd_len);
448 break;
449 case DORMANT_TO_JTAG:
450 LOG_DEBUG("DORMANT-to-JTAG");
451 bitbang_swd_exchange(false, (uint8_t *)swd_seq_dormant_to_jtag, 0, swd_seq_dormant_to_jtag_len);
452 break;
453 default:
454 LOG_ERROR("Sequence %d not supported", seq);
455 return ERROR_FAIL;
456 }
457
458 return ERROR_OK;
459 }
460
461 static void swd_clear_sticky_errors(void)
462 {
463 bitbang_swd_write_reg(swd_cmd(false, false, DP_ABORT),
464 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
465 }
466
467 static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
468 {
469 assert(cmd & SWD_CMD_RNW);
470
471 if (queued_retval != ERROR_OK) {
472 LOG_DEBUG("Skip bitbang_swd_read_reg because queued_retval=%d", queued_retval);
473 return;
474 }
475
476 for (;;) {
477 uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
478
479 cmd |= SWD_CMD_START | SWD_CMD_PARK;
480 bitbang_swd_exchange(false, &cmd, 0, 8);
481
482 bitbang_interface->swdio_drive(false);
483 bitbang_swd_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 32 + 1 + 1);
484 bitbang_interface->swdio_drive(true);
485
486 int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
487 uint32_t data = buf_get_u32(trn_ack_data_parity_trn, 1 + 3, 32);
488 int parity = buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 32, 1);
489
490 LOG_DEBUG_IO("%s %s read reg %X = %08" PRIx32,
491 ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
492 cmd & SWD_CMD_APNDP ? "AP" : "DP",
493 (cmd & SWD_CMD_A32) >> 1,
494 data);
495
496 if (ack == SWD_ACK_WAIT) {
497 swd_clear_sticky_errors();
498 continue;
499 } else if (ack != SWD_ACK_OK) {
500 queued_retval = swd_ack_to_error_code(ack);
501 return;
502 }
503
504 if (parity != parity_u32(data)) {
505 LOG_ERROR("Wrong parity detected");
506 queued_retval = ERROR_FAIL;
507 return;
508 }
509 if (value)
510 *value = data;
511 if (cmd & SWD_CMD_APNDP)
512 bitbang_swd_exchange(true, NULL, 0, ap_delay_clk);
513 return;
514 }
515 }
516
517 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
518 {
519 assert(!(cmd & SWD_CMD_RNW));
520
521 if (queued_retval != ERROR_OK) {
522 LOG_DEBUG("Skip bitbang_swd_write_reg because queued_retval=%d", queued_retval);
523 return;
524 }
525
526 /* Devices do not reply to DP_TARGETSEL write cmd, ignore received ack */
527 bool check_ack = swd_cmd_returns_ack(cmd);
528
529 /* init the array to silence scan-build */
530 uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)] = {0};
531 for (;;) {
532 buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32, value);
533 buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(value));
534
535 cmd |= SWD_CMD_START | SWD_CMD_PARK;
536 bitbang_swd_exchange(false, &cmd, 0, 8);
537
538 bitbang_interface->swdio_drive(false);
539 bitbang_swd_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3);
540
541 /* Avoid a glitch on SWDIO when changing the direction to output.
542 * To keep performance penalty minimal, pre-write the first data
543 * bit to SWDIO GPIO output buffer while clocking the turnaround bit.
544 * Following swdio_drive(true) outputs the pre-written value
545 * and the same value is rewritten by the next swd_write()
546 * instead of glitching SWDIO
547 * HiZ/pull-up --------------> 0 -------------> 1
548 * swdio_drive(true) swd_write(0,1)
549 * in case of data bit 0 = 1
550 */
551 bitbang_swd_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 1);
552 bitbang_interface->swdio_drive(true);
553 bitbang_swd_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 32 + 1);
554
555 int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
556
557 LOG_DEBUG_IO("%s%s %s write reg %X = %08" PRIx32,
558 check_ack ? "" : "ack ignored ",
559 ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
560 cmd & SWD_CMD_APNDP ? "AP" : "DP",
561 (cmd & SWD_CMD_A32) >> 1,
562 buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32));
563
564 if (check_ack) {
565 if (ack == SWD_ACK_WAIT) {
566 swd_clear_sticky_errors();
567 continue;
568 } else if (ack != SWD_ACK_OK) {
569 queued_retval = swd_ack_to_error_code(ack);
570 return;
571 }
572 }
573
574 if (cmd & SWD_CMD_APNDP)
575 bitbang_swd_exchange(true, NULL, 0, ap_delay_clk);
576 return;
577 }
578 }
579
580 static int bitbang_swd_run_queue(void)
581 {
582 /* A transaction must be followed by another transaction or at least 8 idle cycles to
583 * ensure that data is clocked through the AP. */
584 bitbang_swd_exchange(true, NULL, 0, 8);
585
586 int retval = queued_retval;
587 queued_retval = ERROR_OK;
588 LOG_DEBUG_IO("SWD queue return value: %02x", retval);
589 return retval;
590 }
591
592 const struct swd_driver bitbang_swd = {
593 .init = bitbang_swd_init,
594 .switch_seq = bitbang_swd_switch_seq,
595 .read_reg = bitbang_swd_read_reg,
596 .write_reg = bitbang_swd_write_reg,
597 .run = bitbang_swd_run_queue,
598 };

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2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)