1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2008 by Spencer Oliver *
8 * spen@spen-soft.co.uk *
10 * Copyright (C) 2011 Øyvind Harboe *
11 * oyvind.harboe@zylin.com *
12 ***************************************************************************/
19 #include <helper/binarybuffer.h>
20 #include <target/algorithm.h>
21 #include <target/cortex_m.h>
23 /* Regarding performance:
25 * Short story - it might be best to leave the performance at
28 * You may see a jump in speed if you change to using
29 * 32bit words for the block programming.
31 * Its a shame you cannot use the double word as its
32 * even faster - but you require external VPP for that mode.
34 * Having said all that 16bit writes give us the widest vdd
35 * operating range, so may be worth adding a note to that effect.
39 /* Danger!!!! The STM32F1x and STM32F2x series actually have
40 * quite different flash controllers.
42 * What's more scary is that the names of the registers and their
43 * addresses are the same, but the actual bits and what they do are
44 * can be very different.
46 * To reduce testing complexity and dangers of regressions,
47 * a separate file is used for stm32fx2x.
49 * Sector sizes in kiBytes:
50 * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
51 * 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
52 * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
53 * 1 MiByte STM32F42x/43x part with DB1M Option set:
54 * 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
57 * 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
60 * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
63 * 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
64 * 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
65 * 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
66 * 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
68 * Protection size is sector size.
70 * Tested with STM3220F-EVAL board.
72 * STM32F4xx series for reference.
75 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
78 * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
79 * PROGRAMMING_MANUAL/CD00233952.pdf
81 * STM32F7xx series for reference.
84 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
87 * http://www.st.com/resource/en/reference_manual/dm00224583.pdf
90 * http://www.st.com/resource/en/reference_manual/dm00305666.pdf
93 * http://www.st.com/resource/en/reference_manual/dm00305990.pdf
95 * STM32F1x series - notice that this code was copy, pasted and knocked
96 * into a stm32f2x driver, so in case something has been converted or
97 * bugs haven't been fixed, here are the original manuals:
99 * RM0008 - Reference manual
101 * RM0042, the Flash programming manual for low-, medium- high-density and
102 * connectivity line STM32F10x devices
104 * PM0068, the Flash programming manual for XL-density STM32F10x devices.
108 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
109 #define FLASH_ERASE_TIMEOUT 10000
110 #define FLASH_WRITE_TIMEOUT 5
112 /* Mass erase time can be as high as 32 s in x8 mode. */
113 #define FLASH_MASS_ERASE_TIMEOUT 33000
115 #define FLASH_BANK_BASE 0x80000000
117 #define STM32F2_OTP_SIZE 512
118 #define STM32F2_OTP_SECTOR_SIZE 32
119 #define STM32F2_OTP_BANK_BASE 0x1fff7800
120 #define STM32F2_OTP_LOCK_BASE ((STM32F2_OTP_BANK_BASE) + (STM32F2_OTP_SIZE))
122 /* see RM0410 section 3.6 "One-time programmable bytes" */
123 #define STM32F7_OTP_SECTOR_SIZE 64
124 #define STM32F7_OTP_SIZE 1024
125 #define STM32F7_OTP_BANK_BASE 0x1ff0f000
126 #define STM32F7_OTP_LOCK_BASE ((STM32F7_OTP_BANK_BASE) + (STM32F7_OTP_SIZE))
128 #define STM32_FLASH_BASE 0x40023c00
129 #define STM32_FLASH_ACR 0x40023c00
130 #define STM32_FLASH_KEYR 0x40023c04
131 #define STM32_FLASH_OPTKEYR 0x40023c08
132 #define STM32_FLASH_SR 0x40023c0C
133 #define STM32_FLASH_CR 0x40023c10
134 #define STM32_FLASH_OPTCR 0x40023c14
135 #define STM32_FLASH_OPTCR1 0x40023c18
136 #define STM32_FLASH_OPTCR2 0x40023c1c
138 /* FLASH_CR register bits */
139 #define FLASH_PG (1 << 0)
140 #define FLASH_SER (1 << 1)
141 #define FLASH_MER (1 << 2) /* MER/MER1 for f76x/77x */
142 #define FLASH_MER1 (1 << 15) /* MER2 for f76x/77x, confusing ... */
143 #define FLASH_STRT (1 << 16)
144 #define FLASH_PSIZE_8 (0 << 8)
145 #define FLASH_PSIZE_16 (1 << 8)
146 #define FLASH_PSIZE_32 (2 << 8)
147 #define FLASH_PSIZE_64 (3 << 8)
148 /* The sector number encoding is not straight binary for dual bank flash. */
149 #define FLASH_SNB(a) ((a) << 3)
150 #define FLASH_LOCK (1 << 31)
152 /* FLASH_SR register bits */
153 #define FLASH_BSY (1 << 16)
154 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
155 #define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
156 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
157 #define FLASH_WRPERR (1 << 4) /* Write protection error */
158 #define FLASH_OPERR (1 << 1) /* Operation error */
160 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
162 /* STM32_FLASH_OPTCR register bits */
163 #define OPTCR_LOCK (1 << 0)
164 #define OPTCR_START (1 << 1)
165 #define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
166 #define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
167 #define OPTCR_SPRMOD (1 << 31) /* switches PCROPi/nWPRi interpretation */
169 /* STM32_FLASH_OPTCR2 register bits */
170 #define OPTCR2_PCROP_RDP (1 << 31) /* erase PCROP zone when decreasing RDP */
172 /* register unlock keys */
173 #define KEY1 0x45670123
174 #define KEY2 0xCDEF89AB
176 /* option register unlock key */
177 #define OPTKEY1 0x08192A3B
178 #define OPTKEY2 0x4C5D6E7F
180 struct stm32x_options
{
182 uint16_t user_options
; /* bit 0-7 usual options, bit 8-11 extra options */
185 uint32_t optcr2_pcrop
;
188 struct stm32x_flash_bank
{
189 struct stm32x_options option_bytes
;
192 bool has_large_mem
; /* F42x/43x/469/479/7xx in dual bank mode */
193 bool has_extra_options
; /* F42x/43x/469/479/7xx */
194 bool has_boot_addr
; /* F7xx */
195 bool has_optcr2_pcrop
; /* F72x/73x */
196 unsigned int protection_bits
; /* F413/423 */
197 uint32_t user_bank_size
;
200 static bool stm32x_is_otp(struct flash_bank
*bank
)
202 return bank
->base
== STM32F2_OTP_BANK_BASE
||
203 bank
->base
== STM32F7_OTP_BANK_BASE
;
206 static bool stm32x_otp_is_f7(struct flash_bank
*bank
)
208 return bank
->base
== STM32F7_OTP_BANK_BASE
;
211 static int stm32x_is_otp_unlocked(struct flash_bank
*bank
)
213 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
215 return stm32x_info
->otp_unlocked
;
218 static int stm32x_otp_disable(struct flash_bank
*bank
)
220 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
222 LOG_INFO("OTP memory bank #%u is disabled for write commands.",
224 stm32x_info
->otp_unlocked
= false;
228 static int stm32x_otp_enable(struct flash_bank
*bank
)
230 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
232 if (!stm32x_info
->otp_unlocked
) {
233 LOG_INFO("OTP memory bank #%u is enabled for write commands.",
235 stm32x_info
->otp_unlocked
= true;
237 LOG_WARNING("OTP memory bank #%u is already enabled for write commands.",
243 /* flash bank stm32x <base> <size> 0 0 <target#>
245 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
247 struct stm32x_flash_bank
*stm32x_info
;
250 return ERROR_COMMAND_SYNTAX_ERROR
;
252 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
253 bank
->driver_priv
= stm32x_info
;
255 stm32x_info
->probed
= false;
256 stm32x_info
->otp_unlocked
= false;
257 stm32x_info
->user_bank_size
= bank
->size
;
262 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
267 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
269 struct target
*target
= bank
->target
;
270 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
273 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
275 struct target
*target
= bank
->target
;
277 int retval
= ERROR_OK
;
279 /* wait for busy to clear */
281 retval
= stm32x_get_flash_status(bank
, &status
);
282 if (retval
!= ERROR_OK
)
284 LOG_DEBUG("status: 0x%" PRIx32
, status
);
285 if ((status
& FLASH_BSY
) == 0)
287 if (timeout
-- <= 0) {
288 LOG_ERROR("timed out waiting for flash");
295 if (status
& FLASH_WRPERR
) {
296 LOG_ERROR("stm32x device protected");
300 /* Clear but report errors */
301 if (status
& FLASH_ERROR
) {
302 if (retval
== ERROR_OK
)
304 /* If this operation fails, we ignore it and report the original
307 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
308 status
& FLASH_ERROR
);
313 static int stm32x_unlock_reg(struct target
*target
)
317 /* first check if not already unlocked
318 * otherwise writing on STM32_FLASH_KEYR will fail
320 int retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
321 if (retval
!= ERROR_OK
)
324 if ((ctrl
& FLASH_LOCK
) == 0)
327 /* unlock flash registers */
328 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
329 if (retval
!= ERROR_OK
)
332 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
333 if (retval
!= ERROR_OK
)
336 retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
337 if (retval
!= ERROR_OK
)
340 if (ctrl
& FLASH_LOCK
) {
341 LOG_ERROR("flash not unlocked STM32_FLASH_CR: 0x%" PRIx32
, ctrl
);
342 return ERROR_TARGET_FAILURE
;
348 static int stm32x_unlock_option_reg(struct target
*target
)
352 int retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &ctrl
);
353 if (retval
!= ERROR_OK
)
356 if ((ctrl
& OPTCR_LOCK
) == 0)
359 /* unlock option registers */
360 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
361 if (retval
!= ERROR_OK
)
364 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
365 if (retval
!= ERROR_OK
)
368 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &ctrl
);
369 if (retval
!= ERROR_OK
)
372 if (ctrl
& OPTCR_LOCK
) {
373 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32
, ctrl
);
374 return ERROR_TARGET_FAILURE
;
380 static int stm32x_read_options(struct flash_bank
*bank
)
383 struct stm32x_flash_bank
*stm32x_info
= NULL
;
384 struct target
*target
= bank
->target
;
386 stm32x_info
= bank
->driver_priv
;
388 /* read current option bytes */
389 int retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
390 if (retval
!= ERROR_OK
)
393 /* caution: F2 implements 5 bits (WDG_SW only)
394 * whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
395 stm32x_info
->option_bytes
.user_options
= optiondata
& 0xfc;
396 stm32x_info
->option_bytes
.RDP
= (optiondata
>> 8) & 0xff;
397 stm32x_info
->option_bytes
.protection
=
398 (optiondata
>> 16) & (~(0xffff << stm32x_info
->protection_bits
) & 0xffff);
400 if (stm32x_info
->has_extra_options
) {
401 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
402 stm32x_info
->option_bytes
.user_options
|= (optiondata
>> 20) &
403 ((0xf00 << (stm32x_info
->protection_bits
- 12)) & 0xf00);
406 if (stm32x_info
->has_large_mem
|| stm32x_info
->has_boot_addr
) {
407 retval
= target_read_u32(target
, STM32_FLASH_OPTCR1
, &optiondata
);
408 if (retval
!= ERROR_OK
)
411 /* FLASH_OPTCR1 has quite different meanings ... */
412 if (stm32x_info
->has_boot_addr
) {
413 /* for F7xx it contains boot0 and boot1 */
414 stm32x_info
->option_bytes
.boot_addr
= optiondata
;
416 /* for F42x/43x/469/479 it contains 12 additional protection bits */
417 stm32x_info
->option_bytes
.protection
|= (optiondata
>> 4) & 0x00fff000;
421 if (stm32x_info
->has_optcr2_pcrop
) {
422 retval
= target_read_u32(target
, STM32_FLASH_OPTCR2
, &optiondata
);
423 if (retval
!= ERROR_OK
)
426 stm32x_info
->option_bytes
.optcr2_pcrop
= optiondata
;
427 if (stm32x_info
->has_optcr2_pcrop
&&
428 (stm32x_info
->option_bytes
.optcr2_pcrop
& ~OPTCR2_PCROP_RDP
)) {
429 LOG_INFO("PCROP Engaged");
432 stm32x_info
->option_bytes
.optcr2_pcrop
= 0x0;
435 if (stm32x_info
->option_bytes
.RDP
!= 0xAA)
436 LOG_INFO("Device Security Bit Set");
441 static int stm32x_write_options(struct flash_bank
*bank
)
443 struct stm32x_flash_bank
*stm32x_info
= NULL
;
444 struct target
*target
= bank
->target
;
445 uint32_t optiondata
, optiondata2
;
447 stm32x_info
= bank
->driver_priv
;
449 int retval
= stm32x_unlock_option_reg(target
);
450 if (retval
!= ERROR_OK
)
453 /* rebuild option data */
454 optiondata
= stm32x_info
->option_bytes
.user_options
& 0xfc;
455 optiondata
|= stm32x_info
->option_bytes
.RDP
<< 8;
456 optiondata
|= (stm32x_info
->option_bytes
.protection
&
457 (~(0xffff << stm32x_info
->protection_bits
))) << 16;
459 if (stm32x_info
->has_extra_options
) {
460 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
461 optiondata
|= (stm32x_info
->option_bytes
.user_options
&
462 ((0xf00 << (stm32x_info
->protection_bits
- 12)) & 0xf00)) << 20;
465 if (stm32x_info
->has_large_mem
|| stm32x_info
->has_boot_addr
) {
466 if (stm32x_info
->has_boot_addr
) {
467 /* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
468 optiondata2
= stm32x_info
->option_bytes
.boot_addr
;
470 /* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
471 optiondata2
= (stm32x_info
->option_bytes
.protection
& 0x00fff000) << 4;
474 retval
= target_write_u32(target
, STM32_FLASH_OPTCR1
, optiondata2
);
475 if (retval
!= ERROR_OK
)
479 /* program extra pcrop register */
480 if (stm32x_info
->has_optcr2_pcrop
) {
481 retval
= target_write_u32(target
, STM32_FLASH_OPTCR2
,
482 stm32x_info
->option_bytes
.optcr2_pcrop
);
483 if (retval
!= ERROR_OK
)
487 /* program options */
488 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
);
489 if (retval
!= ERROR_OK
)
492 /* start programming cycle */
493 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
| OPTCR_START
);
494 if (retval
!= ERROR_OK
)
497 /* wait for completion, this might trigger a security erase and take a while */
498 retval
= stm32x_wait_status_busy(bank
, FLASH_MASS_ERASE_TIMEOUT
);
499 if (retval
!= ERROR_OK
)
502 /* relock registers */
503 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
| OPTCR_LOCK
);
504 if (retval
!= ERROR_OK
)
510 static int stm32x_otp_read_protect(struct flash_bank
*bank
)
512 struct target
*target
= bank
->target
;
517 lock_base
= stm32x_otp_is_f7(bank
) ? STM32F7_OTP_LOCK_BASE
518 : STM32F2_OTP_LOCK_BASE
;
520 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
521 retval
= target_read_u8(target
, lock_base
+ i
, &lock
);
522 if (retval
!= ERROR_OK
)
524 bank
->sectors
[i
].is_protected
= !lock
;
530 static int stm32x_otp_protect(struct flash_bank
*bank
, unsigned int first
,
533 struct target
*target
= bank
->target
;
538 assert((first
<= last
) && (last
< bank
->num_sectors
));
540 lock_base
= stm32x_otp_is_f7(bank
) ? STM32F7_OTP_LOCK_BASE
541 : STM32F2_OTP_LOCK_BASE
;
543 for (i
= first
; first
<= last
; i
++) {
544 retval
= target_read_u8(target
, lock_base
+ i
, &lock
);
545 if (retval
!= ERROR_OK
)
551 retval
= target_write_u8(target
, lock_base
+ i
, lock
);
552 if (retval
!= ERROR_OK
)
559 static int stm32x_protect_check(struct flash_bank
*bank
)
561 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
562 struct flash_sector
*prot_blocks
;
563 unsigned int num_prot_blocks
;
566 /* if it's the OTP bank, look at the lock bits there */
567 if (stm32x_is_otp(bank
))
568 return stm32x_otp_read_protect(bank
);
570 /* read write protection settings */
571 retval
= stm32x_read_options(bank
);
572 if (retval
!= ERROR_OK
) {
573 LOG_DEBUG("unable to read option bytes");
577 if (bank
->prot_blocks
) {
578 num_prot_blocks
= bank
->num_prot_blocks
;
579 prot_blocks
= bank
->prot_blocks
;
581 num_prot_blocks
= bank
->num_sectors
;
582 prot_blocks
= bank
->sectors
;
585 for (unsigned int i
= 0; i
< num_prot_blocks
; i
++)
586 prot_blocks
[i
].is_protected
=
587 ~(stm32x_info
->option_bytes
.protection
>> i
) & 1;
592 static int stm32x_erase(struct flash_bank
*bank
, unsigned int first
,
595 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
596 struct target
*target
= bank
->target
;
598 if (stm32x_is_otp(bank
)) {
599 LOG_ERROR("Cannot erase OTP memory");
603 assert((first
<= last
) && (last
< bank
->num_sectors
));
605 if (bank
->target
->state
!= TARGET_HALTED
) {
606 LOG_ERROR("Target not halted");
607 return ERROR_TARGET_NOT_HALTED
;
611 retval
= stm32x_unlock_reg(target
);
612 if (retval
!= ERROR_OK
)
617 To erase a sector, follow the procedure below:
618 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
620 2. Set the SER bit and select the sector
621 you wish to erase (SNB) in the FLASH_CR register
622 3. Set the STRT bit in the FLASH_CR register
623 4. Wait for the BSY bit to be cleared
626 for (unsigned int i
= first
; i
<= last
; i
++) {
628 if (stm32x_info
->has_large_mem
&& i
>= (bank
->num_sectors
/ 2))
629 snb
= (i
- (bank
->num_sectors
/ 2)) | 0x10;
633 retval
= target_write_u32(target
,
634 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_SER
| FLASH_SNB(snb
) | FLASH_STRT
);
635 if (retval
!= ERROR_OK
)
638 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
639 if (retval
!= ERROR_OK
)
643 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
644 if (retval
!= ERROR_OK
)
650 static int stm32x_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
653 struct target
*target
= bank
->target
;
654 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
656 if (target
->state
!= TARGET_HALTED
) {
657 LOG_ERROR("Target not halted");
658 return ERROR_TARGET_NOT_HALTED
;
661 if (stm32x_is_otp(bank
)) {
663 LOG_ERROR("OTP protection can only be enabled");
664 return ERROR_COMMAND_ARGUMENT_INVALID
;
667 return stm32x_otp_protect(bank
, first
, last
);
670 /* read protection settings */
671 int retval
= stm32x_read_options(bank
);
672 if (retval
!= ERROR_OK
) {
673 LOG_DEBUG("unable to read option bytes");
677 for (unsigned int i
= first
; i
<= last
; i
++) {
679 stm32x_info
->option_bytes
.protection
&= ~(1 << i
);
681 stm32x_info
->option_bytes
.protection
|= (1 << i
);
684 retval
= stm32x_write_options(bank
);
685 if (retval
!= ERROR_OK
)
691 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
692 uint32_t offset
, uint32_t count
)
694 struct target
*target
= bank
->target
;
695 uint32_t buffer_size
= 16384;
696 struct working_area
*write_algorithm
;
697 struct working_area
*source
;
698 uint32_t address
= bank
->base
+ offset
;
699 struct reg_param reg_params
[5];
700 struct armv7m_algorithm armv7m_info
;
701 int retval
= ERROR_OK
;
703 static const uint8_t stm32x_flash_write_code
[] = {
704 #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
707 if (stm32x_is_otp(bank
) && !stm32x_is_otp_unlocked(bank
)) {
708 LOG_ERROR("OTP memory bank is disabled for write commands.");
712 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
713 &write_algorithm
) != ERROR_OK
) {
714 LOG_WARNING("no working area available, can't do block memory writes");
715 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
718 retval
= target_write_buffer(target
, write_algorithm
->address
,
719 sizeof(stm32x_flash_write_code
),
720 stm32x_flash_write_code
);
721 if (retval
!= ERROR_OK
) {
722 target_free_working_area(target
, write_algorithm
);
727 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
729 if (buffer_size
<= 256) {
730 /* we already allocated the writing code, but failed to get a
731 * buffer, free the algorithm */
732 target_free_working_area(target
, write_algorithm
);
734 LOG_WARNING("no large enough working area available, can't do block memory writes");
735 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
739 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
740 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
742 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
743 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
744 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
745 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (halfword-16bit) */
746 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash base */
748 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
749 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
750 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
751 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
752 buf_set_u32(reg_params
[4].value
, 0, 32, STM32_FLASH_BASE
);
754 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
757 source
->address
, source
->size
,
758 write_algorithm
->address
, 0,
761 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
762 LOG_ERROR("error executing stm32x flash write algorithm");
764 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
766 if (error
& FLASH_WRPERR
)
767 LOG_ERROR("flash memory write protected");
770 LOG_ERROR("flash write failed = 0x%08" PRIx32
, error
);
771 /* Clear but report errors */
772 target_write_u32(target
, STM32_FLASH_SR
, error
);
777 target_free_working_area(target
, source
);
778 target_free_working_area(target
, write_algorithm
);
780 destroy_reg_param(®_params
[0]);
781 destroy_reg_param(®_params
[1]);
782 destroy_reg_param(®_params
[2]);
783 destroy_reg_param(®_params
[3]);
784 destroy_reg_param(®_params
[4]);
789 static int stm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
790 uint32_t offset
, uint32_t count
)
792 struct target
*target
= bank
->target
;
793 uint32_t words_remaining
= (count
/ 2);
794 uint32_t bytes_remaining
= (count
& 0x00000001);
795 uint32_t address
= bank
->base
+ offset
;
796 uint32_t bytes_written
= 0;
799 if (bank
->target
->state
!= TARGET_HALTED
) {
800 LOG_ERROR("Target not halted");
801 return ERROR_TARGET_NOT_HALTED
;
805 LOG_WARNING("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
806 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
809 retval
= stm32x_unlock_reg(target
);
810 if (retval
!= ERROR_OK
)
813 /* multiple half words (2-byte) to be programmed? */
814 if (words_remaining
> 0) {
815 /* try using a block write */
816 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
817 if (retval
!= ERROR_OK
) {
818 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
819 /* if block write failed (no sufficient working area),
820 * we use normal (slow) single dword accesses */
821 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
824 buffer
+= words_remaining
* 2;
825 address
+= words_remaining
* 2;
830 if ((retval
!= ERROR_OK
) && (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
))
835 The Flash memory programming sequence is as follows:
836 1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
838 2. Set the PG bit in the FLASH_CR register
839 3. Perform the data write operation(s) to the desired memory address (inside main
840 memory block or OTP area):
841 – – Half-word access in case of x16 parallelism
842 – Word access in case of x32 parallelism
845 Byte access in case of x8 parallelism
846 Double word access in case of x64 parallelism
847 Wait for the BSY bit to be cleared
849 while (words_remaining
> 0) {
850 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
851 FLASH_PG
| FLASH_PSIZE_16
);
852 if (retval
!= ERROR_OK
)
855 retval
= target_write_memory(target
, address
, 2, 1, buffer
+ bytes_written
);
856 if (retval
!= ERROR_OK
)
859 retval
= stm32x_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
860 if (retval
!= ERROR_OK
)
868 if (bytes_remaining
) {
869 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
870 FLASH_PG
| FLASH_PSIZE_8
);
871 if (retval
!= ERROR_OK
)
873 retval
= target_write_u8(target
, address
, buffer
[bytes_written
]);
874 if (retval
!= ERROR_OK
)
877 retval
= stm32x_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
878 if (retval
!= ERROR_OK
)
882 return target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
885 static void setup_sector(struct flash_bank
*bank
, unsigned int i
,
888 assert(i
< bank
->num_sectors
);
889 bank
->sectors
[i
].offset
= bank
->size
;
890 bank
->sectors
[i
].size
= size
;
891 bank
->size
+= bank
->sectors
[i
].size
;
892 LOG_DEBUG("sector %u: %ukBytes", i
, size
>> 10);
895 static uint16_t sector_size_in_kb(unsigned int i
, uint16_t max_sector_size_in_kb
)
898 return max_sector_size_in_kb
/ 8;
900 return max_sector_size_in_kb
/ 2;
901 return max_sector_size_in_kb
;
904 static unsigned int calculate_number_of_sectors(struct flash_bank
*bank
,
905 uint16_t flash_size_in_kb
,
906 uint16_t max_sector_size_in_kb
)
908 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
909 uint16_t remaining_flash_size_in_kb
= flash_size_in_kb
;
910 unsigned int nr_sectors
;
912 /* Dual Bank Flash has two identically-arranged banks of sectors. */
913 if (stm32x_info
->has_large_mem
)
914 remaining_flash_size_in_kb
/= 2;
916 for (nr_sectors
= 0; remaining_flash_size_in_kb
> 0; nr_sectors
++) {
917 uint16_t size_in_kb
= sector_size_in_kb(nr_sectors
, max_sector_size_in_kb
);
918 if (size_in_kb
> remaining_flash_size_in_kb
) {
919 LOG_INFO("%s Bank %" PRIu16
" kiB final sector clipped to %" PRIu16
" kiB",
920 stm32x_info
->has_large_mem
? "Dual" : "Single",
921 flash_size_in_kb
, remaining_flash_size_in_kb
);
922 remaining_flash_size_in_kb
= 0;
924 remaining_flash_size_in_kb
-= size_in_kb
;
928 return stm32x_info
->has_large_mem
? nr_sectors
*2 : nr_sectors
;
931 static void setup_bank(struct flash_bank
*bank
, unsigned int start
,
932 uint16_t flash_size_in_kb
, uint16_t max_sector_size_in_kb
)
934 uint16_t remaining_flash_size_in_kb
= flash_size_in_kb
;
935 unsigned int sector_index
= 0;
936 while (remaining_flash_size_in_kb
> 0) {
937 uint16_t size_in_kb
= sector_size_in_kb(sector_index
, max_sector_size_in_kb
);
938 if (size_in_kb
> remaining_flash_size_in_kb
) {
939 /* Clip last sector. Already warned in
940 * calculate_number_of_sectors. */
941 size_in_kb
= remaining_flash_size_in_kb
;
943 setup_sector(bank
, start
+ sector_index
, size_in_kb
* 1024);
944 remaining_flash_size_in_kb
-= size_in_kb
;
949 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
951 /* this checks for a stm32f4x errata issue where a
952 * stm32f2x DBGMCU_IDCODE is incorrectly returned.
953 * If the issue is detected target is forced to stm32f4x Rev A.
954 * Only effects Rev A silicon */
956 struct target
*target
= bank
->target
;
958 /* read stm32 device id register */
959 int retval
= target_read_u32(target
, 0xE0042000, device_id
);
960 if (retval
!= ERROR_OK
)
963 if ((*device_id
& 0xfff) == 0x411
964 && cortex_m_get_impl_part(target
) == CORTEX_M4_PARTNO
) {
965 *device_id
&= ~((0xFFFF << 16) | 0xfff);
966 *device_id
|= (0x1000 << 16) | 0x413;
967 LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
972 static int stm32x_probe(struct flash_bank
*bank
)
974 struct target
*target
= bank
->target
;
975 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
976 unsigned int num_prot_blocks
, num_sectors
;
977 uint16_t flash_size_in_kb
;
978 uint16_t otp_size_in_b
;
979 uint16_t otp_sector_size
;
980 uint32_t flash_size_reg
= 0x1FFF7A22;
981 uint16_t max_sector_size_in_kb
= 128;
982 uint16_t max_flash_size_in_kb
;
984 uint32_t base_address
= 0x08000000;
986 stm32x_info
->probed
= false;
987 stm32x_info
->has_large_mem
= false;
988 stm32x_info
->has_boot_addr
= false;
989 stm32x_info
->has_extra_options
= false;
990 stm32x_info
->has_optcr2_pcrop
= false;
991 stm32x_info
->protection_bits
= 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
995 bank
->num_sectors
= 0;
996 bank
->sectors
= NULL
;
998 free(bank
->prot_blocks
);
999 bank
->num_prot_blocks
= 0;
1000 bank
->prot_blocks
= NULL
;
1002 if (!target_was_examined(target
)) {
1003 LOG_ERROR("Target not examined yet");
1004 return ERROR_TARGET_NOT_EXAMINED
;
1007 /* if explicitly called out as OTP bank, short circuit probe */
1008 if (stm32x_is_otp(bank
)) {
1009 if (stm32x_otp_is_f7(bank
)) {
1010 otp_size_in_b
= STM32F7_OTP_SIZE
;
1011 otp_sector_size
= STM32F7_OTP_SECTOR_SIZE
;
1013 otp_size_in_b
= STM32F2_OTP_SIZE
;
1014 otp_sector_size
= STM32F2_OTP_SECTOR_SIZE
;
1017 num_sectors
= otp_size_in_b
/ otp_sector_size
;
1018 LOG_INFO("flash size = %" PRIu16
" bytes", otp_size_in_b
);
1020 assert(num_sectors
> 0);
1022 bank
->num_sectors
= num_sectors
;
1023 bank
->sectors
= calloc(sizeof(struct flash_sector
), num_sectors
);
1025 if (stm32x_otp_is_f7(bank
))
1026 bank
->size
= STM32F7_OTP_SIZE
;
1028 bank
->size
= STM32F2_OTP_SIZE
;
1030 for (unsigned int i
= 0; i
< num_sectors
; i
++) {
1031 bank
->sectors
[i
].offset
= i
* otp_sector_size
;
1032 bank
->sectors
[i
].size
= otp_sector_size
;
1033 bank
->sectors
[i
].is_erased
= 1;
1034 bank
->sectors
[i
].is_protected
= 0;
1037 stm32x_info
->probed
= true;
1041 /* read stm32 device id register */
1042 int retval
= stm32x_get_device_id(bank
, &device_id
);
1043 if (retval
!= ERROR_OK
)
1045 LOG_INFO("device id = 0x%08" PRIx32
, device_id
);
1046 device_id
&= 0xfff; /* only bits 0-11 are used further on */
1048 /* set max flash size depending on family, id taken from AN2606 */
1049 switch (device_id
) {
1050 case 0x411: /* F20x/21x */
1051 case 0x413: /* F40x/41x */
1052 max_flash_size_in_kb
= 1024;
1055 case 0x419: /* F42x/43x */
1056 case 0x434: /* F469/479 */
1057 stm32x_info
->has_extra_options
= true;
1058 max_flash_size_in_kb
= 2048;
1061 case 0x423: /* F401xB/C */
1062 max_flash_size_in_kb
= 256;
1065 case 0x421: /* F446 */
1066 case 0x431: /* F411 */
1067 case 0x433: /* F401xD/E */
1068 case 0x441: /* F412 */
1069 max_flash_size_in_kb
= 512;
1072 case 0x458: /* F410 */
1073 max_flash_size_in_kb
= 128;
1076 case 0x449: /* F74x/75x */
1077 max_flash_size_in_kb
= 1024;
1078 max_sector_size_in_kb
= 256;
1079 flash_size_reg
= 0x1FF0F442;
1080 stm32x_info
->has_extra_options
= true;
1081 stm32x_info
->has_boot_addr
= true;
1084 case 0x451: /* F76x/77x */
1085 max_flash_size_in_kb
= 2048;
1086 max_sector_size_in_kb
= 256;
1087 flash_size_reg
= 0x1FF0F442;
1088 stm32x_info
->has_extra_options
= true;
1089 stm32x_info
->has_boot_addr
= true;
1092 case 0x452: /* F72x/73x */
1093 max_flash_size_in_kb
= 512;
1094 flash_size_reg
= 0x1FF07A22; /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
1095 stm32x_info
->has_extra_options
= true;
1096 stm32x_info
->has_boot_addr
= true;
1097 stm32x_info
->has_optcr2_pcrop
= true;
1100 case 0x463: /* F413x/423x */
1101 max_flash_size_in_kb
= 1536;
1102 stm32x_info
->has_extra_options
= true;
1103 stm32x_info
->protection_bits
= 15;
1104 num_prot_blocks
= 15;
1108 LOG_WARNING("Cannot identify target as a STM32 family.");
1112 /* get flash size from target. */
1113 retval
= target_read_u16(target
, flash_size_reg
, &flash_size_in_kb
);
1115 /* failed reading flash size or flash size invalid (early silicon),
1116 * default to max target family */
1117 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
1118 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %" PRIu16
"k flash",
1119 max_flash_size_in_kb
);
1120 flash_size_in_kb
= max_flash_size_in_kb
;
1123 /* if the user sets the size manually then ignore the probed value
1124 * this allows us to work around devices that have a invalid flash size register value */
1125 if (stm32x_info
->user_bank_size
) {
1126 LOG_INFO("ignoring flash probed value, using configured bank size");
1127 flash_size_in_kb
= stm32x_info
->user_bank_size
/ 1024;
1130 LOG_INFO("flash size = %" PRIu16
" KiB", flash_size_in_kb
);
1132 /* did we assign flash size? */
1133 assert(flash_size_in_kb
!= 0xffff);
1135 /* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
1136 if ((device_id
== 0x419) || (device_id
== 0x434)) {
1137 uint32_t optiondata
;
1138 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
1139 if (retval
!= ERROR_OK
) {
1140 LOG_DEBUG("unable to read option bytes");
1143 if ((flash_size_in_kb
> 1024) || (optiondata
& OPTCR_DB1M
)) {
1144 stm32x_info
->has_large_mem
= true;
1145 LOG_INFO("Dual Bank %" PRIu16
" kiB STM32F42x/43x/469/479 found", flash_size_in_kb
);
1147 stm32x_info
->has_large_mem
= false;
1148 LOG_INFO("Single Bank %" PRIu16
" kiB STM32F42x/43x/469/479 found", flash_size_in_kb
);
1152 /* F76x/77x devices have a dual bank option */
1153 if (device_id
== 0x451) {
1154 uint32_t optiondata
;
1155 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
1156 if (retval
!= ERROR_OK
) {
1157 LOG_DEBUG("unable to read option bytes");
1160 if (optiondata
& OPTCR_NDBANK
) {
1161 stm32x_info
->has_large_mem
= false;
1162 LOG_INFO("Single Bank %" PRIu16
" kiB STM32F76x/77x found", flash_size_in_kb
);
1164 stm32x_info
->has_large_mem
= true;
1165 max_sector_size_in_kb
>>= 1; /* sector size divided by 2 in dual-bank mode */
1166 LOG_INFO("Dual Bank %" PRIu16
" kiB STM32F76x/77x found", flash_size_in_kb
);
1170 /* calculate numbers of pages */
1171 unsigned int num_pages
= calculate_number_of_sectors(
1172 bank
, flash_size_in_kb
, max_sector_size_in_kb
);
1174 bank
->base
= base_address
;
1175 bank
->num_sectors
= num_pages
;
1176 bank
->sectors
= calloc(num_pages
, sizeof(struct flash_sector
));
1177 for (unsigned int i
= 0; i
< num_pages
; i
++) {
1178 bank
->sectors
[i
].is_erased
= -1;
1179 bank
->sectors
[i
].is_protected
= 0;
1182 LOG_DEBUG("allocated %u sectors", num_pages
);
1184 /* F76x/77x in dual bank mode */
1185 if ((device_id
== 0x451) && stm32x_info
->has_large_mem
)
1186 num_prot_blocks
= num_pages
>> 1;
1188 if (num_prot_blocks
) {
1189 bank
->prot_blocks
= malloc(sizeof(struct flash_sector
) * num_prot_blocks
);
1190 for (unsigned int i
= 0; i
< num_prot_blocks
; i
++)
1191 bank
->prot_blocks
[i
].is_protected
= 0;
1192 LOG_DEBUG("allocated %u prot blocks", num_prot_blocks
);
1195 if (stm32x_info
->has_large_mem
) {
1197 setup_bank(bank
, 0, flash_size_in_kb
>> 1, max_sector_size_in_kb
);
1198 setup_bank(bank
, num_pages
>> 1, flash_size_in_kb
>> 1,
1199 max_sector_size_in_kb
);
1201 /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
1202 if (device_id
== 0x451) {
1203 for (unsigned int i
= 0; i
< num_prot_blocks
; i
++) {
1204 bank
->prot_blocks
[i
].offset
= bank
->sectors
[i
<< 1].offset
;
1205 bank
->prot_blocks
[i
].size
= bank
->sectors
[i
<< 1].size
1206 + bank
->sectors
[(i
<< 1) + 1].size
;
1211 setup_bank(bank
, 0, flash_size_in_kb
, max_sector_size_in_kb
);
1213 /* F413/F423, sectors 14 and 15 share one common protection bit */
1214 if (device_id
== 0x463) {
1215 for (unsigned int i
= 0; i
< num_prot_blocks
; i
++) {
1216 bank
->prot_blocks
[i
].offset
= bank
->sectors
[i
].offset
;
1217 bank
->prot_blocks
[i
].size
= bank
->sectors
[i
].size
;
1219 bank
->prot_blocks
[num_prot_blocks
- 1].size
<<= 1;
1222 bank
->num_prot_blocks
= num_prot_blocks
;
1223 assert((bank
->size
>> 10) == flash_size_in_kb
);
1225 stm32x_info
->probed
= true;
1229 static int stm32x_auto_probe(struct flash_bank
*bank
)
1231 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1232 if (stm32x_info
->probed
)
1234 return stm32x_probe(bank
);
1237 static int get_stm32x_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
1239 uint32_t dbgmcu_idcode
;
1241 /* read stm32 device id register */
1242 int retval
= stm32x_get_device_id(bank
, &dbgmcu_idcode
);
1243 if (retval
!= ERROR_OK
)
1246 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
1247 uint16_t rev_id
= dbgmcu_idcode
>> 16;
1248 const char *device_str
;
1249 const char *rev_str
= NULL
;
1251 switch (device_id
) {
1253 device_str
= "STM32F2xx";
1293 device_str
= "STM32F4xx";
1319 device_str
= "STM32F446";
1333 device_str
= "STM32F4xx (Low Power)";
1355 device_str
= "STM32F7[4|5]x";
1369 device_str
= "STM32F7[6|7]x";
1382 device_str
= "STM32F7[2|3]x";
1392 device_str
= "STM32F4[1|2]3";
1402 command_print_sameline(cmd
, "Cannot identify target as a STM32F2/4/7\n");
1407 command_print_sameline(cmd
, "%s - Rev: %s", device_str
, rev_str
);
1409 command_print_sameline(cmd
, "%s - Rev: unknown (0x%04" PRIx16
")", device_str
, rev_id
);
1414 COMMAND_HANDLER(stm32x_handle_lock_command
)
1416 struct target
*target
= NULL
;
1417 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1420 return ERROR_COMMAND_SYNTAX_ERROR
;
1422 struct flash_bank
*bank
;
1423 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1424 if (retval
!= ERROR_OK
)
1427 stm32x_info
= bank
->driver_priv
;
1428 target
= bank
->target
;
1430 if (target
->state
!= TARGET_HALTED
) {
1431 LOG_INFO("Target not halted");
1432 /* return ERROR_TARGET_NOT_HALTED; */
1435 if (stm32x_read_options(bank
) != ERROR_OK
) {
1436 command_print(CMD
, "%s failed to read options", bank
->driver
->name
);
1440 /* set readout protection */
1441 stm32x_info
->option_bytes
.RDP
= 0;
1443 if (stm32x_write_options(bank
) != ERROR_OK
) {
1444 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
1448 command_print(CMD
, "%s locked", bank
->driver
->name
);
1453 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1455 struct target
*target
= NULL
;
1456 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1459 return ERROR_COMMAND_SYNTAX_ERROR
;
1461 struct flash_bank
*bank
;
1462 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1463 if (retval
!= ERROR_OK
)
1466 stm32x_info
= bank
->driver_priv
;
1467 target
= bank
->target
;
1469 if (target
->state
!= TARGET_HALTED
) {
1470 LOG_INFO("Target not halted");
1471 /* return ERROR_TARGET_NOT_HALTED; */
1474 if (stm32x_read_options(bank
) != ERROR_OK
) {
1475 command_print(CMD
, "%s failed to read options", bank
->driver
->name
);
1479 /* clear readout protection and complementary option bytes
1480 * this will also force a device unlock if set */
1481 stm32x_info
->option_bytes
.RDP
= 0xAA;
1482 if (stm32x_info
->has_optcr2_pcrop
) {
1483 stm32x_info
->option_bytes
.optcr2_pcrop
= OPTCR2_PCROP_RDP
| (~1U << bank
->num_sectors
);
1486 if (stm32x_write_options(bank
) != ERROR_OK
) {
1487 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
1491 command_print(CMD
, "%s unlocked.\n"
1492 "INFO: a reset or power cycle is required "
1493 "for the new settings to take effect.", bank
->driver
->name
);
1498 static int stm32x_mass_erase(struct flash_bank
*bank
)
1502 struct target
*target
= bank
->target
;
1503 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1505 if (target
->state
!= TARGET_HALTED
) {
1506 LOG_ERROR("Target not halted");
1507 return ERROR_TARGET_NOT_HALTED
;
1510 stm32x_info
= bank
->driver_priv
;
1512 retval
= stm32x_unlock_reg(target
);
1513 if (retval
!= ERROR_OK
)
1516 /* mass erase flash memory */
1517 if (stm32x_info
->has_large_mem
)
1518 flash_mer
= FLASH_MER
| FLASH_MER1
;
1520 flash_mer
= FLASH_MER
;
1522 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), flash_mer
);
1523 if (retval
!= ERROR_OK
)
1525 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1526 flash_mer
| FLASH_STRT
);
1527 if (retval
!= ERROR_OK
)
1530 retval
= stm32x_wait_status_busy(bank
, FLASH_MASS_ERASE_TIMEOUT
);
1531 if (retval
!= ERROR_OK
)
1534 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1535 if (retval
!= ERROR_OK
)
1541 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1544 command_print(CMD
, "stm32x mass_erase <bank>");
1545 return ERROR_COMMAND_SYNTAX_ERROR
;
1548 struct flash_bank
*bank
;
1549 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1550 if (retval
!= ERROR_OK
)
1553 retval
= stm32x_mass_erase(bank
);
1554 if (retval
== ERROR_OK
) {
1555 command_print(CMD
, "stm32x mass erase complete");
1557 command_print(CMD
, "stm32x mass erase failed");
1563 COMMAND_HANDLER(stm32f2x_handle_options_read_command
)
1566 struct flash_bank
*bank
;
1567 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1569 if (CMD_ARGC
!= 1) {
1570 command_print(CMD
, "stm32f2x options_read <bank>");
1571 return ERROR_COMMAND_SYNTAX_ERROR
;
1574 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1575 if (retval
!= ERROR_OK
)
1578 retval
= stm32x_read_options(bank
);
1579 if (retval
!= ERROR_OK
)
1582 stm32x_info
= bank
->driver_priv
;
1583 if (stm32x_info
->has_extra_options
) {
1584 if (stm32x_info
->has_boot_addr
) {
1585 uint32_t boot_addr
= stm32x_info
->option_bytes
.boot_addr
;
1587 command_print(CMD
, "stm32f2x user_options 0x%03" PRIX16
","
1588 " boot_add0 0x%04" PRIX32
", boot_add1 0x%04" PRIX32
,
1589 stm32x_info
->option_bytes
.user_options
,
1590 boot_addr
& 0xffff, (boot_addr
& 0xffff0000) >> 16);
1591 if (stm32x_info
->has_optcr2_pcrop
) {
1592 command_print(CMD
, "stm32f2x optcr2_pcrop 0x%08" PRIX32
,
1593 stm32x_info
->option_bytes
.optcr2_pcrop
);
1596 command_print(CMD
, "stm32f2x user_options 0x%03" PRIX16
,
1597 stm32x_info
->option_bytes
.user_options
);
1600 command_print(CMD
, "stm32f2x user_options 0x%02" PRIX16
,
1601 stm32x_info
->option_bytes
.user_options
);
1608 COMMAND_HANDLER(stm32f2x_handle_options_write_command
)
1611 struct flash_bank
*bank
;
1612 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1613 uint16_t user_options
, boot_addr0
, boot_addr1
, options_mask
;
1616 command_print(CMD
, "stm32f2x options_write <bank> ...");
1617 return ERROR_COMMAND_SYNTAX_ERROR
;
1620 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1621 if (retval
!= ERROR_OK
)
1624 retval
= stm32x_read_options(bank
);
1625 if (retval
!= ERROR_OK
)
1628 stm32x_info
= bank
->driver_priv
;
1629 if (stm32x_info
->has_boot_addr
) {
1630 if (CMD_ARGC
!= 4) {
1631 command_print(CMD
, "stm32f2x options_write <bank> <user_options>"
1632 " <boot_addr0> <boot_addr1>");
1633 return ERROR_COMMAND_SYNTAX_ERROR
;
1635 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[2], boot_addr0
);
1636 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[3], boot_addr1
);
1637 stm32x_info
->option_bytes
.boot_addr
= boot_addr0
| (((uint32_t) boot_addr1
) << 16);
1639 if (CMD_ARGC
!= 2) {
1640 command_print(CMD
, "stm32f2x options_write <bank> <user_options>");
1641 return ERROR_COMMAND_SYNTAX_ERROR
;
1645 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[1], user_options
);
1646 options_mask
= !stm32x_info
->has_extra_options
? ~0xfc :
1647 ~(((0xf00 << (stm32x_info
->protection_bits
- 12)) | 0xff) & 0xffc);
1648 if (user_options
& options_mask
) {
1649 command_print(CMD
, "stm32f2x invalid user_options");
1650 return ERROR_COMMAND_ARGUMENT_INVALID
;
1653 stm32x_info
->option_bytes
.user_options
= user_options
;
1655 if (stm32x_write_options(bank
) != ERROR_OK
) {
1656 command_print(CMD
, "stm32f2x failed to write options");
1660 /* switching between single- and dual-bank modes requires re-probe */
1661 /* ... and reprogramming of whole flash */
1662 stm32x_info
->probed
= false;
1664 command_print(CMD
, "stm32f2x write options complete.\n"
1665 "INFO: a reset or power cycle is required "
1666 "for the new settings to take effect.");
1670 COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command
)
1673 struct flash_bank
*bank
;
1674 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1675 uint32_t optcr2_pcrop
;
1677 if (CMD_ARGC
!= 2) {
1678 command_print(CMD
, "stm32f2x optcr2_write <bank> <optcr2_value>");
1679 return ERROR_COMMAND_SYNTAX_ERROR
;
1682 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1683 if (retval
!= ERROR_OK
)
1686 stm32x_info
= bank
->driver_priv
;
1687 if (!stm32x_info
->has_optcr2_pcrop
) {
1688 command_print(CMD
, "no optcr2 register");
1689 return ERROR_COMMAND_ARGUMENT_INVALID
;
1692 command_print(CMD
, "INFO: To disable PCROP, set PCROP_RDP"
1693 " with PCROPi bits STILL SET, then\nlock device and"
1694 " finally unlock it. Clears PCROP and mass erases flash.");
1696 retval
= stm32x_read_options(bank
);
1697 if (retval
!= ERROR_OK
)
1700 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], optcr2_pcrop
);
1701 stm32x_info
->option_bytes
.optcr2_pcrop
= optcr2_pcrop
;
1703 if (stm32x_write_options(bank
) != ERROR_OK
) {
1704 command_print(CMD
, "stm32f2x failed to write options");
1708 command_print(CMD
, "stm32f2x optcr2_write complete.");
1712 COMMAND_HANDLER(stm32x_handle_otp_command
)
1715 command_print(CMD
, "stm32x otp <bank> (enable|disable|show)");
1716 return ERROR_COMMAND_SYNTAX_ERROR
;
1719 struct flash_bank
*bank
;
1720 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1721 if (retval
!= ERROR_OK
)
1723 if (stm32x_is_otp(bank
)) {
1724 if (strcmp(CMD_ARGV
[1], "enable") == 0) {
1725 stm32x_otp_enable(bank
);
1726 } else if (strcmp(CMD_ARGV
[1], "disable") == 0) {
1727 stm32x_otp_disable(bank
);
1728 } else if (strcmp(CMD_ARGV
[1], "show") == 0) {
1730 "OTP memory bank #%u is %s for write commands.",
1732 stm32x_is_otp_unlocked(bank
) ? "enabled" : "disabled");
1734 return ERROR_COMMAND_SYNTAX_ERROR
;
1737 command_print(CMD
, "Failed: not an OTP bank.");
1743 static const struct command_registration stm32f2x_exec_command_handlers
[] = {
1746 .handler
= stm32x_handle_lock_command
,
1747 .mode
= COMMAND_EXEC
,
1749 .help
= "Lock entire flash device.",
1753 .handler
= stm32x_handle_unlock_command
,
1754 .mode
= COMMAND_EXEC
,
1756 .help
= "Unlock entire protected flash device.",
1759 .name
= "mass_erase",
1760 .handler
= stm32x_handle_mass_erase_command
,
1761 .mode
= COMMAND_EXEC
,
1763 .help
= "Erase entire flash device.",
1766 .name
= "options_read",
1767 .handler
= stm32f2x_handle_options_read_command
,
1768 .mode
= COMMAND_EXEC
,
1770 .help
= "Read and display device option bytes.",
1773 .name
= "options_write",
1774 .handler
= stm32f2x_handle_options_write_command
,
1775 .mode
= COMMAND_EXEC
,
1776 .usage
= "bank_id user_options [ boot_add0 boot_add1 ]",
1777 .help
= "Write option bytes",
1780 .name
= "optcr2_write",
1781 .handler
= stm32f2x_handle_optcr2_write_command
,
1782 .mode
= COMMAND_EXEC
,
1783 .usage
= "bank_id optcr2",
1784 .help
= "Write optcr2 word",
1788 .handler
= stm32x_handle_otp_command
,
1789 .mode
= COMMAND_EXEC
,
1791 .help
= "OTP (One Time Programmable) memory write enable/disable.",
1793 COMMAND_REGISTRATION_DONE
1796 static const struct command_registration stm32f2x_command_handlers
[] = {
1799 .mode
= COMMAND_ANY
,
1800 .help
= "stm32f2x flash command group",
1802 .chain
= stm32f2x_exec_command_handlers
,
1804 COMMAND_REGISTRATION_DONE
1807 const struct flash_driver stm32f2x_flash
= {
1809 .commands
= stm32f2x_command_handlers
,
1810 .flash_bank_command
= stm32x_flash_bank_command
,
1811 .erase
= stm32x_erase
,
1812 .protect
= stm32x_protect
,
1813 .write
= stm32x_write
,
1814 .read
= default_flash_read
,
1815 .probe
= stm32x_probe
,
1816 .auto_probe
= stm32x_auto_probe
,
1817 .erase_check
= default_flash_blank_check
,
1818 .protect_check
= stm32x_protect_check
,
1819 .info
= get_stm32x_info
,
1820 .free_driver_priv
= default_flash_free_driver_priv
,
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