1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
17 * GNU General public License for more details. *
19 * You should have received a copy of the GNU General public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ****************************************************************************/
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
57 /* END ATMEL COPYRIGHT */
66 #include <helper/time_support.h>
68 #define REG_NAME_WIDTH (12)
70 // at91sam3u series (has one or two flash banks)
71 #define FLASH_BANK0_BASE_U 0x00080000
72 #define FLASH_BANK1_BASE_U 0x00100000
74 // at91sam3s series (has always one flash bank)
75 #define FLASH_BANK_BASE_S 0x00400000
77 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
78 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
79 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
80 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
81 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
82 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
83 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
84 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
85 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
86 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
87 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
88 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
89 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
90 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
91 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
92 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
93 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
94 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
96 #define offset_EFC_FMR 0
97 #define offset_EFC_FCR 4
98 #define offset_EFC_FSR 8
99 #define offset_EFC_FRR 12
103 _tomhz(uint32_t freq_hz
)
107 f
= ((float)(freq_hz
)) / 1000000.0;
111 // How the chip is configured.
113 uint32_t unique_id
[4];
117 uint32_t mainosc_freq
;
127 #define SAM3_CHIPID_CIDR (0x400E0740)
128 uint32_t CHIPID_CIDR
;
129 #define SAM3_CHIPID_EXID (0x400E0744)
130 uint32_t CHIPID_EXID
;
132 #define SAM3_SUPC_CR (0x400E1210)
135 #define SAM3_PMC_BASE (0x400E0400)
136 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
138 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
140 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
142 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
144 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
146 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
148 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
150 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
152 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
154 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
156 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
158 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
160 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
162 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
167 struct sam3_bank_private
{
169 // DANGER: THERE ARE DRAGONS HERE..
170 // NOTE: If you add more 'ghost' pointers
171 // be aware that you must *manually* update
172 // these pointers in the function sam3_GetDetails()
173 // See the comment "Here there be dragons"
175 // so we can find the chip we belong to
176 struct sam3_chip
*pChip
;
177 // so we can find the orginal bank pointer
178 struct flash_bank
*pBank
;
179 unsigned bank_number
;
180 uint32_t controller_address
;
181 uint32_t base_address
;
185 unsigned sector_size
;
189 struct sam3_chip_details
{
190 // THERE ARE DRAGONS HERE..
191 // note: If you add pointers here
192 // becareful about them as they
193 // may need to be updated inside
194 // the function: "sam3_GetDetails()
195 // which copy/overwrites the
196 // 'runtime' copy of this structure
197 uint32_t chipid_cidr
;
201 #define SAM3_N_NVM_BITS 3
202 unsigned gpnvm
[SAM3_N_NVM_BITS
];
203 unsigned total_flash_size
;
204 unsigned total_sram_size
;
206 #define SAM3_MAX_FLASH_BANKS 2
207 // these are "initialized" from the global const data
208 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
213 struct sam3_chip
*next
;
216 // this is "initialized" from the global const structure
217 struct sam3_chip_details details
;
218 struct target
*target
;
223 struct sam3_reg_list
{
224 uint32_t address
; size_t struct_offset
; const char *name
;
225 void (*explain_func
)(struct sam3_chip
*pInfo
);
229 static struct sam3_chip
*all_sam3_chips
;
231 static struct sam3_chip
*
232 get_current_sam3(struct command_context
*cmd_ctx
)
235 static struct sam3_chip
*p
;
237 t
= get_current_target(cmd_ctx
);
239 command_print(cmd_ctx
, "No current target?");
245 // this should not happen
246 // the command is not registered until the chip is created?
247 command_print(cmd_ctx
, "No SAM3 chips exist?");
252 if (p
->target
== t
) {
257 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
262 // these are used to *initialize* the "pChip->details" structure.
263 static const struct sam3_chip_details all_sam3_details
[] = {
264 // Start at91sam3u* series
266 .chipid_cidr
= 0x28100960,
267 .name
= "at91sam3u4e",
268 .total_flash_size
= 256 * 1024,
269 .total_sram_size
= 52 * 1024,
273 // System boots at address 0x0
274 // gpnvm[1] = selects boot code
276 // boot is via "SAMBA" (rom)
279 // Selection is via gpnvm[2]
282 // NOTE: banks 0 & 1 switch places
284 // Bank0 is the boot rom
286 // Bank1 is the boot rom
295 .base_address
= FLASH_BANK0_BASE_U
,
296 .controller_address
= 0x400e0800,
298 .size_bytes
= 128 * 1024,
310 .base_address
= FLASH_BANK1_BASE_U
,
311 .controller_address
= 0x400e0a00,
313 .size_bytes
= 128 * 1024,
322 .chipid_cidr
= 0x281a0760,
323 .name
= "at91sam3u2e",
324 .total_flash_size
= 128 * 1024,
325 .total_sram_size
= 36 * 1024,
329 // System boots at address 0x0
330 // gpnvm[1] = selects boot code
332 // boot is via "SAMBA" (rom)
335 // Selection is via gpnvm[2]
344 .base_address
= FLASH_BANK0_BASE_U
,
345 .controller_address
= 0x400e0800,
347 .size_bytes
= 128 * 1024,
361 .chipid_cidr
= 0x28190560,
362 .name
= "at91sam3u1e",
363 .total_flash_size
= 64 * 1024,
364 .total_sram_size
= 20 * 1024,
368 // System boots at address 0x0
369 // gpnvm[1] = selects boot code
371 // boot is via "SAMBA" (rom)
374 // Selection is via gpnvm[2]
385 .base_address
= FLASH_BANK0_BASE_U
,
386 .controller_address
= 0x400e0800,
388 .size_bytes
= 64 * 1024,
404 .chipid_cidr
= 0x28000960,
405 .name
= "at91sam3u4c",
406 .total_flash_size
= 256 * 1024,
407 .total_sram_size
= 52 * 1024,
411 // System boots at address 0x0
412 // gpnvm[1] = selects boot code
414 // boot is via "SAMBA" (rom)
417 // Selection is via gpnvm[2]
420 // NOTE: banks 0 & 1 switch places
422 // Bank0 is the boot rom
424 // Bank1 is the boot rom
433 .base_address
= FLASH_BANK0_BASE_U
,
434 .controller_address
= 0x400e0800,
436 .size_bytes
= 128 * 1024,
447 .base_address
= FLASH_BANK1_BASE_U
,
448 .controller_address
= 0x400e0a00,
450 .size_bytes
= 128 * 1024,
459 .chipid_cidr
= 0x280a0760,
460 .name
= "at91sam3u2c",
461 .total_flash_size
= 128 * 1024,
462 .total_sram_size
= 36 * 1024,
466 // System boots at address 0x0
467 // gpnvm[1] = selects boot code
469 // boot is via "SAMBA" (rom)
472 // Selection is via gpnvm[2]
481 .base_address
= FLASH_BANK0_BASE_U
,
482 .controller_address
= 0x400e0800,
484 .size_bytes
= 128 * 1024,
498 .chipid_cidr
= 0x28090560,
499 .name
= "at91sam3u1c",
500 .total_flash_size
= 64 * 1024,
501 .total_sram_size
= 20 * 1024,
505 // System boots at address 0x0
506 // gpnvm[1] = selects boot code
508 // boot is via "SAMBA" (rom)
511 // Selection is via gpnvm[2]
522 .base_address
= FLASH_BANK0_BASE_U
,
523 .controller_address
= 0x400e0800,
525 .size_bytes
= 64 * 1024,
540 // Start at91sam3s* series
542 // Note: The preliminary at91sam3s datasheet says on page 302
543 // that the flash controller is at address 0x400E0800.
544 // This is _not_ the case, the controller resides at address 0x400e0a0.
546 .chipid_cidr
= 0x28A00960,
547 .name
= "at91sam3s4c",
548 .total_flash_size
= 256 * 1024,
549 .total_sram_size
= 48 * 1024,
559 .base_address
= FLASH_BANK_BASE_S
,
561 .controller_address
= 0x400e0a00,
563 .size_bytes
= 256 * 1024,
579 .chipid_cidr
= 0x28900960,
580 .name
= "at91sam3s4b",
581 .total_flash_size
= 256 * 1024,
582 .total_sram_size
= 48 * 1024,
592 .base_address
= FLASH_BANK_BASE_S
,
594 .controller_address
= 0x400e0a00,
596 .size_bytes
= 256 * 1024,
611 .chipid_cidr
= 0x28800960,
612 .name
= "at91sam3s4a",
613 .total_flash_size
= 256 * 1024,
614 .total_sram_size
= 48 * 1024,
624 .base_address
= FLASH_BANK_BASE_S
,
626 .controller_address
= 0x400e0a00,
628 .size_bytes
= 256 * 1024,
643 .chipid_cidr
= 0x28AA0760,
644 .name
= "at91sam3s2c",
645 .total_flash_size
= 128 * 1024,
646 .total_sram_size
= 32 * 1024,
656 .base_address
= FLASH_BANK_BASE_S
,
658 .controller_address
= 0x400e0a00,
660 .size_bytes
= 128 * 1024,
675 .chipid_cidr
= 0x289A0760,
676 .name
= "at91sam3s2b",
677 .total_flash_size
= 128 * 1024,
678 .total_sram_size
= 32 * 1024,
688 .base_address
= FLASH_BANK_BASE_S
,
690 .controller_address
= 0x400e0a00,
692 .size_bytes
= 128 * 1024,
707 .chipid_cidr
= 0x288A0760,
708 .name
= "at91sam3s2a",
709 .total_flash_size
= 128 * 1024,
710 .total_sram_size
= 32 * 1024,
720 .base_address
= FLASH_BANK_BASE_S
,
722 .controller_address
= 0x400e0a00,
724 .size_bytes
= 128 * 1024,
739 .chipid_cidr
= 0x28A90560,
740 .name
= "at91sam3s1c",
741 .total_flash_size
= 64 * 1024,
742 .total_sram_size
= 16 * 1024,
752 .base_address
= FLASH_BANK_BASE_S
,
754 .controller_address
= 0x400e0a00,
756 .size_bytes
= 64 * 1024,
771 .chipid_cidr
= 0x28990560,
772 .name
= "at91sam3s1b",
773 .total_flash_size
= 64 * 1024,
774 .total_sram_size
= 16 * 1024,
784 .base_address
= FLASH_BANK_BASE_S
,
786 .controller_address
= 0x400e0a00,
788 .size_bytes
= 64 * 1024,
803 .chipid_cidr
= 0x28890560,
804 .name
= "at91sam3s1a",
805 .total_flash_size
= 64 * 1024,
806 .total_sram_size
= 16 * 1024,
816 .base_address
= FLASH_BANK_BASE_S
,
818 .controller_address
= 0x400e0a00,
820 .size_bytes
= 64 * 1024,
842 /***********************************************************************
843 **********************************************************************
844 **********************************************************************
845 **********************************************************************
846 **********************************************************************
847 **********************************************************************/
848 /* *ATMEL* style code - from the SAM3 driver code */
851 * Get the current status of the EEFC and
852 * the value of some status bits (LOCKE, PROGE).
853 * @param pPrivate - info about the bank
854 * @param v - result goes here
857 EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
860 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FSR
, v
);
861 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
863 ((unsigned int)((*v
>> 2) & 1)),
864 ((unsigned int)((*v
>> 1) & 1)),
865 ((unsigned int)((*v
>> 0) & 1)));
871 * Get the result of the last executed command.
872 * @param pPrivate - info about the bank
873 * @param v - result goes here
876 EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
880 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FRR
, &rv
);
884 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
889 EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
890 unsigned command
, unsigned argument
)
899 // Check command & argument
902 case AT91C_EFC_FCMD_WP
:
903 case AT91C_EFC_FCMD_WPL
:
904 case AT91C_EFC_FCMD_EWP
:
905 case AT91C_EFC_FCMD_EWPL
:
906 // case AT91C_EFC_FCMD_EPL:
907 // case AT91C_EFC_FCMD_EPA:
908 case AT91C_EFC_FCMD_SLB
:
909 case AT91C_EFC_FCMD_CLB
:
910 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
912 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
916 case AT91C_EFC_FCMD_SFB
:
917 case AT91C_EFC_FCMD_CFB
:
918 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
919 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
920 pPrivate
->pChip
->details
.n_gpnvms
);
924 case AT91C_EFC_FCMD_GETD
:
925 case AT91C_EFC_FCMD_EA
:
926 case AT91C_EFC_FCMD_GLB
:
927 case AT91C_EFC_FCMD_GFB
:
928 case AT91C_EFC_FCMD_STUI
:
929 case AT91C_EFC_FCMD_SPUI
:
931 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
935 LOG_ERROR("Unknown command %d", command
);
939 if (command
== AT91C_EFC_FCMD_SPUI
) {
940 // this is a very special situation.
941 // Situation (1) - error/retry - see below
942 // And we are being called recursively
943 // Situation (2) - normal, finished reading unique id
945 // it should be "ready"
946 EFC_GetStatus(pPrivate
, &v
);
952 // we have done this before
953 // the controller is not responding.
954 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate
->bank_number
);
958 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
959 pPrivate
->bank_number
);
960 // we do that by issuing the *STOP* command
961 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
962 // above is recursive, and further recursion is blocked by
963 // if (command == AT91C_EFC_FCMD_SPUI) above
969 v
= (0x5A << 24) | (argument
<< 8) | command
;
970 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
971 r
= target_write_u32(pPrivate
->pBank
->target
,
972 pPrivate
->controller_address
+ offset_EFC_FCR
,
975 LOG_DEBUG("Error Write failed");
981 * Performs the given command and wait until its completion (or an error).
982 * @param pPrivate - info about the bank
983 * @param command - Command to perform.
984 * @param argument - Optional command argument.
985 * @param status - put command status bits here
988 EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
996 long long ms_now
, ms_end
;
1003 r
= EFC_StartCommand(pPrivate
, command
, argument
);
1004 if (r
!= ERROR_OK
) {
1008 ms_end
= 500 + timeval_ms();
1012 r
= EFC_GetStatus(pPrivate
, &v
);
1013 if (r
!= ERROR_OK
) {
1016 ms_now
= timeval_ms();
1017 if (ms_now
> ms_end
) {
1019 LOG_ERROR("Command timeout");
1023 while ((v
& 1) == 0)
1028 *status
= (v
& 0x6);
1039 * Read the unique ID.
1040 * @param pPrivate - info about the bank
1041 * The unique ID is stored in the 'pPrivate' structure.
1044 FLASHD_ReadUniqueID (struct sam3_bank_private
*pPrivate
)
1050 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
1051 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
1052 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
1053 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
1056 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
1061 for (x
= 0 ; x
< 4 ; x
++) {
1062 r
= target_read_u32(pPrivate
->pChip
->target
,
1063 pPrivate
->pBank
->base
+ (x
* 4),
1068 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
1071 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
1072 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1074 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
1075 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
1076 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
1077 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
1083 * Erases the entire flash.
1084 * @param pPrivate - the info about the bank.
1087 FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
1090 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
1096 * Gets current GPNVM state.
1097 * @param pPrivate - info about the bank.
1098 * @param gpnvm - GPNVM bit index.
1099 * @param puthere - result stored here.
1101 //------------------------------------------------------------------------------
1103 FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
1109 if (pPrivate
->bank_number
!= 0) {
1110 LOG_ERROR("GPNVM only works with Bank0");
1114 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1115 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1116 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1120 // Get GPNVMs status
1121 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1122 if (r
!= ERROR_OK
) {
1123 LOG_ERROR("Failed");
1127 r
= EFC_GetResult(pPrivate
, &v
);
1130 // Check if GPNVM is set
1131 // get the bit and make it a 0/1
1132 *puthere
= (v
>> gpnvm
) & 1;
1142 * Clears the selected GPNVM bit.
1143 * @param pPrivate info about the bank
1144 * @param gpnvm GPNVM index.
1145 * @returns 0 if successful; otherwise returns an error code.
1148 FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1154 if (pPrivate
->bank_number
!= 0) {
1155 LOG_ERROR("GPNVM only works with Bank0");
1159 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1160 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1161 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1165 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1166 if (r
!= ERROR_OK
) {
1167 LOG_DEBUG("Failed: %d",r
);
1170 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
1171 LOG_DEBUG("End: %d",r
);
1178 * Sets the selected GPNVM bit.
1179 * @param pPrivate info about the bank
1180 * @param gpnvm GPNVM index.
1183 FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1188 if (pPrivate
->bank_number
!= 0) {
1189 LOG_ERROR("GPNVM only works with Bank0");
1193 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1194 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1195 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1199 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1200 if (r
!= ERROR_OK
) {
1208 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
1215 * Returns a bit field (at most 64) of locked regions within a page.
1216 * @param pPrivate info about the bank
1217 * @param v where to store locked bits
1220 FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1224 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
1225 if (r
== ERROR_OK
) {
1226 r
= EFC_GetResult(pPrivate
, v
);
1228 LOG_DEBUG("End: %d",r
);
1234 * Unlocks all the regions in the given address range.
1235 * @param pPrivate info about the bank
1236 * @param start_sector first sector to unlock
1237 * @param end_sector last (inclusive) to unlock
1241 FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
1242 unsigned start_sector
,
1243 unsigned end_sector
)
1248 uint32_t pages_per_sector
;
1250 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1252 /* Unlock all pages */
1253 while (start_sector
<= end_sector
) {
1254 pg
= start_sector
* pages_per_sector
;
1256 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
1257 if (r
!= ERROR_OK
) {
1269 * @param pPrivate - info about the bank
1270 * @param start_sector - first sector to lock
1271 * @param end_sector - last sector (inclusive) to lock
1274 FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
1275 unsigned start_sector
,
1276 unsigned end_sector
)
1280 uint32_t pages_per_sector
;
1283 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1285 /* Lock all pages */
1286 while (start_sector
<= end_sector
) {
1287 pg
= start_sector
* pages_per_sector
;
1289 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1290 if (r
!= ERROR_OK
) {
1299 /****** END SAM3 CODE ********/
1301 /* begin helpful debug code */
1302 // print the fieldname, the field value, in dec & hex, and return field value
1304 sam3_reg_fieldname(struct sam3_chip
*pChip
,
1305 const char *regname
,
1314 // extract the field
1316 v
= v
& ((1 << width
)-1);
1326 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1327 REG_NAME_WIDTH
, regname
,
1334 static const char _unknown
[] = "unknown";
1335 static const char * const eproc_names
[] = {
1354 #define nvpsize2 nvpsize // these two tables are identical
1355 static const char * const nvpsize
[] = {
1368 "1024K bytes", // 12
1370 "2048K bytes", // 14
1375 static const char * const sramsize
[] = {
1395 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1396 { 0x19, "AT91SAM9xx Series" },
1397 { 0x29, "AT91SAM9XExx Series" },
1398 { 0x34, "AT91x34 Series" },
1399 { 0x37, "CAP7 Series" },
1400 { 0x39, "CAP9 Series" },
1401 { 0x3B, "CAP11 Series" },
1402 { 0x40, "AT91x40 Series" },
1403 { 0x42, "AT91x42 Series" },
1404 { 0x55, "AT91x55 Series" },
1405 { 0x60, "AT91SAM7Axx Series" },
1406 { 0x61, "AT91SAM7AQxx Series" },
1407 { 0x63, "AT91x63 Series" },
1408 { 0x70, "AT91SAM7Sxx Series" },
1409 { 0x71, "AT91SAM7XCxx Series" },
1410 { 0x72, "AT91SAM7SExx Series" },
1411 { 0x73, "AT91SAM7Lxx Series" },
1412 { 0x75, "AT91SAM7Xxx Series" },
1413 { 0x76, "AT91SAM7SLxx Series" },
1414 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1415 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1416 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1417 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1418 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1419 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1420 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1421 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1422 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1423 { 0x92, "AT91x92 Series" },
1424 { 0xF0, "AT75Cxx Series" },
1429 static const char * const nvptype
[] = {
1431 "romless or onchip flash", // 1
1432 "embedded flash memory", // 2
1433 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1434 "sram emulating flash", // 4
1441 static const char *_yes_or_no(uint32_t v
)
1450 static const char * const _rc_freq
[] = {
1451 "4 MHz", "8 MHz", "12 MHz", "reserved"
1455 sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
1460 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
1461 LOG_USER_N("(main xtal enabled: %s)\n",
1463 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
1464 LOG_USER_N("(main osc bypass: %s)\n",
1466 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 2, 1);
1467 LOG_USER_N("(onchip RC-OSC enabled: %s)\n",
1469 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
1470 LOG_USER_N("(onchip RC-OSC freq: %s)\n",
1473 pChip
->cfg
.rc_freq
= 0;
1477 pChip
->cfg
.rc_freq
= 0;
1479 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
1482 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
1485 pChip
->cfg
.rc_freq
= 12* 1000 * 1000;
1490 v
= sam3_reg_fieldname(pChip
,"MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
1491 LOG_USER_N("(startup clks, time= %f uSecs)\n",
1492 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
1493 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
1494 LOG_USER_N("(mainosc source: %s)\n",
1495 v
? "external xtal" : "internal RC");
1497 v
= sam3_reg_fieldname(pChip
,"CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
1498 LOG_USER_N("(clock failure enabled: %s)\n",
1505 sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
1511 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
1514 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
1515 LOG_USER_N("%s\n", eproc_names
[v
]);
1517 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
1518 LOG_USER_N("%s\n", nvpsize
[v
]);
1520 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
1521 LOG_USER_N("%s\n", nvpsize2
[v
]);
1523 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16,4);
1524 LOG_USER_N("%s\n", sramsize
[ v
]);
1526 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
1528 for (x
= 0 ; archnames
[x
].name
; x
++) {
1529 if (v
== archnames
[x
].value
) {
1530 cp
= archnames
[x
].name
;
1535 LOG_USER_N("%s\n", cp
);
1537 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
1538 LOG_USER_N("%s\n", nvptype
[ v
]);
1540 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
1541 LOG_USER_N("(exists: %s)\n", _yes_or_no(v
));
1545 sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
1550 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
1551 LOG_USER_N("(main ready: %s)\n", _yes_or_no(v
));
1553 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
1555 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
1556 pChip
->cfg
.mainosc_freq
= v
;
1558 LOG_USER_N("(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1560 pChip
->cfg
.slow_freq
/ 1000,
1561 pChip
->cfg
.slow_freq
% 1000);
1566 sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
1570 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
1572 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
1574 pChip
->cfg
.plla_freq
= 0;
1576 LOG_USER_N("\tPLLA Freq: (Disabled,mula = 0)\n");
1577 } else if (diva
== 0) {
1578 LOG_USER_N("\tPLLA Freq: (Disabled,diva = 0)\n");
1579 } else if (diva
== 1) {
1580 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1));
1581 LOG_USER_N("\tPLLA Freq: %3.03f MHz\n",
1582 _tomhz(pChip
->cfg
.plla_freq
));
1588 sam3_explain_mckr(struct sam3_chip
*pChip
)
1590 uint32_t css
, pres
, fin
= 0;
1592 const char *cp
= NULL
;
1594 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
1597 fin
= pChip
->cfg
.slow_freq
;
1601 fin
= pChip
->cfg
.mainosc_freq
;
1605 fin
= pChip
->cfg
.plla_freq
;
1609 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
1610 fin
= 480 * 1000 * 1000;
1614 cp
= "upll (*ERROR* UPLL is disabled)";
1622 LOG_USER_N("%s (%3.03f Mhz)\n",
1625 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
1626 switch (pres
& 0x07) {
1629 cp
= "selected clock";
1662 LOG_USER_N("(%s)\n", cp
);
1664 // sam3 has a *SINGLE* clock -
1665 // other at91 series parts have divisors for these.
1666 pChip
->cfg
.cpu_freq
= fin
;
1667 pChip
->cfg
.mclk_freq
= fin
;
1668 pChip
->cfg
.fclk_freq
= fin
;
1669 LOG_USER_N("\t\tResult CPU Freq: %3.03f\n",
1674 static struct sam3_chip
*
1675 target2sam3(struct target
*pTarget
)
1677 struct sam3_chip
*pChip
;
1679 if (pTarget
== NULL
) {
1683 pChip
= all_sam3_chips
;
1685 if (pChip
->target
== pTarget
) {
1686 break; // return below
1688 pChip
= pChip
->next
;
1696 sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
1698 // this function exists to help
1699 // keep funky offsetof() errors
1700 // and casting from causing bugs
1702 // By using prototypes - we can detect what would
1703 // be casting errors.
1705 return ((uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
));
1709 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1710 static const struct sam3_reg_list sam3_all_regs
[] = {
1711 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
1712 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
1713 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
1714 SAM3_ENTRY(CKGR_UCKR
, NULL
),
1715 SAM3_ENTRY(PMC_FSMR
, NULL
),
1716 SAM3_ENTRY(PMC_FSPR
, NULL
),
1717 SAM3_ENTRY(PMC_IMR
, NULL
),
1718 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
1719 SAM3_ENTRY(PMC_PCK0
, NULL
),
1720 SAM3_ENTRY(PMC_PCK1
, NULL
),
1721 SAM3_ENTRY(PMC_PCK2
, NULL
),
1722 SAM3_ENTRY(PMC_PCSR
, NULL
),
1723 SAM3_ENTRY(PMC_SCSR
, NULL
),
1724 SAM3_ENTRY(PMC_SR
, NULL
),
1725 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
1726 SAM3_ENTRY(CHIPID_EXID
, NULL
),
1727 SAM3_ENTRY(SUPC_CR
, NULL
),
1729 // TERMINATE THE LIST
1737 static struct sam3_bank_private
*
1738 get_sam3_bank_private(struct flash_bank
*bank
)
1740 return (struct sam3_bank_private
*)(bank
->driver_priv
);
1744 * Given a pointer to where it goes in the structure,
1745 * determine the register name, address from the all registers table.
1747 static const struct sam3_reg_list
*
1748 sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
1750 const struct sam3_reg_list
*pReg
;
1752 pReg
= &(sam3_all_regs
[0]);
1753 while (pReg
->name
) {
1754 uint32_t *pPossible
;
1756 // calculate where this one go..
1757 // it is "possibly" this register.
1759 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
1761 // well? Is it this register
1762 if (pPossible
== goes_here
) {
1770 // This is *TOTAL*PANIC* - we are totally screwed.
1771 LOG_ERROR("INVALID SAM3 REGISTER");
1777 sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
1779 const struct sam3_reg_list
*pReg
;
1782 pReg
= sam3_GetReg(pChip
, goes_here
);
1787 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
1788 if (r
!= ERROR_OK
) {
1789 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1790 pReg
->name
, (unsigned)(pReg
->address
), r
);
1798 sam3_ReadAllRegs(struct sam3_chip
*pChip
)
1801 const struct sam3_reg_list
*pReg
;
1803 pReg
= &(sam3_all_regs
[0]);
1804 while (pReg
->name
) {
1805 r
= sam3_ReadThisReg(pChip
,
1806 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
1807 if (r
!= ERROR_OK
) {
1808 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1809 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
1821 sam3_GetInfo(struct sam3_chip
*pChip
)
1823 const struct sam3_reg_list
*pReg
;
1826 pReg
= &(sam3_all_regs
[0]);
1827 while (pReg
->name
) {
1829 LOG_DEBUG("Start: %s", pReg
->name
);
1830 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
1831 LOG_USER_N("%*s: [0x%08x] -> 0x%08x\n",
1836 if (pReg
->explain_func
) {
1837 (*(pReg
->explain_func
))(pChip
);
1839 LOG_DEBUG("End: %s", pReg
->name
);
1842 LOG_USER_N(" rc-osc: %3.03f MHz\n", _tomhz(pChip
->cfg
.rc_freq
));
1843 LOG_USER_N(" mainosc: %3.03f MHz\n", _tomhz(pChip
->cfg
.mainosc_freq
));
1844 LOG_USER_N(" plla: %3.03f MHz\n", _tomhz(pChip
->cfg
.plla_freq
));
1845 LOG_USER_N(" cpu-freq: %3.03f MHz\n", _tomhz(pChip
->cfg
.cpu_freq
));
1846 LOG_USER_N("mclk-freq: %3.03f MHz\n", _tomhz(pChip
->cfg
.mclk_freq
));
1849 LOG_USER_N(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1850 pChip
->cfg
.unique_id
[0],
1851 pChip
->cfg
.unique_id
[1],
1852 pChip
->cfg
.unique_id
[2],
1853 pChip
->cfg
.unique_id
[3]);
1861 sam3_erase_check(struct flash_bank
*bank
)
1866 if (bank
->target
->state
!= TARGET_HALTED
) {
1867 LOG_ERROR("Target not halted");
1868 return ERROR_TARGET_NOT_HALTED
;
1870 if (0 == bank
->num_sectors
) {
1871 LOG_ERROR("Target: not supported/not probed\n");
1875 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1876 for (x
= 0 ; x
< bank
->num_sectors
; x
++) {
1877 bank
->sectors
[x
].is_erased
= 1;
1885 sam3_protect_check(struct flash_bank
*bank
)
1890 struct sam3_bank_private
*pPrivate
;
1893 if (bank
->target
->state
!= TARGET_HALTED
) {
1894 LOG_ERROR("Target not halted");
1895 return ERROR_TARGET_NOT_HALTED
;
1898 pPrivate
= get_sam3_bank_private(bank
);
1900 LOG_ERROR("no private for this bank?");
1903 if (!(pPrivate
->probed
)) {
1904 return ERROR_FLASH_BANK_NOT_PROBED
;
1907 r
= FLASHD_GetLockBits(pPrivate
, &v
);
1908 if (r
!= ERROR_OK
) {
1909 LOG_DEBUG("Failed: %d",r
);
1913 for (x
= 0 ; x
< pPrivate
->nsectors
; x
++) {
1914 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
1920 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
1922 struct sam3_chip
*pChip
;
1924 pChip
= all_sam3_chips
;
1926 // is this an existing chip?
1928 if (pChip
->target
== bank
->target
) {
1931 pChip
= pChip
->next
;
1935 // this is a *NEW* chip
1936 pChip
= calloc(1, sizeof(struct sam3_chip
));
1938 LOG_ERROR("NO RAM!");
1941 pChip
->target
= bank
->target
;
1943 pChip
->next
= all_sam3_chips
;
1944 all_sam3_chips
= pChip
;
1945 pChip
->target
= bank
->target
;
1946 // assumption is this runs at 32khz
1947 pChip
->cfg
.slow_freq
= 32768;
1951 switch (bank
->base
) {
1953 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
1954 [at91sam3u series] or 0x%08x [at91sam3s series])",
1955 ((unsigned int)(bank
->base
)),
1956 ((unsigned int)(FLASH_BANK0_BASE_U
)),
1957 ((unsigned int)(FLASH_BANK1_BASE_U
)),
1958 ((unsigned int)(FLASH_BANK_BASE_S
)));
1963 case FLASH_BANK0_BASE_U
:
1964 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
1965 bank
->bank_number
= 0;
1966 pChip
->details
.bank
[0].pChip
= pChip
;
1967 pChip
->details
.bank
[0].pBank
= bank
;
1969 case FLASH_BANK1_BASE_U
:
1970 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
1971 bank
->bank_number
= 1;
1972 pChip
->details
.bank
[1].pChip
= pChip
;
1973 pChip
->details
.bank
[1].pBank
= bank
;
1976 case FLASH_BANK_BASE_S
:
1977 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
1978 bank
->bank_number
= 0;
1979 pChip
->details
.bank
[0].pChip
= pChip
;
1980 pChip
->details
.bank
[0].pBank
= bank
;
1984 // we initialize after probing.
1989 sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
1991 const struct sam3_chip_details
*pDetails
;
1992 struct sam3_chip
*pChip
;
1993 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
1997 pDetails
= all_sam3_details
;
1998 while (pDetails
->name
) {
1999 if (pDetails
->chipid_cidr
== pPrivate
->pChip
->cfg
.CHIPID_CIDR
) {
2005 if (pDetails
->name
== NULL
) {
2006 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
2007 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
2008 // Help the victim, print details about the chip
2009 LOG_INFO_N("SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
2010 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
2011 sam3_explain_chipid_cidr(pPrivate
->pChip
);
2015 // DANGER: THERE ARE DRAGONS HERE
2017 // get our pChip - it is going
2018 // to be over-written shortly
2019 pChip
= pPrivate
->pChip
;
2021 // Note that, in reality:
2023 // pPrivate = &(pChip->details.bank[0])
2024 // or pPrivate = &(pChip->details.bank[1])
2027 // save the "bank" pointers
2028 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2029 saved_banks
[ x
] = pChip
->details
.bank
[x
].pBank
;
2032 // Overwrite the "details" structure.
2033 memcpy(&(pPrivate
->pChip
->details
),
2035 sizeof(pPrivate
->pChip
->details
));
2037 // now fix the ghosted pointers
2038 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2039 pChip
->details
.bank
[x
].pChip
= pChip
;
2040 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
2043 // update the *BANK*SIZE*
2052 _sam3_probe(struct flash_bank
*bank
, int noise
)
2056 struct sam3_bank_private
*pPrivate
;
2059 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
2060 if (bank
->target
->state
!= TARGET_HALTED
)
2062 LOG_ERROR("Target not halted");
2063 return ERROR_TARGET_NOT_HALTED
;
2066 pPrivate
= get_sam3_bank_private(bank
);
2068 LOG_ERROR("Invalid/unknown bank number\n");
2072 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
2073 if (r
!= ERROR_OK
) {
2079 if (pPrivate
->pChip
->probed
) {
2080 r
= sam3_GetInfo(pPrivate
->pChip
);
2082 r
= sam3_GetDetails(pPrivate
);
2084 if (r
!= ERROR_OK
) {
2088 // update the flash bank size
2089 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2090 if (bank
->base
== pPrivate
->pChip
->details
.bank
[0].base_address
) {
2091 bank
->size
= pPrivate
->pChip
->details
.bank
[0].size_bytes
;
2096 if (bank
->sectors
== NULL
) {
2097 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
2098 if (bank
->sectors
== NULL
) {
2099 LOG_ERROR("No memory!");
2102 bank
->num_sectors
= pPrivate
->nsectors
;
2104 for (x
= 0 ; ((int)(x
)) < bank
->num_sectors
; x
++) {
2105 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
2106 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
2108 bank
->sectors
[x
].is_erased
= -1;
2109 bank
->sectors
[x
].is_protected
= -1;
2113 pPrivate
->probed
= 1;
2115 r
= sam3_protect_check(bank
);
2116 if (r
!= ERROR_OK
) {
2120 LOG_DEBUG("Bank = %d, nbanks = %d",
2121 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
2122 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
2124 // it appears to be associated with the *last* flash bank.
2125 FLASHD_ReadUniqueID(pPrivate
);
2132 sam3_probe(struct flash_bank
*bank
)
2134 return _sam3_probe(bank
, 1);
2138 sam3_auto_probe(struct flash_bank
*bank
)
2140 return _sam3_probe(bank
, 0);
2146 sam3_erase(struct flash_bank
*bank
, int first
, int last
)
2148 struct sam3_bank_private
*pPrivate
;
2152 if (bank
->target
->state
!= TARGET_HALTED
) {
2153 LOG_ERROR("Target not halted");
2154 return ERROR_TARGET_NOT_HALTED
;
2157 r
= sam3_auto_probe(bank
);
2158 if (r
!= ERROR_OK
) {
2159 LOG_DEBUG("Here,r=%d",r
);
2163 pPrivate
= get_sam3_bank_private(bank
);
2164 if (!(pPrivate
->probed
)) {
2165 return ERROR_FLASH_BANK_NOT_PROBED
;
2168 if ((first
== 0) && ((last
+ 1)== ((int)(pPrivate
->nsectors
)))) {
2171 return FLASHD_EraseEntireBank(pPrivate
);
2173 LOG_INFO("sam3 auto-erases while programing (request ignored)");
2178 sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
2180 struct sam3_bank_private
*pPrivate
;
2184 if (bank
->target
->state
!= TARGET_HALTED
) {
2185 LOG_ERROR("Target not halted");
2186 return ERROR_TARGET_NOT_HALTED
;
2189 pPrivate
= get_sam3_bank_private(bank
);
2190 if (!(pPrivate
->probed
)) {
2191 return ERROR_FLASH_BANK_NOT_PROBED
;
2195 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2197 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2199 LOG_DEBUG("End: r=%d",r
);
2207 sam3_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2209 if (bank
->target
->state
!= TARGET_HALTED
) {
2210 LOG_ERROR("Target not halted");
2211 return ERROR_TARGET_NOT_HALTED
;
2218 sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2223 adr
= pagenum
* pPrivate
->page_size
;
2224 adr
+= adr
+ pPrivate
->base_address
;
2226 r
= target_read_memory(pPrivate
->pChip
->target
,
2228 4, /* THIS*MUST*BE* in 32bit values */
2229 pPrivate
->page_size
/ 4,
2231 if (r
!= ERROR_OK
) {
2232 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr
));
2237 // The code below is basically this:
2239 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
2241 // Only the *CPU* can write to the flash buffer.
2242 // the DAP cannot... so - we download this 28byte thing
2243 // Run the algorithm - (below)
2244 // to program the device
2246 // ========================================
2247 // #include <stdint.h>
2251 // const uint32_t *src;
2253 // volatile uint32_t *base;
2258 // uint32_t sam3_function(struct foo *p)
2260 // volatile uint32_t *v;
2262 // const uint32_t *s;
2284 // ========================================
2288 static const uint8_t
2289 sam3_page_write_opcodes
[] = {
2290 // 24 0000 0446 mov r4, r0
2292 // 25 0002 6168 ldr r1, [r4, #4]
2294 // 26 0004 0068 ldr r0, [r0, #0]
2296 // 27 0006 A268 ldr r2, [r4, #8]
2298 // 28 @ lr needed for prologue
2300 // 30 0008 51F8043B ldr r3, [r1], #4
2301 0x51,0xf8,0x04,0x3b,
2302 // 31 000c 12F1FF32 adds r2, r2, #-1
2303 0x12,0xf1,0xff,0x32,
2304 // 32 0010 40F8043B str r3, [r0], #4
2305 0x40,0xf8,0x04,0x3b,
2306 // 33 0014 F8D1 bne .L2
2308 // 34 0016 E268 ldr r2, [r4, #12]
2310 // 35 0018 2369 ldr r3, [r4, #16]
2312 // 36 001a 5360 str r3, [r2, #4]
2314 // 37 001c 0832 adds r2, r2, #8
2317 // 39 001e 1068 ldr r0, [r2, #0]
2319 // 40 0020 10F0010F tst r0, #1
2320 0x10,0xf0,0x01,0x0f,
2321 // 41 0024 FBD0 beq .L4
2323 0x00,0xBE /* bkpt #0 */
2328 sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2334 adr
= pagenum
* pPrivate
->page_size
;
2335 adr
+= (adr
+ pPrivate
->base_address
);
2337 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
2338 r
= target_write_memory(pPrivate
->pChip
->target
,
2340 4, /* THIS*MUST*BE* in 32bit values */
2341 pPrivate
->page_size
/ 4,
2343 if (r
!= ERROR_OK
) {
2344 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr
));
2348 r
= EFC_PerformCommand(pPrivate
,
2349 // send Erase & Write Page
2354 if (r
!= ERROR_OK
) {
2355 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr
));
2357 if (status
& (1 << 2)) {
2358 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
2361 if (status
& (1 << 1)) {
2362 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
2373 sam3_write(struct flash_bank
*bank
,
2382 unsigned page_offset
;
2383 struct sam3_bank_private
*pPrivate
;
2384 uint8_t *pagebuffer
;
2386 // incase we bail further below, set this to null
2389 // ignore dumb requests
2395 if (bank
->target
->state
!= TARGET_HALTED
) {
2396 LOG_ERROR("Target not halted");
2397 r
= ERROR_TARGET_NOT_HALTED
;
2401 pPrivate
= get_sam3_bank_private(bank
);
2402 if (!(pPrivate
->probed
)) {
2403 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2408 if ((offset
+ count
) > pPrivate
->size_bytes
) {
2409 LOG_ERROR("Flash write error - past end of bank");
2410 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2411 (unsigned int)(offset
),
2412 (unsigned int)(count
),
2413 (unsigned int)(pPrivate
->size_bytes
));
2418 pagebuffer
= malloc(pPrivate
->page_size
);
2420 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
2425 // what page do we start & end in?
2426 page_cur
= offset
/ pPrivate
->page_size
;
2427 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2429 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2430 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2432 // Special case: all one page
2435 // (1) non-aligned start
2437 // (3) non-aligned end.
2439 // Handle special case - all one page.
2440 if (page_cur
== page_end
) {
2441 LOG_DEBUG("Special case, all in one page");
2442 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2443 if (r
!= ERROR_OK
) {
2447 page_offset
= (offset
& (pPrivate
->page_size
-1));
2448 memcpy(pagebuffer
+ page_offset
,
2452 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2453 if (r
!= ERROR_OK
) {
2460 // non-aligned start
2461 page_offset
= offset
& (pPrivate
->page_size
- 1);
2463 LOG_DEBUG("Not-Aligned start");
2465 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2466 if (r
!= ERROR_OK
) {
2470 // over-write with new data
2471 n
= (pPrivate
->page_size
- page_offset
);
2472 memcpy(pagebuffer
+ page_offset
,
2476 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2477 if (r
!= ERROR_OK
) {
2487 // intermediate large pages
2488 // also - the final *terminal*
2489 // if that terminal page is a full page
2490 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2491 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
2493 while ((page_cur
< page_end
) &&
2494 (count
>= pPrivate
->page_size
)) {
2495 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
2496 if (r
!= ERROR_OK
) {
2499 count
-= pPrivate
->page_size
;
2500 buffer
+= pPrivate
->page_size
;
2504 // terminal partial page?
2506 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
2507 // we have a partial page
2508 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2509 if (r
!= ERROR_OK
) {
2512 // data goes at start
2513 memcpy(pagebuffer
, buffer
, count
);
2514 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2515 if (r
!= ERROR_OK
) {
2530 COMMAND_HANDLER(sam3_handle_info_command
)
2532 struct sam3_chip
*pChip
;
2536 pChip
= get_current_sam3(CMD_CTX
);
2543 // bank0 must exist before we can do anything
2544 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2547 command_print(CMD_CTX
,
2548 "Please define bank %d via command: flash bank %s ... ",
2550 at91sam3_flash
.name
);
2554 // if bank 0 is not probed, then probe it
2555 if (!(pChip
->details
.bank
[0].probed
)) {
2556 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
2557 if (r
!= ERROR_OK
) {
2561 // above guarantees the "chip details" structure is valid
2562 // and thus, bank private areas are valid
2563 // and we have a SAM3 chip, what a concept!
2566 // auto-probe other banks, 0 done above
2567 for (x
= 1 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2568 // skip banks not present
2569 if (!(pChip
->details
.bank
[x
].present
)) {
2573 if (pChip
->details
.bank
[x
].pBank
== NULL
) {
2577 if (pChip
->details
.bank
[x
].probed
) {
2581 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
2582 if (r
!= ERROR_OK
) {
2588 r
= sam3_GetInfo(pChip
);
2589 if (r
!= ERROR_OK
) {
2590 LOG_DEBUG("Sam3Info, Failed %d\n",r
);
2597 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
2601 struct sam3_chip
*pChip
;
2603 pChip
= get_current_sam3(CMD_CTX
);
2608 if (pChip
->target
->state
!= TARGET_HALTED
) {
2609 LOG_ERROR("sam3 - target not halted");
2610 return ERROR_TARGET_NOT_HALTED
;
2614 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2615 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
2616 at91sam3_flash
.name
);
2619 if (!pChip
->details
.bank
[0].probed
) {
2620 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
2621 if (r
!= ERROR_OK
) {
2629 command_print(CMD_CTX
,"Too many parameters\n");
2630 return ERROR_COMMAND_SYNTAX_ERROR
;
2640 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all"))) {
2644 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
2650 if (0 == strcmp("show", CMD_ARGV
[0])) {
2654 for (x
= 0 ; x
< pChip
->details
.n_gpnvms
; x
++) {
2655 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
2656 if (r
!= ERROR_OK
) {
2659 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
2663 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
2664 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
2665 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
2668 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
2669 return ERROR_COMMAND_SYNTAX_ERROR
;
2674 command_print(CMD_CTX
, "Missing GPNVM number");
2675 return ERROR_COMMAND_SYNTAX_ERROR
;
2678 if (0 == strcmp("set", CMD_ARGV
[0])) {
2679 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
2680 } else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
2681 (0 == strcmp("clear", CMD_ARGV
[0]))) { // quietly accept both
2682 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
2684 command_print(CMD_CTX
, "Unkown command: %s", CMD_ARGV
[0]);
2685 r
= ERROR_COMMAND_SYNTAX_ERROR
;
2690 COMMAND_HANDLER(sam3_handle_slowclk_command
)
2692 struct sam3_chip
*pChip
;
2694 pChip
= get_current_sam3(CMD_CTX
);
2708 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
2710 // absurd slow clock of 200Khz?
2711 command_print(CMD_CTX
,"Absurd/illegal slow clock freq: %d\n", (int)(v
));
2712 return ERROR_COMMAND_SYNTAX_ERROR
;
2714 pChip
->cfg
.slow_freq
= v
;
2719 command_print(CMD_CTX
,"Too many parameters");
2720 return ERROR_COMMAND_SYNTAX_ERROR
;
2723 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
2724 (int)(pChip
->cfg
.slow_freq
/ 1000),
2725 (int)(pChip
->cfg
.slow_freq
% 1000));
2729 static const struct command_registration at91sam3_exec_command_handlers
[] = {
2732 .handler
= sam3_handle_gpnvm_command
,
2733 .mode
= COMMAND_EXEC
,
2734 .usage
= "[('clr'|'set'|'show') bitnum]",
2735 .help
= "Without arguments, shows all bits in the gpnvm "
2736 "register. Otherwise, clears, sets, or shows one "
2737 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2741 .handler
= sam3_handle_info_command
,
2742 .mode
= COMMAND_EXEC
,
2743 .help
= "Print information about the current at91sam3 chip"
2744 "and its flash configuration.",
2748 .handler
= sam3_handle_slowclk_command
,
2749 .mode
= COMMAND_EXEC
,
2750 .usage
= "[clock_hz]",
2751 .help
= "Display or set the slowclock frequency "
2752 "(default 32768 Hz).",
2754 COMMAND_REGISTRATION_DONE
2756 static const struct command_registration at91sam3_command_handlers
[] = {
2759 .mode
= COMMAND_ANY
,
2760 .help
= "at91sam3 flash command group",
2761 .chain
= at91sam3_exec_command_handlers
,
2763 COMMAND_REGISTRATION_DONE
2766 struct flash_driver at91sam3_flash
= {
2768 .commands
= at91sam3_command_handlers
,
2769 .flash_bank_command
= sam3_flash_bank_command
,
2770 .erase
= sam3_erase
,
2771 .protect
= sam3_protect
,
2772 .write
= sam3_write
,
2773 .read
= default_flash_read
,
2774 .probe
= sam3_probe
,
2775 .auto_probe
= sam3_auto_probe
,
2776 .erase_check
= sam3_erase_check
,
2777 .protect_check
= sam3_protect_check
,
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