1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-Source-Code)
4 * Copyright (C) 2009 by Duane Ellis <openocd@duaneellis.com>
7 * Copyright (C) 2010 by Olaf Lüke <olaf@uni-paderborn.de>
8 * Copyright (C) 2011 by Olivier Schonken and Jim Norris
10 * Some of the lower level code was based on code supplied by
11 * ATMEL under BSD-Source-Code License and this copyright.
12 * ATMEL Microcontroller Software Support
13 * Copyright (c) 2009, Atmel Corporation. All rights reserved.
21 #include <helper/time_support.h>
23 #define REG_NAME_WIDTH (12)
25 /* at91sam3u series (has one or two flash banks) */
26 #define FLASH_BANK0_BASE_U 0x00080000
27 #define FLASH_BANK1_BASE_U 0x00100000
29 /* at91sam3s series (has always one flash bank) */
30 #define FLASH_BANK_BASE_S 0x00400000
32 /* at91sam3sd series (has always two flash banks) */
33 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
34 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
37 /* at91sam3n series (has always one flash bank) */
38 #define FLASH_BANK_BASE_N 0x00400000
40 /* at91sam3a/x series has two flash banks*/
41 #define FLASH_BANK0_BASE_AX 0x00080000
42 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
43 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
44 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
46 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
47 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
48 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
49 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
50 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
51 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
52 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
53 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
54 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
55 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
56 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
57 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
58 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
59 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
60 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
61 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
62 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
63 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
65 #define OFFSET_EFC_FMR 0
66 #define OFFSET_EFC_FCR 4
67 #define OFFSET_EFC_FSR 8
68 #define OFFSET_EFC_FRR 12
70 static float _tomhz(uint32_t freq_hz
)
74 f
= ((float)(freq_hz
)) / 1000000.0;
78 /* How the chip is configured. */
80 uint32_t unique_id
[4];
84 uint32_t mainosc_freq
;
94 #define SAM3_CHIPID_CIDR (0x400E0740)
96 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
97 uint32_t CHIPID_CIDR2
;
98 #define SAM3_CHIPID_EXID (0x400E0744)
100 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
101 uint32_t CHIPID_EXID2
;
104 #define SAM3_PMC_BASE (0x400E0400)
105 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
107 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
109 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
111 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
113 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
115 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
117 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
119 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
121 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
123 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
125 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
127 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
129 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
131 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
136 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
137 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
138 * the flash wait state (FWS) should be set to 6. It seems like that the
139 * cause of the problem is not the flash itself, but the flash write
140 * buffer. Ie the wait states have to be set before writing into the
142 * Tested and confirmed with SAM3N and SAM3U
145 struct sam3_bank_private
{
147 /* DANGER: THERE ARE DRAGONS HERE.. */
148 /* NOTE: If you add more 'ghost' pointers */
149 /* be aware that you must *manually* update */
150 /* these pointers in the function sam3_get_details() */
151 /* See the comment "Here there be dragons" */
153 /* so we can find the chip we belong to */
154 struct sam3_chip
*chip
;
155 /* so we can find the original bank pointer */
156 struct flash_bank
*bank
;
157 unsigned bank_number
;
158 uint32_t controller_address
;
159 uint32_t base_address
;
160 uint32_t flash_wait_states
;
164 unsigned sector_size
;
168 struct sam3_chip_details
{
169 /* THERE ARE DRAGONS HERE.. */
170 /* note: If you add pointers here */
171 /* be careful about them as they */
172 /* may need to be updated inside */
173 /* the function: "sam3_get_details() */
174 /* which copy/overwrites the */
175 /* 'runtime' copy of this structure */
176 uint32_t chipid_cidr
;
180 #define SAM3_N_NVM_BITS 3
181 unsigned gpnvm
[SAM3_N_NVM_BITS
];
182 unsigned total_flash_size
;
183 unsigned total_sram_size
;
185 #define SAM3_MAX_FLASH_BANKS 2
186 /* these are "initialized" from the global const data */
187 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
191 struct sam3_chip
*next
;
194 /* this is "initialized" from the global const structure */
195 struct sam3_chip_details details
;
196 struct target
*target
;
201 struct sam3_reg_list
{
202 uint32_t address
; size_t struct_offset
; const char *name
;
203 void (*explain_func
)(struct sam3_chip
*chip
);
206 static struct sam3_chip
*all_sam3_chips
;
208 static struct sam3_chip
*get_current_sam3(struct command_invocation
*cmd
)
211 static struct sam3_chip
*p
;
213 t
= get_current_target(cmd
->ctx
);
215 command_print_sameline(cmd
, "No current target?\n");
221 /* this should not happen */
222 /* the command is not registered until the chip is created? */
223 command_print_sameline(cmd
, "No SAM3 chips exist?\n");
232 command_print_sameline(cmd
, "Cannot find SAM3 chip?\n");
236 /* these are used to *initialize* the "chip->details" structure. */
237 static const struct sam3_chip_details all_sam3_details
[] = {
238 /* Start at91sam3u* series */
240 .chipid_cidr
= 0x28100960,
241 .name
= "at91sam3u4e",
242 .total_flash_size
= 256 * 1024,
243 .total_sram_size
= 52 * 1024,
247 /* System boots at address 0x0 */
248 /* gpnvm[1] = selects boot code */
249 /* if gpnvm[1] == 0 */
250 /* boot is via "SAMBA" (rom) */
252 /* boot is via FLASH */
253 /* Selection is via gpnvm[2] */
256 /* NOTE: banks 0 & 1 switch places */
257 /* if gpnvm[2] == 0 */
258 /* Bank0 is the boot rom */
260 /* Bank1 is the boot rom */
269 .base_address
= FLASH_BANK0_BASE_U
,
270 .controller_address
= 0x400e0800,
271 .flash_wait_states
= 6, /* workaround silicon bug */
273 .size_bytes
= 128 * 1024,
285 .base_address
= FLASH_BANK1_BASE_U
,
286 .controller_address
= 0x400e0a00,
287 .flash_wait_states
= 6, /* workaround silicon bug */
289 .size_bytes
= 128 * 1024,
298 .chipid_cidr
= 0x281a0760,
299 .name
= "at91sam3u2e",
300 .total_flash_size
= 128 * 1024,
301 .total_sram_size
= 36 * 1024,
305 /* System boots at address 0x0 */
306 /* gpnvm[1] = selects boot code */
307 /* if gpnvm[1] == 0 */
308 /* boot is via "SAMBA" (rom) */
310 /* boot is via FLASH */
311 /* Selection is via gpnvm[2] */
320 .base_address
= FLASH_BANK0_BASE_U
,
321 .controller_address
= 0x400e0800,
322 .flash_wait_states
= 6, /* workaround silicon bug */
324 .size_bytes
= 128 * 1024,
338 .chipid_cidr
= 0x28190560,
339 .name
= "at91sam3u1e",
340 .total_flash_size
= 64 * 1024,
341 .total_sram_size
= 20 * 1024,
345 /* System boots at address 0x0 */
346 /* gpnvm[1] = selects boot code */
347 /* if gpnvm[1] == 0 */
348 /* boot is via "SAMBA" (rom) */
350 /* boot is via FLASH */
351 /* Selection is via gpnvm[2] */
362 .base_address
= FLASH_BANK0_BASE_U
,
363 .controller_address
= 0x400e0800,
364 .flash_wait_states
= 6, /* workaround silicon bug */
366 .size_bytes
= 64 * 1024,
382 .chipid_cidr
= 0x28000960,
383 .name
= "at91sam3u4c",
384 .total_flash_size
= 256 * 1024,
385 .total_sram_size
= 52 * 1024,
389 /* System boots at address 0x0 */
390 /* gpnvm[1] = selects boot code */
391 /* if gpnvm[1] == 0 */
392 /* boot is via "SAMBA" (rom) */
394 /* boot is via FLASH */
395 /* Selection is via gpnvm[2] */
398 /* NOTE: banks 0 & 1 switch places */
399 /* if gpnvm[2] == 0 */
400 /* Bank0 is the boot rom */
402 /* Bank1 is the boot rom */
411 .base_address
= FLASH_BANK0_BASE_U
,
412 .controller_address
= 0x400e0800,
413 .flash_wait_states
= 6, /* workaround silicon bug */
415 .size_bytes
= 128 * 1024,
426 .base_address
= FLASH_BANK1_BASE_U
,
427 .controller_address
= 0x400e0a00,
428 .flash_wait_states
= 6, /* workaround silicon bug */
430 .size_bytes
= 128 * 1024,
439 .chipid_cidr
= 0x280a0760,
440 .name
= "at91sam3u2c",
441 .total_flash_size
= 128 * 1024,
442 .total_sram_size
= 36 * 1024,
446 /* System boots at address 0x0 */
447 /* gpnvm[1] = selects boot code */
448 /* if gpnvm[1] == 0 */
449 /* boot is via "SAMBA" (rom) */
451 /* boot is via FLASH */
452 /* Selection is via gpnvm[2] */
461 .base_address
= FLASH_BANK0_BASE_U
,
462 .controller_address
= 0x400e0800,
463 .flash_wait_states
= 6, /* workaround silicon bug */
465 .size_bytes
= 128 * 1024,
479 .chipid_cidr
= 0x28090560,
480 .name
= "at91sam3u1c",
481 .total_flash_size
= 64 * 1024,
482 .total_sram_size
= 20 * 1024,
486 /* System boots at address 0x0 */
487 /* gpnvm[1] = selects boot code */
488 /* if gpnvm[1] == 0 */
489 /* boot is via "SAMBA" (rom) */
491 /* boot is via FLASH */
492 /* Selection is via gpnvm[2] */
503 .base_address
= FLASH_BANK0_BASE_U
,
504 .controller_address
= 0x400e0800,
505 .flash_wait_states
= 6, /* workaround silicon bug */
507 .size_bytes
= 64 * 1024,
522 /* Start at91sam3s* series */
524 /* Note: The preliminary at91sam3s datasheet says on page 302 */
525 /* that the flash controller is at address 0x400E0800. */
526 /* This is _not_ the case, the controller resides at address 0x400e0a00. */
528 .chipid_cidr
= 0x28A00960,
529 .name
= "at91sam3s4c",
530 .total_flash_size
= 256 * 1024,
531 .total_sram_size
= 48 * 1024,
541 .base_address
= FLASH_BANK_BASE_S
,
542 .controller_address
= 0x400e0a00,
543 .flash_wait_states
= 6, /* workaround silicon bug */
545 .size_bytes
= 256 * 1024,
547 .sector_size
= 16384,
561 .chipid_cidr
= 0x28900960,
562 .name
= "at91sam3s4b",
563 .total_flash_size
= 256 * 1024,
564 .total_sram_size
= 48 * 1024,
574 .base_address
= FLASH_BANK_BASE_S
,
575 .controller_address
= 0x400e0a00,
576 .flash_wait_states
= 6, /* workaround silicon bug */
578 .size_bytes
= 256 * 1024,
580 .sector_size
= 16384,
593 .chipid_cidr
= 0x28800960,
594 .name
= "at91sam3s4a",
595 .total_flash_size
= 256 * 1024,
596 .total_sram_size
= 48 * 1024,
606 .base_address
= FLASH_BANK_BASE_S
,
607 .controller_address
= 0x400e0a00,
608 .flash_wait_states
= 6, /* workaround silicon bug */
610 .size_bytes
= 256 * 1024,
612 .sector_size
= 16384,
625 .chipid_cidr
= 0x28AA0760,
626 .name
= "at91sam3s2c",
627 .total_flash_size
= 128 * 1024,
628 .total_sram_size
= 32 * 1024,
638 .base_address
= FLASH_BANK_BASE_S
,
639 .controller_address
= 0x400e0a00,
640 .flash_wait_states
= 6, /* workaround silicon bug */
642 .size_bytes
= 128 * 1024,
644 .sector_size
= 16384,
657 .chipid_cidr
= 0x289A0760,
658 .name
= "at91sam3s2b",
659 .total_flash_size
= 128 * 1024,
660 .total_sram_size
= 32 * 1024,
670 .base_address
= FLASH_BANK_BASE_S
,
671 .controller_address
= 0x400e0a00,
672 .flash_wait_states
= 6, /* workaround silicon bug */
674 .size_bytes
= 128 * 1024,
676 .sector_size
= 16384,
689 .chipid_cidr
= 0x298B0A60,
690 .name
= "at91sam3sd8a",
691 .total_flash_size
= 512 * 1024,
692 .total_sram_size
= 64 * 1024,
702 .base_address
= FLASH_BANK0_BASE_SD
,
703 .controller_address
= 0x400e0a00,
704 .flash_wait_states
= 6, /* workaround silicon bug */
706 .size_bytes
= 256 * 1024,
708 .sector_size
= 32768,
717 .base_address
= FLASH_BANK1_BASE_512K_SD
,
718 .controller_address
= 0x400e0a00,
719 .flash_wait_states
= 6, /* workaround silicon bug */
721 .size_bytes
= 256 * 1024,
723 .sector_size
= 32768,
729 .chipid_cidr
= 0x299B0A60,
730 .name
= "at91sam3sd8b",
731 .total_flash_size
= 512 * 1024,
732 .total_sram_size
= 64 * 1024,
742 .base_address
= FLASH_BANK0_BASE_SD
,
743 .controller_address
= 0x400e0a00,
744 .flash_wait_states
= 6, /* workaround silicon bug */
746 .size_bytes
= 256 * 1024,
748 .sector_size
= 32768,
757 .base_address
= FLASH_BANK1_BASE_512K_SD
,
758 .controller_address
= 0x400e0a00,
759 .flash_wait_states
= 6, /* workaround silicon bug */
761 .size_bytes
= 256 * 1024,
763 .sector_size
= 32768,
769 .chipid_cidr
= 0x29ab0a60,
770 .name
= "at91sam3sd8c",
771 .total_flash_size
= 512 * 1024,
772 .total_sram_size
= 64 * 1024,
782 .base_address
= FLASH_BANK0_BASE_SD
,
783 .controller_address
= 0x400e0a00,
784 .flash_wait_states
= 6, /* workaround silicon bug */
786 .size_bytes
= 256 * 1024,
788 .sector_size
= 32768,
797 .base_address
= FLASH_BANK1_BASE_512K_SD
,
798 .controller_address
= 0x400e0a00,
799 .flash_wait_states
= 6, /* workaround silicon bug */
801 .size_bytes
= 256 * 1024,
803 .sector_size
= 32768,
809 .chipid_cidr
= 0x288A0760,
810 .name
= "at91sam3s2a",
811 .total_flash_size
= 128 * 1024,
812 .total_sram_size
= 32 * 1024,
822 .base_address
= FLASH_BANK_BASE_S
,
823 .controller_address
= 0x400e0a00,
824 .flash_wait_states
= 6, /* workaround silicon bug */
826 .size_bytes
= 128 * 1024,
828 .sector_size
= 16384,
841 .chipid_cidr
= 0x28A90560,
842 .name
= "at91sam3s1c",
843 .total_flash_size
= 64 * 1024,
844 .total_sram_size
= 16 * 1024,
854 .base_address
= FLASH_BANK_BASE_S
,
855 .controller_address
= 0x400e0a00,
856 .flash_wait_states
= 6, /* workaround silicon bug */
858 .size_bytes
= 64 * 1024,
860 .sector_size
= 16384,
873 .chipid_cidr
= 0x28990560,
874 .name
= "at91sam3s1b",
875 .total_flash_size
= 64 * 1024,
876 .total_sram_size
= 16 * 1024,
886 .base_address
= FLASH_BANK_BASE_S
,
887 .controller_address
= 0x400e0a00,
888 .flash_wait_states
= 6, /* workaround silicon bug */
890 .size_bytes
= 64 * 1024,
892 .sector_size
= 16384,
905 .chipid_cidr
= 0x28890560,
906 .name
= "at91sam3s1a",
907 .total_flash_size
= 64 * 1024,
908 .total_sram_size
= 16 * 1024,
918 .base_address
= FLASH_BANK_BASE_S
,
919 .controller_address
= 0x400e0a00,
920 .flash_wait_states
= 6, /* workaround silicon bug */
922 .size_bytes
= 64 * 1024,
924 .sector_size
= 16384,
937 .chipid_cidr
= 0x288B0A60,
938 .name
= "at91sam3s8a",
939 .total_flash_size
= 256 * 2048,
940 .total_sram_size
= 64 * 1024,
950 .base_address
= FLASH_BANK_BASE_S
,
951 .controller_address
= 0x400e0a00,
952 .flash_wait_states
= 6, /* workaround silicon bug */
954 .size_bytes
= 256 * 2048,
956 .sector_size
= 32768,
969 .chipid_cidr
= 0x289B0A60,
970 .name
= "at91sam3s8b",
971 .total_flash_size
= 256 * 2048,
972 .total_sram_size
= 64 * 1024,
982 .base_address
= FLASH_BANK_BASE_S
,
983 .controller_address
= 0x400e0a00,
984 .flash_wait_states
= 6, /* workaround silicon bug */
986 .size_bytes
= 256 * 2048,
988 .sector_size
= 32768,
1001 .chipid_cidr
= 0x28AB0A60,
1002 .name
= "at91sam3s8c",
1003 .total_flash_size
= 256 * 2048,
1004 .total_sram_size
= 64 * 1024,
1014 .base_address
= FLASH_BANK_BASE_S
,
1015 .controller_address
= 0x400e0a00,
1016 .flash_wait_states
= 6, /* workaround silicon bug */
1018 .size_bytes
= 256 * 2048,
1020 .sector_size
= 32768,
1033 /* Start at91sam3n* series */
1035 .chipid_cidr
= 0x29540960,
1036 .name
= "at91sam3n4c",
1037 .total_flash_size
= 256 * 1024,
1038 .total_sram_size
= 24 * 1024,
1042 /* System boots at address 0x0 */
1043 /* gpnvm[1] = selects boot code */
1044 /* if gpnvm[1] == 0 */
1045 /* boot is via "SAMBA" (rom) */
1047 /* boot is via FLASH */
1048 /* Selection is via gpnvm[2] */
1051 /* NOTE: banks 0 & 1 switch places */
1052 /* if gpnvm[2] == 0 */
1053 /* Bank0 is the boot rom */
1055 /* Bank1 is the boot rom */
1064 .base_address
= FLASH_BANK_BASE_N
,
1065 .controller_address
= 0x400e0A00,
1066 .flash_wait_states
= 6, /* workaround silicon bug */
1068 .size_bytes
= 256 * 1024,
1070 .sector_size
= 16384,
1084 .chipid_cidr
= 0x29440960,
1085 .name
= "at91sam3n4b",
1086 .total_flash_size
= 256 * 1024,
1087 .total_sram_size
= 24 * 1024,
1091 /* System boots at address 0x0 */
1092 /* gpnvm[1] = selects boot code */
1093 /* if gpnvm[1] == 0 */
1094 /* boot is via "SAMBA" (rom) */
1096 /* boot is via FLASH */
1097 /* Selection is via gpnvm[2] */
1100 /* NOTE: banks 0 & 1 switch places */
1101 /* if gpnvm[2] == 0 */
1102 /* Bank0 is the boot rom */
1104 /* Bank1 is the boot rom */
1113 .base_address
= FLASH_BANK_BASE_N
,
1114 .controller_address
= 0x400e0A00,
1115 .flash_wait_states
= 6, /* workaround silicon bug */
1117 .size_bytes
= 256 * 1024,
1119 .sector_size
= 16384,
1133 .chipid_cidr
= 0x29340960,
1134 .name
= "at91sam3n4a",
1135 .total_flash_size
= 256 * 1024,
1136 .total_sram_size
= 24 * 1024,
1140 /* System boots at address 0x0 */
1141 /* gpnvm[1] = selects boot code */
1142 /* if gpnvm[1] == 0 */
1143 /* boot is via "SAMBA" (rom) */
1145 /* boot is via FLASH */
1146 /* Selection is via gpnvm[2] */
1149 /* NOTE: banks 0 & 1 switch places */
1150 /* if gpnvm[2] == 0 */
1151 /* Bank0 is the boot rom */
1153 /* Bank1 is the boot rom */
1162 .base_address
= FLASH_BANK_BASE_N
,
1163 .controller_address
= 0x400e0A00,
1164 .flash_wait_states
= 6, /* workaround silicon bug */
1166 .size_bytes
= 256 * 1024,
1168 .sector_size
= 16384,
1182 .chipid_cidr
= 0x29590760,
1183 .name
= "at91sam3n2c",
1184 .total_flash_size
= 128 * 1024,
1185 .total_sram_size
= 16 * 1024,
1189 /* System boots at address 0x0 */
1190 /* gpnvm[1] = selects boot code */
1191 /* if gpnvm[1] == 0 */
1192 /* boot is via "SAMBA" (rom) */
1194 /* boot is via FLASH */
1195 /* Selection is via gpnvm[2] */
1198 /* NOTE: banks 0 & 1 switch places */
1199 /* if gpnvm[2] == 0 */
1200 /* Bank0 is the boot rom */
1202 /* Bank1 is the boot rom */
1211 .base_address
= FLASH_BANK_BASE_N
,
1212 .controller_address
= 0x400e0A00,
1213 .flash_wait_states
= 6, /* workaround silicon bug */
1215 .size_bytes
= 128 * 1024,
1217 .sector_size
= 16384,
1231 .chipid_cidr
= 0x29490760,
1232 .name
= "at91sam3n2b",
1233 .total_flash_size
= 128 * 1024,
1234 .total_sram_size
= 16 * 1024,
1238 /* System boots at address 0x0 */
1239 /* gpnvm[1] = selects boot code */
1240 /* if gpnvm[1] == 0 */
1241 /* boot is via "SAMBA" (rom) */
1243 /* boot is via FLASH */
1244 /* Selection is via gpnvm[2] */
1247 /* NOTE: banks 0 & 1 switch places */
1248 /* if gpnvm[2] == 0 */
1249 /* Bank0 is the boot rom */
1251 /* Bank1 is the boot rom */
1260 .base_address
= FLASH_BANK_BASE_N
,
1261 .controller_address
= 0x400e0A00,
1262 .flash_wait_states
= 6, /* workaround silicon bug */
1264 .size_bytes
= 128 * 1024,
1266 .sector_size
= 16384,
1280 .chipid_cidr
= 0x29390760,
1281 .name
= "at91sam3n2a",
1282 .total_flash_size
= 128 * 1024,
1283 .total_sram_size
= 16 * 1024,
1287 /* System boots at address 0x0 */
1288 /* gpnvm[1] = selects boot code */
1289 /* if gpnvm[1] == 0 */
1290 /* boot is via "SAMBA" (rom) */
1292 /* boot is via FLASH */
1293 /* Selection is via gpnvm[2] */
1296 /* NOTE: banks 0 & 1 switch places */
1297 /* if gpnvm[2] == 0 */
1298 /* Bank0 is the boot rom */
1300 /* Bank1 is the boot rom */
1309 .base_address
= FLASH_BANK_BASE_N
,
1310 .controller_address
= 0x400e0A00,
1311 .flash_wait_states
= 6, /* workaround silicon bug */
1313 .size_bytes
= 128 * 1024,
1315 .sector_size
= 16384,
1329 .chipid_cidr
= 0x29580560,
1330 .name
= "at91sam3n1c",
1331 .total_flash_size
= 64 * 1024,
1332 .total_sram_size
= 8 * 1024,
1336 /* System boots at address 0x0 */
1337 /* gpnvm[1] = selects boot code */
1338 /* if gpnvm[1] == 0 */
1339 /* boot is via "SAMBA" (rom) */
1341 /* boot is via FLASH */
1342 /* Selection is via gpnvm[2] */
1345 /* NOTE: banks 0 & 1 switch places */
1346 /* if gpnvm[2] == 0 */
1347 /* Bank0 is the boot rom */
1349 /* Bank1 is the boot rom */
1358 .base_address
= FLASH_BANK_BASE_N
,
1359 .controller_address
= 0x400e0A00,
1360 .flash_wait_states
= 6, /* workaround silicon bug */
1362 .size_bytes
= 64 * 1024,
1364 .sector_size
= 16384,
1378 .chipid_cidr
= 0x29480560,
1379 .name
= "at91sam3n1b",
1380 .total_flash_size
= 64 * 1024,
1381 .total_sram_size
= 8 * 1024,
1385 /* System boots at address 0x0 */
1386 /* gpnvm[1] = selects boot code */
1387 /* if gpnvm[1] == 0 */
1388 /* boot is via "SAMBA" (rom) */
1390 /* boot is via FLASH */
1391 /* Selection is via gpnvm[2] */
1394 /* NOTE: banks 0 & 1 switch places */
1395 /* if gpnvm[2] == 0 */
1396 /* Bank0 is the boot rom */
1398 /* Bank1 is the boot rom */
1407 .base_address
= FLASH_BANK_BASE_N
,
1408 .controller_address
= 0x400e0A00,
1409 .flash_wait_states
= 6, /* workaround silicon bug */
1411 .size_bytes
= 64 * 1024,
1413 .sector_size
= 16384,
1427 .chipid_cidr
= 0x29380560,
1428 .name
= "at91sam3n1a",
1429 .total_flash_size
= 64 * 1024,
1430 .total_sram_size
= 8 * 1024,
1434 /* System boots at address 0x0 */
1435 /* gpnvm[1] = selects boot code */
1436 /* if gpnvm[1] == 0 */
1437 /* boot is via "SAMBA" (rom) */
1439 /* boot is via FLASH */
1440 /* Selection is via gpnvm[2] */
1443 /* NOTE: banks 0 & 1 switch places */
1444 /* if gpnvm[2] == 0 */
1445 /* Bank0 is the boot rom */
1447 /* Bank1 is the boot rom */
1456 .base_address
= FLASH_BANK_BASE_N
,
1457 .controller_address
= 0x400e0A00,
1458 .flash_wait_states
= 6, /* workaround silicon bug */
1460 .size_bytes
= 64 * 1024,
1462 .sector_size
= 16384,
1476 .chipid_cidr
= 0x29480360,
1477 .name
= "at91sam3n0b",
1478 .total_flash_size
= 32 * 1024,
1479 .total_sram_size
= 8 * 1024,
1490 .base_address
= FLASH_BANK_BASE_N
,
1491 .controller_address
= 0x400e0A00,
1492 .flash_wait_states
= 6, /* workaround silicon bug */
1494 .size_bytes
= 32 * 1024,
1496 .sector_size
= 16384,
1510 .chipid_cidr
= 0x29380360,
1511 .name
= "at91sam3n0a",
1512 .total_flash_size
= 32 * 1024,
1513 .total_sram_size
= 8 * 1024,
1524 .base_address
= FLASH_BANK_BASE_N
,
1525 .controller_address
= 0x400e0A00,
1526 .flash_wait_states
= 6, /* workaround silicon bug */
1528 .size_bytes
= 32 * 1024,
1530 .sector_size
= 16384,
1544 .chipid_cidr
= 0x29450260,
1545 .name
= "at91sam3n00b",
1546 .total_flash_size
= 16 * 1024,
1547 .total_sram_size
= 4 * 1024,
1558 .base_address
= FLASH_BANK_BASE_N
,
1559 .controller_address
= 0x400e0A00,
1560 .flash_wait_states
= 6, /* workaround silicon bug */
1562 .size_bytes
= 16 * 1024,
1564 .sector_size
= 16384,
1578 .chipid_cidr
= 0x29350260,
1579 .name
= "at91sam3n00a",
1580 .total_flash_size
= 16 * 1024,
1581 .total_sram_size
= 4 * 1024,
1592 .base_address
= FLASH_BANK_BASE_N
,
1593 .controller_address
= 0x400e0A00,
1594 .flash_wait_states
= 6, /* workaround silicon bug */
1596 .size_bytes
= 16 * 1024,
1598 .sector_size
= 16384,
1612 /* Start at91sam3a series*/
1613 /* System boots at address 0x0 */
1614 /* gpnvm[1] = selects boot code */
1615 /* if gpnvm[1] == 0 */
1616 /* boot is via "SAMBA" (rom) */
1618 /* boot is via FLASH */
1619 /* Selection is via gpnvm[2] */
1622 /* NOTE: banks 0 & 1 switch places */
1623 /* if gpnvm[2] == 0 */
1624 /* Bank0 is the boot rom */
1626 /* Bank1 is the boot rom */
1630 .chipid_cidr
= 0x283E0A60,
1631 .name
= "at91sam3a8c",
1632 .total_flash_size
= 512 * 1024,
1633 .total_sram_size
= 96 * 1024,
1643 .base_address
= FLASH_BANK0_BASE_AX
,
1644 .controller_address
= 0x400e0a00,
1645 .flash_wait_states
= 6, /* workaround silicon bug */
1647 .size_bytes
= 256 * 1024,
1649 .sector_size
= 16384,
1658 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1659 .controller_address
= 0x400e0c00,
1660 .flash_wait_states
= 6, /* workaround silicon bug */
1662 .size_bytes
= 256 * 1024,
1664 .sector_size
= 16384,
1671 .chipid_cidr
= 0x283B0960,
1672 .name
= "at91sam3a4c",
1673 .total_flash_size
= 256 * 1024,
1674 .total_sram_size
= 64 * 1024,
1684 .base_address
= FLASH_BANK0_BASE_AX
,
1685 .controller_address
= 0x400e0a00,
1686 .flash_wait_states
= 6, /* workaround silicon bug */
1688 .size_bytes
= 128 * 1024,
1690 .sector_size
= 16384,
1699 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1700 .controller_address
= 0x400e0c00,
1701 .flash_wait_states
= 6, /* workaround silicon bug */
1703 .size_bytes
= 128 * 1024,
1705 .sector_size
= 16384,
1712 /* Start at91sam3x* series */
1713 /* System boots at address 0x0 */
1714 /* gpnvm[1] = selects boot code */
1715 /* if gpnvm[1] == 0 */
1716 /* boot is via "SAMBA" (rom) */
1718 /* boot is via FLASH */
1719 /* Selection is via gpnvm[2] */
1722 /* NOTE: banks 0 & 1 switch places */
1723 /* if gpnvm[2] == 0 */
1724 /* Bank0 is the boot rom */
1726 /* Bank1 is the boot rom */
1728 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1730 .chipid_cidr
= 0x286E0A20,
1731 .name
= "at91sam3x8h - ES",
1732 .total_flash_size
= 512 * 1024,
1733 .total_sram_size
= 96 * 1024,
1743 .base_address
= FLASH_BANK0_BASE_AX
,
1744 .controller_address
= 0x400e0a00,
1745 .flash_wait_states
= 6, /* workaround silicon bug */
1747 .size_bytes
= 256 * 1024,
1749 .sector_size
= 16384,
1758 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1759 .controller_address
= 0x400e0c00,
1760 .flash_wait_states
= 6, /* workaround silicon bug */
1762 .size_bytes
= 256 * 1024,
1764 .sector_size
= 16384,
1770 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1772 .chipid_cidr
= 0x286E0A60,
1773 .name
= "at91sam3x8h",
1774 .total_flash_size
= 512 * 1024,
1775 .total_sram_size
= 96 * 1024,
1785 .base_address
= FLASH_BANK0_BASE_AX
,
1786 .controller_address
= 0x400e0a00,
1787 .flash_wait_states
= 6, /* workaround silicon bug */
1789 .size_bytes
= 256 * 1024,
1791 .sector_size
= 16384,
1800 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1801 .controller_address
= 0x400e0c00,
1802 .flash_wait_states
= 6, /* workaround silicon bug */
1804 .size_bytes
= 256 * 1024,
1806 .sector_size
= 16384,
1813 .chipid_cidr
= 0x285E0A60,
1814 .name
= "at91sam3x8e",
1815 .total_flash_size
= 512 * 1024,
1816 .total_sram_size
= 96 * 1024,
1826 .base_address
= FLASH_BANK0_BASE_AX
,
1827 .controller_address
= 0x400e0a00,
1828 .flash_wait_states
= 6, /* workaround silicon bug */
1830 .size_bytes
= 256 * 1024,
1832 .sector_size
= 16384,
1841 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1842 .controller_address
= 0x400e0c00,
1843 .flash_wait_states
= 6, /* workaround silicon bug */
1845 .size_bytes
= 256 * 1024,
1847 .sector_size
= 16384,
1854 .chipid_cidr
= 0x284E0A60,
1855 .name
= "at91sam3x8c",
1856 .total_flash_size
= 512 * 1024,
1857 .total_sram_size
= 96 * 1024,
1867 .base_address
= FLASH_BANK0_BASE_AX
,
1868 .controller_address
= 0x400e0a00,
1869 .flash_wait_states
= 6, /* workaround silicon bug */
1871 .size_bytes
= 256 * 1024,
1873 .sector_size
= 16384,
1882 .base_address
= FLASH_BANK1_BASE_512K_AX
,
1883 .controller_address
= 0x400e0c00,
1884 .flash_wait_states
= 6, /* workaround silicon bug */
1886 .size_bytes
= 256 * 1024,
1888 .sector_size
= 16384,
1895 .chipid_cidr
= 0x285B0960,
1896 .name
= "at91sam3x4e",
1897 .total_flash_size
= 256 * 1024,
1898 .total_sram_size
= 64 * 1024,
1908 .base_address
= FLASH_BANK0_BASE_AX
,
1909 .controller_address
= 0x400e0a00,
1910 .flash_wait_states
= 6, /* workaround silicon bug */
1912 .size_bytes
= 128 * 1024,
1914 .sector_size
= 16384,
1923 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1924 .controller_address
= 0x400e0c00,
1925 .flash_wait_states
= 6, /* workaround silicon bug */
1927 .size_bytes
= 128 * 1024,
1929 .sector_size
= 16384,
1936 .chipid_cidr
= 0x284B0960,
1937 .name
= "at91sam3x4c",
1938 .total_flash_size
= 256 * 1024,
1939 .total_sram_size
= 64 * 1024,
1949 .base_address
= FLASH_BANK0_BASE_AX
,
1950 .controller_address
= 0x400e0a00,
1951 .flash_wait_states
= 6, /* workaround silicon bug */
1953 .size_bytes
= 128 * 1024,
1955 .sector_size
= 16384,
1964 .base_address
= FLASH_BANK1_BASE_256K_AX
,
1965 .controller_address
= 0x400e0c00,
1966 .flash_wait_states
= 6, /* workaround silicon bug */
1968 .size_bytes
= 128 * 1024,
1970 .sector_size
= 16384,
1984 /***********************************************************************
1985 **********************************************************************
1986 **********************************************************************
1987 **********************************************************************
1988 **********************************************************************
1989 **********************************************************************/
1990 /* *ATMEL* style code - from the SAM3 driver code */
1993 * Get the current status of the EEFC and
1994 * the value of some status bits (LOCKE, PROGE).
1995 * @param private - info about the bank
1996 * @param v - result goes here
1998 static int efc_get_status(struct sam3_bank_private
*private, uint32_t *v
)
2001 r
= target_read_u32(private->chip
->target
,
2002 private->controller_address
+ OFFSET_EFC_FSR
,
2004 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2006 ((unsigned int)((*v
>> 2) & 1)),
2007 ((unsigned int)((*v
>> 1) & 1)),
2008 ((unsigned int)((*v
>> 0) & 1)));
2014 * Get the result of the last executed command.
2015 * @param private - info about the bank
2016 * @param v - result goes here
2018 static int efc_get_result(struct sam3_bank_private
*private, uint32_t *v
)
2022 r
= target_read_u32(private->chip
->target
,
2023 private->controller_address
+ OFFSET_EFC_FRR
,
2027 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
2031 static int efc_start_command(struct sam3_bank_private
*private,
2032 unsigned command
, unsigned argument
)
2041 /* Check command & argument */
2044 case AT91C_EFC_FCMD_WP
:
2045 case AT91C_EFC_FCMD_WPL
:
2046 case AT91C_EFC_FCMD_EWP
:
2047 case AT91C_EFC_FCMD_EWPL
:
2048 /* case AT91C_EFC_FCMD_EPL: */
2049 /* case AT91C_EFC_FCMD_EPA: */
2050 case AT91C_EFC_FCMD_SLB
:
2051 case AT91C_EFC_FCMD_CLB
:
2052 n
= (private->size_bytes
/ private->page_size
);
2054 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
2057 case AT91C_EFC_FCMD_SFB
:
2058 case AT91C_EFC_FCMD_CFB
:
2059 if (argument
>= private->chip
->details
.n_gpnvms
) {
2060 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2061 private->chip
->details
.n_gpnvms
);
2065 case AT91C_EFC_FCMD_GETD
:
2066 case AT91C_EFC_FCMD_EA
:
2067 case AT91C_EFC_FCMD_GLB
:
2068 case AT91C_EFC_FCMD_GFB
:
2069 case AT91C_EFC_FCMD_STUI
:
2070 case AT91C_EFC_FCMD_SPUI
:
2072 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
2075 LOG_ERROR("Unknown command %d", command
);
2079 if (command
== AT91C_EFC_FCMD_SPUI
) {
2080 /* this is a very special situation. */
2081 /* Situation (1) - error/retry - see below */
2082 /* And we are being called recursively */
2083 /* Situation (2) - normal, finished reading unique id */
2085 /* it should be "ready" */
2086 efc_get_status(private, &v
);
2088 /* then it is ready */
2092 /* we have done this before */
2093 /* the controller is not responding. */
2094 LOG_ERROR("flash controller(%d) is not ready! Error",
2095 private->bank_number
);
2099 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2100 private->bank_number
);
2101 /* we do that by issuing the *STOP* command */
2102 efc_start_command(private, AT91C_EFC_FCMD_SPUI
, 0);
2103 /* above is recursive, and further recursion is blocked by */
2104 /* if (command == AT91C_EFC_FCMD_SPUI) above */
2110 v
= (0x5A << 24) | (argument
<< 8) | command
;
2111 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
2112 r
= target_write_u32(private->bank
->target
,
2113 private->controller_address
+ OFFSET_EFC_FCR
, v
);
2115 LOG_DEBUG("Error Write failed");
2120 * Performs the given command and wait until its completion (or an error).
2121 * @param private - info about the bank
2122 * @param command - Command to perform.
2123 * @param argument - Optional command argument.
2124 * @param status - put command status bits here
2126 static int efc_perform_command(struct sam3_bank_private
*private,
2134 int64_t ms_now
, ms_end
;
2140 r
= efc_start_command(private, command
, argument
);
2144 ms_end
= 500 + timeval_ms();
2147 r
= efc_get_status(private, &v
);
2150 ms_now
= timeval_ms();
2151 if (ms_now
> ms_end
) {
2153 LOG_ERROR("Command timeout");
2156 } while ((v
& 1) == 0);
2160 *status
= (v
& 0x6);
2166 * Read the unique ID.
2167 * @param private - info about the bank
2168 * The unique ID is stored in the 'private' structure.
2170 static int flashd_read_uid(struct sam3_bank_private
*private)
2176 private->chip
->cfg
.unique_id
[0] = 0;
2177 private->chip
->cfg
.unique_id
[1] = 0;
2178 private->chip
->cfg
.unique_id
[2] = 0;
2179 private->chip
->cfg
.unique_id
[3] = 0;
2182 r
= efc_start_command(private, AT91C_EFC_FCMD_STUI
, 0);
2186 for (x
= 0; x
< 4; x
++) {
2187 r
= target_read_u32(private->chip
->target
,
2188 private->bank
->base
+ (x
* 4),
2192 private->chip
->cfg
.unique_id
[x
] = v
;
2195 r
= efc_perform_command(private, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
2196 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2198 (unsigned int)(private->chip
->cfg
.unique_id
[0]),
2199 (unsigned int)(private->chip
->cfg
.unique_id
[1]),
2200 (unsigned int)(private->chip
->cfg
.unique_id
[2]),
2201 (unsigned int)(private->chip
->cfg
.unique_id
[3]));
2207 * Erases the entire flash.
2208 * @param private - the info about the bank.
2210 static int flashd_erase_entire_bank(struct sam3_bank_private
*private)
2213 return efc_perform_command(private, AT91C_EFC_FCMD_EA
, 0, NULL
);
2217 * Gets current GPNVM state.
2218 * @param private - info about the bank.
2219 * @param gpnvm - GPNVM bit index.
2220 * @param puthere - result stored here.
2222 /* ------------------------------------------------------------------------------ */
2223 static int flashd_get_gpnvm(struct sam3_bank_private
*private, unsigned gpnvm
, unsigned *puthere
)
2229 if (private->bank_number
!= 0) {
2230 LOG_ERROR("GPNVM only works with Bank0");
2234 if (gpnvm
>= private->chip
->details
.n_gpnvms
) {
2235 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2236 gpnvm
, private->chip
->details
.n_gpnvms
);
2240 /* Get GPNVMs status */
2241 r
= efc_perform_command(private, AT91C_EFC_FCMD_GFB
, 0, NULL
);
2242 if (r
!= ERROR_OK
) {
2243 LOG_ERROR("Failed");
2247 r
= efc_get_result(private, &v
);
2250 /* Check if GPNVM is set */
2251 /* get the bit and make it a 0/1 */
2252 *puthere
= (v
>> gpnvm
) & 1;
2259 * Clears the selected GPNVM bit.
2260 * @param private info about the bank
2261 * @param gpnvm GPNVM index.
2262 * @returns 0 if successful; otherwise returns an error code.
2264 static int flashd_clr_gpnvm(struct sam3_bank_private
*private, unsigned gpnvm
)
2270 if (private->bank_number
!= 0) {
2271 LOG_ERROR("GPNVM only works with Bank0");
2275 if (gpnvm
>= private->chip
->details
.n_gpnvms
) {
2276 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2277 gpnvm
, private->chip
->details
.n_gpnvms
);
2281 r
= flashd_get_gpnvm(private, gpnvm
, &v
);
2282 if (r
!= ERROR_OK
) {
2283 LOG_DEBUG("Failed: %d", r
);
2286 r
= efc_perform_command(private, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
2287 LOG_DEBUG("End: %d", r
);
2292 * Sets the selected GPNVM bit.
2293 * @param private info about the bank
2294 * @param gpnvm GPNVM index.
2296 static int flashd_set_gpnvm(struct sam3_bank_private
*private, unsigned gpnvm
)
2301 if (private->bank_number
!= 0) {
2302 LOG_ERROR("GPNVM only works with Bank0");
2306 if (gpnvm
>= private->chip
->details
.n_gpnvms
) {
2307 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2308 gpnvm
, private->chip
->details
.n_gpnvms
);
2312 r
= flashd_get_gpnvm(private, gpnvm
, &v
);
2320 r
= efc_perform_command(private, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
2326 * Returns a bit field (at most 64) of locked regions within a page.
2327 * @param private info about the bank
2328 * @param v where to store locked bits
2330 static int flashd_get_lock_bits(struct sam3_bank_private
*private, uint32_t *v
)
2334 r
= efc_perform_command(private, AT91C_EFC_FCMD_GLB
, 0, NULL
);
2336 r
= efc_get_result(private, v
);
2337 LOG_DEBUG("End: %d", r
);
2342 * Unlocks all the regions in the given address range.
2343 * @param private info about the bank
2344 * @param start_sector first sector to unlock
2345 * @param end_sector last (inclusive) to unlock
2348 static int flashd_unlock(struct sam3_bank_private
*private,
2349 unsigned start_sector
,
2350 unsigned end_sector
)
2355 uint32_t pages_per_sector
;
2357 pages_per_sector
= private->sector_size
/ private->page_size
;
2359 /* Unlock all pages */
2360 while (start_sector
<= end_sector
) {
2361 pg
= start_sector
* pages_per_sector
;
2363 r
= efc_perform_command(private, AT91C_EFC_FCMD_CLB
, pg
, &status
);
2374 * @param private - info about the bank
2375 * @param start_sector - first sector to lock
2376 * @param end_sector - last sector (inclusive) to lock
2378 static int flashd_lock(struct sam3_bank_private
*private,
2379 unsigned start_sector
,
2380 unsigned end_sector
)
2384 uint32_t pages_per_sector
;
2387 pages_per_sector
= private->sector_size
/ private->page_size
;
2389 /* Lock all pages */
2390 while (start_sector
<= end_sector
) {
2391 pg
= start_sector
* pages_per_sector
;
2393 r
= efc_perform_command(private, AT91C_EFC_FCMD_SLB
, pg
, &status
);
2401 /****** END SAM3 CODE ********/
2403 /* begin helpful debug code */
2404 /* print the fieldname, the field value, in dec & hex, and return field value */
2405 static uint32_t sam3_reg_fieldname(struct sam3_chip
*chip
,
2406 const char *regname
,
2415 /* extract the field */
2417 v
= v
& ((1 << width
)-1);
2426 /* show the basics */
2427 LOG_USER_N("\t%*s: %*" PRIu32
" [0x%0*" PRIx32
"] ",
2428 REG_NAME_WIDTH
, regname
,
2434 static const char _unknown
[] = "unknown";
2435 static const char *const eproc_names
[] = {
2439 "Cortex-M3", /* 3 */
2441 "arm926ejs", /* 5 */
2454 #define nvpsize2 nvpsize /* these two tables are identical */
2455 static const char *const nvpsize
[] = {
2458 "16K bytes", /* 2 */
2459 "32K bytes", /* 3 */
2461 "64K bytes", /* 5 */
2463 "128K bytes", /* 7 */
2465 "256K bytes", /* 9 */
2466 "512K bytes", /* 10 */
2468 "1024K bytes", /* 12 */
2470 "2048K bytes", /* 14 */
2474 static const char *const sramsize
[] = {
2475 "48K Bytes", /* 0 */
2479 "112K Bytes", /* 4 */
2481 "80K Bytes", /* 6 */
2482 "160K Bytes", /* 7 */
2484 "16K Bytes", /* 9 */
2485 "32K Bytes", /* 10 */
2486 "64K Bytes", /* 11 */
2487 "128K Bytes", /* 12 */
2488 "256K Bytes", /* 13 */
2489 "96K Bytes", /* 14 */
2490 "512K Bytes", /* 15 */
2494 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
2495 { 0x19, "AT91SAM9xx Series" },
2496 { 0x29, "AT91SAM9XExx Series" },
2497 { 0x34, "AT91x34 Series" },
2498 { 0x37, "CAP7 Series" },
2499 { 0x39, "CAP9 Series" },
2500 { 0x3B, "CAP11 Series" },
2501 { 0x40, "AT91x40 Series" },
2502 { 0x42, "AT91x42 Series" },
2503 { 0x55, "AT91x55 Series" },
2504 { 0x60, "AT91SAM7Axx Series" },
2505 { 0x61, "AT91SAM7AQxx Series" },
2506 { 0x63, "AT91x63 Series" },
2507 { 0x70, "AT91SAM7Sxx Series" },
2508 { 0x71, "AT91SAM7XCxx Series" },
2509 { 0x72, "AT91SAM7SExx Series" },
2510 { 0x73, "AT91SAM7Lxx Series" },
2511 { 0x75, "AT91SAM7Xxx Series" },
2512 { 0x76, "AT91SAM7SLxx Series" },
2513 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2514 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2515 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2516 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2517 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2518 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2519 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2520 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2521 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2522 { 0x92, "AT91x92 Series" },
2523 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2524 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2525 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2526 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2527 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2528 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2529 { 0xA5, "ATSAM5A" },
2530 { 0xF0, "AT75Cxx Series" },
2534 static const char *const nvptype
[] = {
2536 "romless or onchip flash", /* 1 */
2537 "embedded flash memory",/* 2 */
2538 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2539 "sram emulating flash", /* 4 */
2545 static const char *_yes_or_no(uint32_t v
)
2553 static const char *const _rc_freq
[] = {
2554 "4 MHz", "8 MHz", "12 MHz", "reserved"
2557 static void sam3_explain_ckgr_mor(struct sam3_chip
*chip
)
2562 v
= sam3_reg_fieldname(chip
, "MOSCXTEN", chip
->cfg
.CKGR_MOR
, 0, 1);
2563 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
2564 v
= sam3_reg_fieldname(chip
, "MOSCXTBY", chip
->cfg
.CKGR_MOR
, 1, 1);
2565 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
2566 rcen
= sam3_reg_fieldname(chip
, "MOSCRCEN", chip
->cfg
.CKGR_MOR
, 3, 1);
2567 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
2568 v
= sam3_reg_fieldname(chip
, "MOSCRCF", chip
->cfg
.CKGR_MOR
, 4, 3);
2569 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
2571 chip
->cfg
.rc_freq
= 0;
2575 chip
->cfg
.rc_freq
= 0;
2578 chip
->cfg
.rc_freq
= 4 * 1000 * 1000;
2581 chip
->cfg
.rc_freq
= 8 * 1000 * 1000;
2584 chip
->cfg
.rc_freq
= 12 * 1000 * 1000;
2589 v
= sam3_reg_fieldname(chip
, "MOSCXTST", chip
->cfg
.CKGR_MOR
, 8, 8);
2590 LOG_USER("(startup clks, time= %f uSecs)",
2591 ((float)(v
* 1000000)) / ((float)(chip
->cfg
.slow_freq
)));
2592 v
= sam3_reg_fieldname(chip
, "MOSCSEL", chip
->cfg
.CKGR_MOR
, 24, 1);
2593 LOG_USER("(mainosc source: %s)",
2594 v
? "external xtal" : "internal RC");
2596 v
= sam3_reg_fieldname(chip
, "CFDEN", chip
->cfg
.CKGR_MOR
, 25, 1);
2597 LOG_USER("(clock failure enabled: %s)",
2601 static void sam3_explain_chipid_cidr(struct sam3_chip
*chip
)
2607 sam3_reg_fieldname(chip
, "Version", chip
->cfg
.CHIPID_CIDR
, 0, 5);
2610 v
= sam3_reg_fieldname(chip
, "EPROC", chip
->cfg
.CHIPID_CIDR
, 5, 3);
2611 LOG_USER("%s", eproc_names
[v
]);
2613 v
= sam3_reg_fieldname(chip
, "NVPSIZE", chip
->cfg
.CHIPID_CIDR
, 8, 4);
2614 LOG_USER("%s", nvpsize
[v
]);
2616 v
= sam3_reg_fieldname(chip
, "NVPSIZE2", chip
->cfg
.CHIPID_CIDR
, 12, 4);
2617 LOG_USER("%s", nvpsize2
[v
]);
2619 v
= sam3_reg_fieldname(chip
, "SRAMSIZE", chip
->cfg
.CHIPID_CIDR
, 16, 4);
2620 LOG_USER("%s", sramsize
[v
]);
2622 v
= sam3_reg_fieldname(chip
, "ARCH", chip
->cfg
.CHIPID_CIDR
, 20, 8);
2624 for (x
= 0; archnames
[x
].name
; x
++) {
2625 if (v
== archnames
[x
].value
) {
2626 cp
= archnames
[x
].name
;
2633 v
= sam3_reg_fieldname(chip
, "NVPTYP", chip
->cfg
.CHIPID_CIDR
, 28, 3);
2634 LOG_USER("%s", nvptype
[v
]);
2636 v
= sam3_reg_fieldname(chip
, "EXTID", chip
->cfg
.CHIPID_CIDR
, 31, 1);
2637 LOG_USER("(exists: %s)", _yes_or_no(v
));
2640 static void sam3_explain_ckgr_mcfr(struct sam3_chip
*chip
)
2644 v
= sam3_reg_fieldname(chip
, "MAINFRDY", chip
->cfg
.CKGR_MCFR
, 16, 1);
2645 LOG_USER("(main ready: %s)", _yes_or_no(v
));
2647 v
= sam3_reg_fieldname(chip
, "MAINF", chip
->cfg
.CKGR_MCFR
, 0, 16);
2649 v
= (v
* chip
->cfg
.slow_freq
) / 16;
2650 chip
->cfg
.mainosc_freq
= v
;
2652 LOG_USER("(%3.03f Mhz (%" PRIu32
".%03" PRIu32
"khz slowclk)",
2654 (uint32_t)(chip
->cfg
.slow_freq
/ 1000),
2655 (uint32_t)(chip
->cfg
.slow_freq
% 1000));
2658 static void sam3_explain_ckgr_plla(struct sam3_chip
*chip
)
2660 uint32_t mula
, diva
;
2662 diva
= sam3_reg_fieldname(chip
, "DIVA", chip
->cfg
.CKGR_PLLAR
, 0, 8);
2664 mula
= sam3_reg_fieldname(chip
, "MULA", chip
->cfg
.CKGR_PLLAR
, 16, 11);
2666 chip
->cfg
.plla_freq
= 0;
2668 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2670 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2671 else if (diva
>= 1) {
2672 chip
->cfg
.plla_freq
= (chip
->cfg
.mainosc_freq
* (mula
+ 1) / diva
);
2673 LOG_USER("\tPLLA Freq: %3.03f MHz",
2674 _tomhz(chip
->cfg
.plla_freq
));
2678 static void sam3_explain_mckr(struct sam3_chip
*chip
)
2680 uint32_t css
, pres
, fin
= 0;
2682 const char *cp
= NULL
;
2684 css
= sam3_reg_fieldname(chip
, "CSS", chip
->cfg
.PMC_MCKR
, 0, 2);
2687 fin
= chip
->cfg
.slow_freq
;
2691 fin
= chip
->cfg
.mainosc_freq
;
2695 fin
= chip
->cfg
.plla_freq
;
2699 if (chip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2700 fin
= 480 * 1000 * 1000;
2704 cp
= "upll (*ERROR* UPLL is disabled)";
2712 LOG_USER("%s (%3.03f Mhz)",
2715 pres
= sam3_reg_fieldname(chip
, "PRES", chip
->cfg
.PMC_MCKR
, 4, 3);
2716 switch (pres
& 0x07) {
2719 cp
= "selected clock";
2753 LOG_USER("(%s)", cp
);
2755 /* sam3 has a *SINGLE* clock - */
2756 /* other at91 series parts have divisors for these. */
2757 chip
->cfg
.cpu_freq
= fin
;
2758 chip
->cfg
.mclk_freq
= fin
;
2759 chip
->cfg
.fclk_freq
= fin
;
2760 LOG_USER("\t\tResult CPU Freq: %3.03f",
2765 static struct sam3_chip
*target2sam3(struct target
*target
)
2767 struct sam3_chip
*chip
;
2772 chip
= all_sam3_chips
;
2774 if (chip
->target
== target
)
2775 break; /* return below */
2783 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg
*cfg
, const struct sam3_reg_list
*list
)
2785 /* this function exists to help */
2786 /* keep funky offsetof() errors */
2787 /* and casting from causing bugs */
2789 /* By using prototypes - we can detect what would */
2790 /* be casting errors. */
2792 return (uint32_t *)(void *)(((char *)(cfg
)) + list
->struct_offset
);
2796 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2798 NAME), # NAME, FUNC }
2799 static const struct sam3_reg_list sam3_all_regs
[] = {
2800 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
2801 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
2802 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
2803 SAM3_ENTRY(CKGR_UCKR
, NULL
),
2804 SAM3_ENTRY(PMC_FSMR
, NULL
),
2805 SAM3_ENTRY(PMC_FSPR
, NULL
),
2806 SAM3_ENTRY(PMC_IMR
, NULL
),
2807 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
2808 SAM3_ENTRY(PMC_PCK0
, NULL
),
2809 SAM3_ENTRY(PMC_PCK1
, NULL
),
2810 SAM3_ENTRY(PMC_PCK2
, NULL
),
2811 SAM3_ENTRY(PMC_PCSR
, NULL
),
2812 SAM3_ENTRY(PMC_SCSR
, NULL
),
2813 SAM3_ENTRY(PMC_SR
, NULL
),
2814 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
2815 SAM3_ENTRY(CHIPID_CIDR2
, sam3_explain_chipid_cidr
),
2816 SAM3_ENTRY(CHIPID_EXID
, NULL
),
2817 SAM3_ENTRY(CHIPID_EXID2
, NULL
),
2818 /* TERMINATE THE LIST */
2823 static struct sam3_bank_private
*get_sam3_bank_private(struct flash_bank
*bank
)
2825 return bank
->driver_priv
;
2829 * Given a pointer to where it goes in the structure,
2830 * determine the register name, address from the all registers table.
2832 static const struct sam3_reg_list
*sam3_get_reg(struct sam3_chip
*chip
, uint32_t *goes_here
)
2834 const struct sam3_reg_list
*reg
;
2836 reg
= &(sam3_all_regs
[0]);
2840 /* calculate where this one go.. */
2841 /* it is "possibly" this register. */
2843 possible
= ((uint32_t *)(void *)(((char *)(&(chip
->cfg
))) + reg
->struct_offset
));
2845 /* well? Is it this register */
2846 if (possible
== goes_here
) {
2854 /* This is *TOTAL*PANIC* - we are totally screwed. */
2855 LOG_ERROR("INVALID SAM3 REGISTER");
2859 static int sam3_read_this_reg(struct sam3_chip
*chip
, uint32_t *goes_here
)
2861 const struct sam3_reg_list
*reg
;
2864 reg
= sam3_get_reg(chip
, goes_here
);
2868 r
= target_read_u32(chip
->target
, reg
->address
, goes_here
);
2869 if (r
!= ERROR_OK
) {
2870 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2871 reg
->name
, (unsigned)(reg
->address
), r
);
2876 static int sam3_read_all_regs(struct sam3_chip
*chip
)
2879 const struct sam3_reg_list
*reg
;
2881 reg
= &(sam3_all_regs
[0]);
2883 r
= sam3_read_this_reg(chip
,
2884 sam3_get_reg_ptr(&(chip
->cfg
), reg
));
2885 if (r
!= ERROR_OK
) {
2886 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2887 reg
->name
, ((unsigned)(reg
->address
)), r
);
2893 /* Chip identification register
2895 * Unfortunately, the chip identification register is not at
2896 * a constant address across all of the SAM3 series'. As a
2897 * consequence, a simple heuristic is used to find where it's
2900 * If the contents at the first address is zero, then we know
2901 * that the second address is where the chip id register is.
2902 * We can deduce this because for those SAM's that have the
2903 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2904 * located in the memory map of the Power Management Controller
2905 * (PMC). Furthermore, the address is not used by the PMC.
2906 * So when read, the memory controller returns zero.*/
2907 if (chip
->cfg
.CHIPID_CIDR
== 0) {
2908 /*Put the correct CIDR and EXID values in the chip structure */
2909 chip
->cfg
.CHIPID_CIDR
= chip
->cfg
.CHIPID_CIDR2
;
2910 chip
->cfg
.CHIPID_EXID
= chip
->cfg
.CHIPID_EXID2
;
2915 static int sam3_get_info(struct sam3_chip
*chip
)
2917 const struct sam3_reg_list
*reg
;
2920 reg
= &(sam3_all_regs
[0]);
2922 /* display all regs */
2923 LOG_DEBUG("Start: %s", reg
->name
);
2924 regval
= *sam3_get_reg_ptr(&(chip
->cfg
), reg
);
2925 LOG_USER("%*s: [0x%08" PRIx32
"] -> 0x%08" PRIx32
,
2930 if (reg
->explain_func
)
2931 (*(reg
->explain_func
))(chip
);
2932 LOG_DEBUG("End: %s", reg
->name
);
2935 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(chip
->cfg
.rc_freq
));
2936 LOG_USER(" mainosc: %3.03f MHz", _tomhz(chip
->cfg
.mainosc_freq
));
2937 LOG_USER(" plla: %3.03f MHz", _tomhz(chip
->cfg
.plla_freq
));
2938 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(chip
->cfg
.cpu_freq
));
2939 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(chip
->cfg
.mclk_freq
));
2941 LOG_USER(" UniqueId: 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
,
2942 chip
->cfg
.unique_id
[0],
2943 chip
->cfg
.unique_id
[1],
2944 chip
->cfg
.unique_id
[2],
2945 chip
->cfg
.unique_id
[3]);
2950 static int sam3_protect_check(struct flash_bank
*bank
)
2955 struct sam3_bank_private
*private;
2958 if (bank
->target
->state
!= TARGET_HALTED
) {
2959 LOG_ERROR("Target not halted");
2960 return ERROR_TARGET_NOT_HALTED
;
2963 private = get_sam3_bank_private(bank
);
2965 LOG_ERROR("no private for this bank?");
2968 if (!(private->probed
))
2969 return ERROR_FLASH_BANK_NOT_PROBED
;
2971 r
= flashd_get_lock_bits(private, &v
);
2972 if (r
!= ERROR_OK
) {
2973 LOG_DEBUG("Failed: %d", r
);
2977 for (x
= 0; x
< private->nsectors
; x
++)
2978 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
2983 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
2985 struct sam3_chip
*chip
;
2987 chip
= all_sam3_chips
;
2989 /* is this an existing chip? */
2991 if (chip
->target
== bank
->target
)
2997 /* this is a *NEW* chip */
2998 chip
= calloc(1, sizeof(struct sam3_chip
));
3000 LOG_ERROR("NO RAM!");
3003 chip
->target
= bank
->target
;
3004 /* insert at head */
3005 chip
->next
= all_sam3_chips
;
3006 all_sam3_chips
= chip
;
3007 chip
->target
= bank
->target
;
3008 /* assumption is this runs at 32khz */
3009 chip
->cfg
.slow_freq
= 32768;
3010 chip
->probed
= false;
3013 switch (bank
->base
) {
3015 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
3016 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3017 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3018 ((unsigned int)(bank
->base
)),
3019 ((unsigned int)(FLASH_BANK0_BASE_U
)),
3020 ((unsigned int)(FLASH_BANK1_BASE_U
)),
3021 ((unsigned int)(FLASH_BANK_BASE_S
)),
3022 ((unsigned int)(FLASH_BANK_BASE_N
)),
3023 ((unsigned int)(FLASH_BANK0_BASE_AX
)),
3024 ((unsigned int)(FLASH_BANK1_BASE_256K_AX
)),
3025 ((unsigned int)(FLASH_BANK1_BASE_512K_AX
)));
3028 /* at91sam3s and at91sam3n series only has bank 0*/
3029 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3030 case FLASH_BANK_BASE_S
:
3031 case FLASH_BANK0_BASE_U
:
3032 bank
->driver_priv
= &(chip
->details
.bank
[0]);
3033 bank
->bank_number
= 0;
3034 chip
->details
.bank
[0].chip
= chip
;
3035 chip
->details
.bank
[0].bank
= bank
;
3038 /* Bank 1 of at91sam3u or at91sam3ax series */
3039 case FLASH_BANK1_BASE_U
:
3040 case FLASH_BANK1_BASE_256K_AX
:
3041 case FLASH_BANK1_BASE_512K_AX
:
3042 bank
->driver_priv
= &(chip
->details
.bank
[1]);
3043 bank
->bank_number
= 1;
3044 chip
->details
.bank
[1].chip
= chip
;
3045 chip
->details
.bank
[1].bank
= bank
;
3049 /* we initialize after probing. */
3054 * Remove all chips from the internal list without distinguishing which one
3055 * is owned by this bank. This simplification works only for one shot
3056 * deallocation like current flash_free_all_banks()
3058 static void sam3_free_driver_priv(struct flash_bank
*bank
)
3060 struct sam3_chip
*chip
= all_sam3_chips
;
3062 struct sam3_chip
*next
= chip
->next
;
3066 all_sam3_chips
= NULL
;
3069 static int sam3_get_details(struct sam3_bank_private
*private)
3071 const struct sam3_chip_details
*details
;
3072 struct sam3_chip
*chip
;
3073 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
3077 details
= all_sam3_details
;
3078 while (details
->name
) {
3079 /* Compare cidr without version bits */
3080 if (((details
->chipid_cidr
^ private->chip
->cfg
.CHIPID_CIDR
) & 0xFFFFFFE0) == 0)
3085 if (!details
->name
) {
3086 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
3087 (unsigned int)(private->chip
->cfg
.CHIPID_CIDR
));
3088 /* Help the victim, print details about the chip */
3089 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32
" decodes as follows",
3090 private->chip
->cfg
.CHIPID_CIDR
);
3091 sam3_explain_chipid_cidr(private->chip
);
3095 /* DANGER: THERE ARE DRAGONS HERE */
3097 /* get our chip - it is going */
3098 /* to be over-written shortly */
3099 chip
= private->chip
;
3101 /* Note that, in reality: */
3103 /* private = &(chip->details.bank[0]) */
3104 /* or private = &(chip->details.bank[1]) */
3107 /* save the "bank" pointers */
3108 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++)
3109 saved_banks
[x
] = chip
->details
.bank
[x
].bank
;
3111 /* Overwrite the "details" structure. */
3112 memcpy(&(private->chip
->details
),
3114 sizeof(private->chip
->details
));
3116 /* now fix the ghosted pointers */
3117 for (x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3118 chip
->details
.bank
[x
].chip
= chip
;
3119 chip
->details
.bank
[x
].bank
= saved_banks
[x
];
3122 /* update the *BANK*SIZE* */
3128 static int _sam3_probe(struct flash_bank
*bank
, int noise
)
3131 struct sam3_bank_private
*private;
3134 LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank
->bank_number
, noise
);
3135 if (bank
->target
->state
!= TARGET_HALTED
) {
3136 LOG_ERROR("Target not halted");
3137 return ERROR_TARGET_NOT_HALTED
;
3140 private = get_sam3_bank_private(bank
);
3142 LOG_ERROR("Invalid/unknown bank number");
3146 r
= sam3_read_all_regs(private->chip
);
3151 if (private->chip
->probed
)
3152 r
= sam3_get_info(private->chip
);
3154 r
= sam3_get_details(private);
3158 /* update the flash bank size */
3159 for (unsigned int x
= 0; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3160 if (bank
->base
== private->chip
->details
.bank
[x
].base_address
) {
3161 bank
->size
= private->chip
->details
.bank
[x
].size_bytes
;
3166 if (!bank
->sectors
) {
3167 bank
->sectors
= calloc(private->nsectors
, (sizeof((bank
->sectors
)[0])));
3168 if (!bank
->sectors
) {
3169 LOG_ERROR("No memory!");
3172 bank
->num_sectors
= private->nsectors
;
3174 for (unsigned int x
= 0; x
< bank
->num_sectors
; x
++) {
3175 bank
->sectors
[x
].size
= private->sector_size
;
3176 bank
->sectors
[x
].offset
= x
* (private->sector_size
);
3177 /* mark as unknown */
3178 bank
->sectors
[x
].is_erased
= -1;
3179 bank
->sectors
[x
].is_protected
= -1;
3183 private->probed
= true;
3185 r
= sam3_protect_check(bank
);
3189 LOG_DEBUG("Bank = %d, nbanks = %d",
3190 private->bank_number
, private->chip
->details
.n_banks
);
3191 if ((private->bank_number
+ 1) == private->chip
->details
.n_banks
) {
3192 /* read unique id, */
3193 /* it appears to be associated with the *last* flash bank. */
3194 flashd_read_uid(private);
3200 static int sam3_probe(struct flash_bank
*bank
)
3202 return _sam3_probe(bank
, 1);
3205 static int sam3_auto_probe(struct flash_bank
*bank
)
3207 return _sam3_probe(bank
, 0);
3210 static int sam3_erase(struct flash_bank
*bank
, unsigned int first
,
3213 struct sam3_bank_private
*private;
3217 if (bank
->target
->state
!= TARGET_HALTED
) {
3218 LOG_ERROR("Target not halted");
3219 return ERROR_TARGET_NOT_HALTED
;
3222 r
= sam3_auto_probe(bank
);
3223 if (r
!= ERROR_OK
) {
3224 LOG_DEBUG("Here,r=%d", r
);
3228 private = get_sam3_bank_private(bank
);
3229 if (!(private->probed
))
3230 return ERROR_FLASH_BANK_NOT_PROBED
;
3232 if ((first
== 0) && ((last
+ 1) == private->nsectors
)) {
3235 return flashd_erase_entire_bank(private);
3237 LOG_INFO("sam3 auto-erases while programming (request ignored)");
3241 static int sam3_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
3244 struct sam3_bank_private
*private;
3248 if (bank
->target
->state
!= TARGET_HALTED
) {
3249 LOG_ERROR("Target not halted");
3250 return ERROR_TARGET_NOT_HALTED
;
3253 private = get_sam3_bank_private(bank
);
3254 if (!(private->probed
))
3255 return ERROR_FLASH_BANK_NOT_PROBED
;
3258 r
= flashd_lock(private, first
, last
);
3260 r
= flashd_unlock(private, first
, last
);
3261 LOG_DEBUG("End: r=%d", r
);
3267 static int sam3_page_read(struct sam3_bank_private
*private, unsigned pagenum
, uint8_t *buf
)
3272 adr
= pagenum
* private->page_size
;
3273 adr
+= private->base_address
;
3275 r
= target_read_memory(private->chip
->target
,
3277 4, /* THIS*MUST*BE* in 32bit values */
3278 private->page_size
/ 4,
3281 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3282 (unsigned int)(adr
));
3286 static int sam3_page_write(struct sam3_bank_private
*private, unsigned pagenum
, const uint8_t *buf
)
3290 uint32_t fmr
; /* EEFC Flash Mode Register */
3293 adr
= pagenum
* private->page_size
;
3294 adr
+= private->base_address
;
3296 /* Get flash mode register value */
3297 r
= target_read_u32(private->chip
->target
, private->controller_address
, &fmr
);
3299 LOG_DEBUG("Error Read failed: read flash mode register");
3301 /* Clear flash wait state field */
3304 /* set FWS (flash wait states) field in the FMR (flash mode register) */
3305 fmr
|= (private->flash_wait_states
<< 8);
3307 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
3308 r
= target_write_u32(private->bank
->target
, private->controller_address
, fmr
);
3310 LOG_DEBUG("Error Write failed: set flash mode register");
3312 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
3313 r
= target_write_memory(private->chip
->target
,
3315 4, /* THIS*MUST*BE* in 32bit values */
3316 private->page_size
/ 4,
3318 if (r
!= ERROR_OK
) {
3319 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3320 (unsigned int)(adr
));
3324 r
= efc_perform_command(private,
3325 /* send Erase & Write Page */
3331 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3332 (unsigned int)(adr
));
3333 if (status
& (1 << 2)) {
3334 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
3337 if (status
& (1 << 1)) {
3338 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
3344 static int sam3_write(struct flash_bank
*bank
,
3345 const uint8_t *buffer
,
3353 unsigned page_offset
;
3354 struct sam3_bank_private
*private;
3355 uint8_t *pagebuffer
;
3357 /* in case we bail further below, set this to null */
3360 /* ignore dumb requests */
3366 if (bank
->target
->state
!= TARGET_HALTED
) {
3367 LOG_ERROR("Target not halted");
3368 r
= ERROR_TARGET_NOT_HALTED
;
3372 private = get_sam3_bank_private(bank
);
3373 if (!(private->probed
)) {
3374 r
= ERROR_FLASH_BANK_NOT_PROBED
;
3378 if ((offset
+ count
) > private->size_bytes
) {
3379 LOG_ERROR("Flash write error - past end of bank");
3380 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3381 (unsigned int)(offset
),
3382 (unsigned int)(count
),
3383 (unsigned int)(private->size_bytes
));
3388 pagebuffer
= malloc(private->page_size
);
3390 LOG_ERROR("No memory for %d Byte page buffer", (int)(private->page_size
));
3395 /* what page do we start & end in? */
3396 page_cur
= offset
/ private->page_size
;
3397 page_end
= (offset
+ count
- 1) / private->page_size
;
3399 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
3400 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
3402 /* Special case: all one page */
3405 /* (1) non-aligned start */
3406 /* (2) body pages */
3407 /* (3) non-aligned end. */
3409 /* Handle special case - all one page. */
3410 if (page_cur
== page_end
) {
3411 LOG_DEBUG("Special case, all in one page");
3412 r
= sam3_page_read(private, page_cur
, pagebuffer
);
3416 page_offset
= (offset
& (private->page_size
-1));
3417 memcpy(pagebuffer
+ page_offset
,
3421 r
= sam3_page_write(private, page_cur
, pagebuffer
);
3428 /* non-aligned start */
3429 page_offset
= offset
& (private->page_size
- 1);
3431 LOG_DEBUG("Not-Aligned start");
3432 /* read the partial */
3433 r
= sam3_page_read(private, page_cur
, pagebuffer
);
3437 /* over-write with new data */
3438 n
= (private->page_size
- page_offset
);
3439 memcpy(pagebuffer
+ page_offset
,
3443 r
= sam3_page_write(private, page_cur
, pagebuffer
);
3453 /* By checking that offset is correct here, we also
3454 fix a clang warning */
3455 assert(offset
% private->page_size
== 0);
3457 /* intermediate large pages */
3458 /* also - the final *terminal* */
3459 /* if that terminal page is a full page */
3460 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3461 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
3463 while ((page_cur
< page_end
) &&
3464 (count
>= private->page_size
)) {
3465 r
= sam3_page_write(private, page_cur
, buffer
);
3468 count
-= private->page_size
;
3469 buffer
+= private->page_size
;
3473 /* terminal partial page? */
3475 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
3476 /* we have a partial page */
3477 r
= sam3_page_read(private, page_cur
, pagebuffer
);
3480 /* data goes at start */
3481 memcpy(pagebuffer
, buffer
, count
);
3482 r
= sam3_page_write(private, page_cur
, pagebuffer
);
3493 COMMAND_HANDLER(sam3_handle_info_command
)
3495 struct sam3_chip
*chip
;
3496 chip
= get_current_sam3(CMD
);
3503 /* bank0 must exist before we can do anything */
3504 if (!chip
->details
.bank
[0].bank
) {
3508 "Please define bank %d via command: flash bank %s ... ",
3510 at91sam3_flash
.name
);
3514 /* if bank 0 is not probed, then probe it */
3515 if (!(chip
->details
.bank
[0].probed
)) {
3516 r
= sam3_auto_probe(chip
->details
.bank
[0].bank
);
3520 /* above guarantees the "chip details" structure is valid */
3521 /* and thus, bank private areas are valid */
3522 /* and we have a SAM3 chip, what a concept! */
3524 /* auto-probe other banks, 0 done above */
3525 for (x
= 1; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3526 /* skip banks not present */
3527 if (!(chip
->details
.bank
[x
].present
))
3530 if (!chip
->details
.bank
[x
].bank
)
3533 if (chip
->details
.bank
[x
].probed
)
3536 r
= sam3_auto_probe(chip
->details
.bank
[x
].bank
);
3541 r
= sam3_get_info(chip
);
3542 if (r
!= ERROR_OK
) {
3543 LOG_DEBUG("Sam3Info, Failed %d", r
);
3550 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
3554 struct sam3_chip
*chip
;
3556 chip
= get_current_sam3(CMD
);
3560 if (chip
->target
->state
!= TARGET_HALTED
) {
3561 LOG_ERROR("sam3 - target not halted");
3562 return ERROR_TARGET_NOT_HALTED
;
3565 if (!chip
->details
.bank
[0].bank
) {
3566 command_print(CMD
, "Bank0 must be defined first via: flash bank %s ...",
3567 at91sam3_flash
.name
);
3570 if (!chip
->details
.bank
[0].probed
) {
3571 r
= sam3_auto_probe(chip
->details
.bank
[0].bank
);
3578 return ERROR_COMMAND_SYNTAX_ERROR
;
3585 if ((strcmp(CMD_ARGV
[0], "show") == 0) && (strcmp(CMD_ARGV
[1], "all") == 0))
3589 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3595 if (strcmp("show", CMD_ARGV
[0]) == 0) {
3599 for (x
= 0; x
< chip
->details
.n_gpnvms
; x
++) {
3600 r
= flashd_get_gpnvm(&(chip
->details
.bank
[0]), x
, &v
);
3603 command_print(CMD
, "sam3-gpnvm%u: %u", x
, v
);
3607 if ((who
>= 0) && (((unsigned)(who
)) < chip
->details
.n_gpnvms
)) {
3608 r
= flashd_get_gpnvm(&(chip
->details
.bank
[0]), who
, &v
);
3610 command_print(CMD
, "sam3-gpnvm%u: %u", who
, v
);
3613 command_print(CMD
, "sam3-gpnvm invalid GPNVM: %u", who
);
3614 return ERROR_COMMAND_SYNTAX_ERROR
;
3619 command_print(CMD
, "Missing GPNVM number");
3620 return ERROR_COMMAND_SYNTAX_ERROR
;
3623 if (strcmp("set", CMD_ARGV
[0]) == 0)
3624 r
= flashd_set_gpnvm(&(chip
->details
.bank
[0]), who
);
3625 else if ((strcmp("clr", CMD_ARGV
[0]) == 0) ||
3626 (strcmp("clear", CMD_ARGV
[0]) == 0)) /* quietly accept both */
3627 r
= flashd_clr_gpnvm(&(chip
->details
.bank
[0]), who
);
3629 command_print(CMD
, "Unknown command: %s", CMD_ARGV
[0]);
3630 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3635 COMMAND_HANDLER(sam3_handle_slowclk_command
)
3637 struct sam3_chip
*chip
;
3639 chip
= get_current_sam3(CMD
);
3651 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3653 /* absurd slow clock of 200Khz? */
3654 command_print(CMD
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
3655 return ERROR_COMMAND_SYNTAX_ERROR
;
3657 chip
->cfg
.slow_freq
= v
;
3662 command_print(CMD
, "Too many parameters");
3663 return ERROR_COMMAND_SYNTAX_ERROR
;
3665 command_print(CMD
, "Slowclk freq: %d.%03dkhz",
3666 (int)(chip
->cfg
.slow_freq
/ 1000),
3667 (int)(chip
->cfg
.slow_freq
% 1000));
3671 static const struct command_registration at91sam3_exec_command_handlers
[] = {
3674 .handler
= sam3_handle_gpnvm_command
,
3675 .mode
= COMMAND_EXEC
,
3676 .usage
= "[('clr'|'set'|'show') bitnum]",
3677 .help
= "Without arguments, shows all bits in the gpnvm "
3678 "register. Otherwise, clears, sets, or shows one "
3679 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3683 .handler
= sam3_handle_info_command
,
3684 .mode
= COMMAND_EXEC
,
3685 .help
= "Print information about the current at91sam3 chip "
3686 "and its flash configuration.",
3691 .handler
= sam3_handle_slowclk_command
,
3692 .mode
= COMMAND_EXEC
,
3693 .usage
= "[clock_hz]",
3694 .help
= "Display or set the slowclock frequency "
3695 "(default 32768 Hz).",
3697 COMMAND_REGISTRATION_DONE
3699 static const struct command_registration at91sam3_command_handlers
[] = {
3702 .mode
= COMMAND_ANY
,
3703 .help
= "at91sam3 flash command group",
3705 .chain
= at91sam3_exec_command_handlers
,
3707 COMMAND_REGISTRATION_DONE
3710 const struct flash_driver at91sam3_flash
= {
3712 .commands
= at91sam3_command_handlers
,
3713 .flash_bank_command
= sam3_flash_bank_command
,
3714 .erase
= sam3_erase
,
3715 .protect
= sam3_protect
,
3716 .write
= sam3_write
,
3717 .read
= default_flash_read
,
3718 .probe
= sam3_probe
,
3719 .auto_probe
= sam3_auto_probe
,
3720 .erase_check
= default_flash_blank_check
,
3721 .protect_check
= sam3_protect_check
,
3722 .free_driver_priv
= sam3_free_driver_priv
,
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