target/xtensa: avoid IHI for writes to non-executable memory

[openocd.git] / tcl / target / stm32f0x.cfg

diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index b8c0de94cfedb79546f470d576145d2245c6a434..5b8954eb214c6a2274c4885b8edc68b95fc71bdd 100644 (file)
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # script for stm32f0x family
 
 #
@@ -22,6 +24,14 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x1000
 }
 
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+       set _FLASH_SIZE $FLASH_SIZE
+} else {
+       # autodetect size
+       set _FLASH_SIZE 0
+}
+
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
@@ -41,12 +51,12 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 
 # flash size will be probed
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
 
 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 reset_config srst_nogate
 
@@ -58,7 +68,7 @@ if {![using_hla]} {
 
 proc stm32f0x_default_reset_start {} {
        # Reset clock is HSI (8 MHz)
-       adapter_khz 1000
+       adapter speed 1000
 }
 
 proc stm32f0x_default_examine_end {} {
@@ -78,7 +88,7 @@ proc stm32f0x_default_reset_init {} {
        mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
 
        # Boost JTAG frequency
-       adapter_khz 8000
+       adapter speed 8000
 }
 
 # Default hooks