+#define EJTAG_IMP_NODMA (1 << 14)
+/* v2.0 - 11:13 external PC trace. Trace PC Width. */
+/* v2.0 - 8:10 external PC trace. PCST Width and DCLK Division Factor */
+#define EJTAG_V20_IMP_NOPB (1 << 7) /* no processor breaks */
+#define EJTAG_V20_IMP_NODB (1 << 6) /* no data breaks */
+#define EJTAG_V20_IMP_NOIB (1 << 5) /* no instruction breaks implemented */
+/* v2.0 - 1:4 Number of Break Channels. */
+#define EJTAG_V20_IMP_BCHANNELS_MASK 0xf
+#define EJTAG_V20_IMP_BCHANNELS_SHIFT 1
+#define EJTAG_DCR_MIPS64 (1 << 0)
+
+/* Debug Control Register DCR */
+#define EJTAG_DCR 0xFF300000
+#define EJTAG_DCR_ENM (1 << 29)
+#define EJTAG_DCR_DB (1 << 17)
+#define EJTAG_DCR_IB (1 << 16)
+#define EJTAG_DCR_INTE (1 << 4)
+#define EJTAG_DCR_MP (1 << 2)
+
+/* breakpoint support */
+/* EJTAG_V20_* was tested on Broadcom BCM7401
+ * and may or will differ with other hardware. For example EZ4021-FC. */
+#define EJTAG_V20_IBS 0xFF300004
+#define EJTAG_V20_IBA0 0xFF300100
+#define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */
+#define EJTAG_V20_IBM_OFFS 0x8
+#define EJTAG_V20_IBAn_STEP 0x10 /* Offset for next channel */
+#define EJTAG_V20_DBS 0xFF300008
+#define EJTAG_V20_DBA0 0xFF300200
+#define EJTAG_V20_DBC_OFFS 0x4
+#define EJTAG_V20_DBM_OFFS 0x8
+#define EJTAG_V20_DBV_OFFS 0xc
+#define EJTAG_V20_DBAn_STEP 0x10
+
+#define EJTAG_V25_IBS 0xFF301000
+#define EJTAG_V25_IBA0 0xFF301100
+#define EJTAG_V25_IBM_OFFS 0x8
+#define EJTAG_V25_IBASID_OFFS 0x10
+#define EJTAG_V25_IBC_OFFS 0x18
+#define EJTAG_V25_IBAn_STEP 0x100
+#define EJTAG_V25_DBS 0xFF302000
+#define EJTAG_V25_DBA0 0xFF302100
+#define EJTAG_V25_DBM_OFFS 0x8
+#define EJTAG_V25_DBASID_OFFS 0x10
+#define EJTAG_V25_DBC_OFFS 0x18
+#define EJTAG_V25_DBV_OFFS 0x20
+#define EJTAG_V25_DBAn_STEP 0x100
+
+#define EJTAG_DBCn_NOSB (1 << 13)
+#define EJTAG_DBCn_NOLB (1 << 12)
+#define EJTAG_DBCn_BLM_MASK 0xff
+#define EJTAG_DBCn_BLM_SHIFT 4
+#define EJTAG_DBCn_BE (1 << 0)