tcl/target/xilinx_zynqmp.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # target configuration for
   5 # Xilinx ZynqMP (UltraScale+ / A53)
   6 #
   7 if { [info exists CHIPNAME] } {
   8     set _CHIPNAME $CHIPNAME
   9 } else {
  10     set _CHIPNAME uscale
  11 }
  12
  13 #
  14 # DAP tap (Quard core A53)
  15 #
  16 if { [info exists DAP_TAPID] } {
  17     set _DAP_TAPID $DAP_TAPID
  18 } else {
  19     set _DAP_TAPID 0x5ba00477
  20 }
  21
  22 jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
  23 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
  24
  25 #
  26 # PS tap (UltraScale+)
  27 #
  28 if { [info exists PS_TAPID] } {
  29     set _PS_TAPID $PS_TAPID
  30     jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
  31 } else {
  32     # FPGA Programmable logic. Values take from Table 39-1 in UG1085:
  33     jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \
  34         -expected-id 0x04711093 \
  35         -expected-id 0x04710093 \
  36         -expected-id 0x04721093 \
  37         -expected-id 0x04720093 \
  38         -expected-id 0x04739093 \
  39         -expected-id 0x04730093 \
  40         -expected-id 0x04738093 \
  41         -expected-id 0x04740093 \
  42         -expected-id 0x04750093 \
  43         -expected-id 0x04759093 \
  44         -expected-id 0x04758093
  45 }
  46
  47 set jtag_configured 0
  48
  49 jtag configure $_CHIPNAME.ps -event setup {
  50     global _CHIPNAME
  51     global jtag_configured
  52
  53     if { $jtag_configured == 0 } {
  54         # add the DAP tap to the chain
  55         # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924
  56         irscan $_CHIPNAME.ps 0x824
  57         drscan $_CHIPNAME.ps 32 0x00000003
  58         runtest 100
  59
  60         # setup event will be re-entered through jtag arp_init
  61         # break the recursion
  62         set jtag_configured 1
  63         # re-initialized the jtag chain
  64         jtag arp_init
  65     }
  66 }
  67
  68 set _TARGETNAME $_CHIPNAME.a53
  69 set _CTINAME $_CHIPNAME.cti
  70 set _smp_command ""
  71
  72 set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
  73 set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
  74 set _cores 4
  75
  76 for { set _core 0 } { $_core < $_cores } { incr _core } {
  77
  78     cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
  79         -baseaddr [lindex $CTIBASE $_core]
  80
  81     set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
  82         -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
  83
  84     if { $_core != 0 } {
  85         # non-boot core examination may fail
  86         set _command "$_command -defer-examine"
  87         set _smp_command "$_smp_command $_TARGETNAME.$_core"
  88     } else {
  89         set _command "$_command -rtos hwthread"
  90         set _smp_command "target smp $_TARGETNAME.$_core"
  91     }
  92
  93     eval $_command
  94 }
  95
  96 target create uscale.axi mem_ap -dap uscale.dap -ap-num 0
  97
  98 eval $_smp_command
  99 targets $_TARGETNAME.0
 100
 101 proc core_up { args } {
 102     global _TARGETNAME
 103     foreach core $args {
 104         $_TARGETNAME.$core arp_examine
 105     }
 106 }
 107
 108 proc BIT {n} {
 109         return [expr {1 << $n}]
 110 }
 111
 112 set IPI_BASE                    0xff300000
 113 set IPI_PMU_0_TRIG              [expr {$IPI_BASE + 0x30000}]
 114 set IPI_PMU_0_IER               [expr {$IPI_BASE + 0x30018}]
 115 set IPI_PMU_0                                   [BIT 16]
 116
 117 set CRF_APB_BASE                0xfd1a0000
 118 set CRF_APB_RST_FPD_APU         [expr {$CRF_APB_BASE + 0x104}]
 119 set CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET       [BIT 10]
 120 set CRF_APB_RST_FPD_APU_L2_RESET                [BIT  8]
 121 set CRF_APB_RST_FPD_APU_ACPU0_RESET             [BIT  0]
 122
 123 set APU_BASE                    0xfd5c0000
 124 set APU_RVBARADDR_BASE          [expr {$APU_BASE + 0x40}]
 125
 126 set PMU_BASE                    0xffd80000
 127 set PMU_GLOBAL                  $PMU_BASE
 128 set PMU_GLOBAL_MB_SLEEP                         [BIT 16]
 129 set PMU_GLOBAL_FW_IS_PRESENT                    [BIT  4]
 130 set PMU_GLOBAL_DONT_SLEEP                       [BIT  0]
 131
 132 set PMU_RAM_BASE                0xffdc0000
 133
 134 set OCM_RAM_BASE                0xfffc0000
 135
 136 rename BIT {}
 137
 138 add_help_text halt_pmu "Halt the PMU in preparation for loading new firmware.\
 139         This should be matched with a call to resume_pmu."
 140 proc halt_pmu {} {
 141         set axi $::_CHIPNAME.axi
 142         set val [$axi read_memory $::IPI_PMU_0_IER 32 1]
 143         $axi write_memory $::IPI_PMU_0_IER 32 [expr {$val | $::IPI_PMU_0}]
 144
 145         set val [$axi read_memory $::IPI_PMU_0_TRIG 32 1]
 146         $axi write_memory $::IPI_PMU_0_TRIG 32 [expr {$val | $::IPI_PMU_0}]
 147
 148         set start [ms]
 149         while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_MB_SLEEP)} {
 150                 if {[ms] - $start > 1000} {
 151                         error "Timed out waiting for PMU to halt"
 152                 }
 153         }
 154 }
 155
 156 add_help_text resume_pmu "Resume the PMU after loading new firmware. This\
 157         should be matched with a call to halt_pmu."
 158 proc resume_pmu {} {
 159         set axi $::_CHIPNAME.axi
 160         set val [$axi read_memory $::PMU_GLOBAL 32 1]
 161         $axi write_memory $::PMU_GLOBAL 32 [expr {$val | $::PMU_GLOBAL_DONT_SLEEP}]
 162
 163         set start [ms]
 164         while {!([$axi read_memory $::PMU_GLOBAL 32 1] & $::PMU_GLOBAL_FW_IS_PRESENT)} {
 165                 if {[ms] - $start > 5000} {
 166                         error "Timed out waiting for PMU firmware"
 167                 }
 168         }
 169 }
 170
 171 add_usage_text release_apu {apu}
 172 add_help_text release_apu "Release an APU from reset. It will start executing\
 173         at RVBARADDR. You probably want resume_apu or start_apu instead."
 174 proc release_apu {apu} {
 175         set axi $::_CHIPNAME.axi
 176         set val [$axi read_memory $::CRF_APB_RST_FPD_APU 32 1]
 177         set mask [expr {
 178                 (($::CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET | \
 179                   $::CRF_APB_RST_FPD_APU_ACPU0_RESET) << $apu) | \
 180                 $::CRF_APB_RST_FPD_APU_L2_RESET
 181         }]
 182         $axi write_memory $::CRF_APB_RST_FPD_APU 32 [expr {$val & ~$mask}]
 183
 184         core_up $apu
 185         $::_TARGETNAME.$apu aarch64 dbginit
 186 }
 187
 188 proc _rvbaraddr {apu} {
 189         return [expr {$::APU_RVBARADDR_BASE + 8 * $apu}]
 190 }
 191
 192 add_usage_text resume_apu {apu addr}
 193 add_help_text resume_apu "Resume an APU at a given address."
 194 proc resume_apu {apu addr} {
 195         set addrl [expr {$addr & 0xffffffff}]
 196         set addrh [expr {$addr >> 32}]
 197         $::_CHIPNAME.axi write_memory [_rvbaraddr $apu] 32 [list $addrl $addrh]
 198
 199         release_apu $apu
 200 }
 201
 202 add_usage_text start_apu {apu}
 203 add_help_text start_apu "Start an APU and put it into an infinite loop at\
 204         RVBARADDR. This can be convenient if you just want to halt the APU\
 205         (since it won't execute anything unusual)."
 206 proc start_apu {apu} {
 207         set axi $::_CHIPNAME.axi
 208         foreach {addrl addrh} [$axi read_memory [_rvbaraddr $apu] 32 2] {
 209                 set addr [expr {($addrh << 32) | $addrl}]
 210         }
 211         # write the infinite loop instruction
 212         $axi write_memory $addr 32 0x14000000
 213
 214         release_apu $apu
 215 }
 216
 217 add_usage_text boot_pmu {image}
 218 add_help_text boot_pmu "Boot the PMU with a given firmware image, loading it\
 219         to the beginning of PMU RAM. The PMU ROM will jump to this location\
 220         after we resume it."
 221 proc boot_pmu {image} {
 222         halt_pmu
 223         echo "Info : Loading PMU firmware $image to $::PMU_RAM_BASE"
 224         load_image $image $::PMU_RAM_BASE
 225         resume_pmu
 226 }
 227
 228 add_usage_text boot_apu "image \[apu=0 \[addr=$OCM_RAM_BASE\]\]"
 229 add_help_text boot_apu "Boot an APU with a given firmware image. The default\
 230         address is the beginning of OCM RAM. Upon success, the default target\
 231         will be changed to the (running) apu."
 232 proc boot_apu [list image {apu 0} [list addr $OCM_RAM_BASE]] {
 233         start_apu $apu
 234         targets $::_TARGETNAME.$apu
 235         halt
 236
 237         echo "Info : Loading APU$apu firmware $image to $addr"
 238         load_image $image $addr
 239         resume $addr
 240 }