target/xtensa: avoid IHI for writes to non-executable memory
[openocd.git] / tcl / board / tx27_stk5.cfg
1 # SPDX-License-Identifier: GPL-2.0-or-later
2
3 # KaRo TX27 CPU Module on a StarterkitV base board
4 #
5 # http://www.karo-electronics.com/tx27.html
6 #
7 source [find target/imx27.cfg]
8
9 $_TARGETNAME configure -event gdb-attach { reset init }
10 $_TARGETNAME configure -event reset-init { tx27_init }
11
12 proc tx27_init { } {
13 # This setup puts RAM at 0xA0000000
14 # init_aipi (AIPI1.PSR0, AIPI2.PSR0, AIPI1.PSR1 and AIPI2.PSR1)
15 mww 0x10000000 0x20040304
16 mww 0x10020000 0x00000000
17 mww 0x10000004 0xDFFBFCFB
18 mww 0x10020004 0xFFFFFFFF
19
20 sleep 100
21
22 #init_max ( PORT0.MPR, #PORT0.AMPR, #PORT1.MPR, #PORT1.AMPR, #PORT2.MPR, #PORT2.AMPR)
23 mww 0x1003F000 0x00302145
24 mww 0x1003F004 0x00302145
25 mww 0x1003F100 0x00302145
26 mww 0x1003F104 0x00302145
27 mww 0x1003F200 0x00302145
28 mww 0x1003F204 0x00302145
29
30 #init_drive_strength (#DSCR3, #DSCR5, #DSCR6, #DSCR7, #DSCR8 )
31 mww 0x10027828 0x55555555
32 mww 0x10027830 0x55555555
33 mww 0x10027834 0x55555555
34 mww 0x10027838 0x00005005
35 mww 0x1002783C 0x15555555
36
37 #init_sdram_speed
38 #mww 0xD8001010 0x00000004
39 mww 0xD8001010 0x00000024
40
41 mww 0xD8001004 0x00395729
42
43 mww 0xD8001000 0x92120000
44 mww 0xA0000400 0x0
45
46 mww 0xD8001000 0xA2120000
47 mww 0xA0000000 0x0
48 mww 0xA0000000 0x0
49
50 mww 0xD8001000 0xB2120000
51 mdb 0xA0000000
52 mdb 0xA0000033
53
54 mww 0xD8001000 0x82126485
55
56 # =============================================
57 # Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz)
58 # =============================================
59 mww 0xD8002000 0x23524E80
60 mww 0xD8002004 0x10000D03
61 mww 0xD8002008 0x00720900
62
63 nand probe 0
64 }
65
66 nand device tx27.nand mxc $_TARGETNAME mx27 hwecc biswap

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