tcl/board/dm355evm.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # DM355 EVM board
   4 #   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
   5 #   http://c6000.spectrumdigital.com/evmdm355/
   6
   7 source [find target/ti_dm355.cfg]
   8
   9 reset_config trst_and_srst separate
  10
  11 # NOTE:  disable or replace this call to dm355evm_init if you're
  12 # debugging new UBL code from SRAM.
  13 $_TARGETNAME configure -event reset-init { dm355evm_init }
  14
  15 #
  16 # This post-reset init is called when the MMU isn't active, all IRQs
  17 # are disabled, etc.  It should do most of what a UBL does, except for
  18 # loading code (like U-Boot) into DRAM and running it.
  19 #
  20 proc dm355evm_init {} {
  21         global dm355
  22
  23         echo "Initialize DM355 EVM board"
  24
  25         # CLKIN = 24 MHz ... can't talk quickly to ARM yet
  26         jtag_rclk 1500
  27
  28         ########################
  29         # PLL1          = 432 MHz (/8, x144)
  30         # ...SYSCLK1    = 216 MHz (/2)  ... ARM, MJCP
  31         # ...SYSCLK2    = 108 MHz (/4)  ... Peripherals
  32         # ...SYSCLK3    = 27  MHz (/16) ... VPBE, DAC
  33         # ...SYSCLK4    = 108 MHz (/4)  ... VPSS
  34         #       pll1.{prediv,div1,div2} are fixed
  35         #       pll1.postdiv set in MISC (for *this* speed grade)
  36
  37         set addr [dict get $dm355 pllc1]
  38         set pll_divs [dict create]
  39         dict set pll_divs div3 16
  40         dict set pll_divs div4 4
  41         pll_v02_setup $addr 144 $pll_divs
  42
  43         # ARM is now running at 216 MHz, so JTAG can go faster
  44         jtag_rclk 20000
  45
  46         ########################
  47         # PLL2          = 342 MHz (/8, x114)
  48         # ....SYSCLK1   = 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
  49         #       pll2.{postdiv,div1} are fixed
  50
  51         set addr [dict get $dm355 pllc2]
  52         set pll_divs [dict create]
  53         dict set pll_divs div1 1
  54         dict set pll_divs prediv 8
  55         pll_v02_setup $addr 114 $pll_divs
  56
  57         ########################
  58         # PINMUX
  59
  60         # All Video Inputs
  61         davinci_pinmux $dm355 0 0x00007f55
  62         # All Video Outputs
  63         davinci_pinmux $dm355 1 0x00145555
  64         # EMIFA (NOTE: more could be set up for use as GPIOs)
  65         davinci_pinmux $dm355 2 0x00000c08
  66         # SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
  67         davinci_pinmux $dm355 3 0x1bff55ff
  68         # MMC/SD0 instead of MS; SPI0
  69         davinci_pinmux $dm355 4 0x00000000
  70
  71         ########################
  72         # PSC setup (minimal)
  73
  74         # DDR EMIF/13, AEMIF/14, UART0/19
  75         psc_enable 13
  76         psc_enable 14
  77         psc_enable 19
  78         psc_go
  79
  80         ########################
  81         # DDR2 EMIF
  82
  83         # VTPIOCR impedance calibration
  84         set addr [dict get $dm355 sysbase]
  85         set addr [expr {$addr + 0x70}]
  86
  87         # clear CLR, LOCK, PWRDN; wait a clock; set CLR
  88         mmw $addr 0 0x20c0
  89         mmw $addr 0x2000 0
  90
  91         # wait for READY
  92         while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
  93
  94         # set IO_READY; then LOCK and PWRSAVE; then PWRDN
  95         mmw $addr 0x4000 0
  96         mmw $addr 0x0180 0
  97         mmw $addr 0x0040 0
  98
  99         # NOTE:  this DDR2 initialization sequence borrows from
 100         # both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
 101
 102         # reset (then re-enable) DDR controller
 103         psc_reset 13
 104         psc_go
 105         psc_enable 13
 106         psc_go
 107
 108         # now set it up for Micron MT47H64M16HR-37E @ 171 MHz
 109
 110         set addr [dict get $dm355 ddr_emif]
 111
 112         # DDRPHYCR1
 113         mww [expr {$addr + 0xe4}] 0x50006404
 114
 115         # PBBPR -- burst priority
 116         mww [expr {$addr + 0x20}] 0xfe
 117
 118         # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
 119         mmw [expr {$addr + 0x08}] 0x00800000 0
 120         mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
 121
 122         # SDTIMR0, SDTIMR1
 123         mww [expr {$addr + 0x10}] 0x2a923249
 124         mww [expr {$addr + 0x14}] 0x4c17c763
 125
 126         # SDCR -- relock SDTIM*
 127         mmw [expr {$addr + 0x08}] 0 0x00008000
 128
 129         # SDRCR -- refresh rate (171 MHz * 7.8usec)
 130         mww [expr {$addr + 0x0c}] 1336
 131
 132         ########################
 133         # ASYNC EMIF
 134
 135         set addr [dict get $dm355 a_emif]
 136
 137         # slow/pessimistic timings
 138         set nand_timings 0x40400204
 139         # fast (25% faster page reads)
 140         #set nand_timings 0x0400008c
 141
 142         # AWCCR
 143         mww [expr {$addr + 0x04}] 0xff
 144         # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
 145         mww [expr {$addr + 0x10}] $nand_timings
 146         # CS1 == dm9000 Ethernet
 147         mww [expr {$addr + 0x14}] 0x00a00505
 148         # NANDFCR -- only CS0 has NAND
 149         mww [expr {$addr + 0x60}] 0x01
 150
 151         # default: both chipselects to the NAND socket are used
 152         nand probe 0
 153         nand probe 1
 154
 155         ########################
 156         # UART0
 157
 158         set addr [dict get $dm355 uart0]
 159
 160         # PWREMU_MGNT -- rx + tx in reset
 161         mww [expr {$addr + 0x30}] 0
 162
 163         # DLL, DLH -- 115200 baud
 164         mwb [expr {$addr + 0x20}] 0x0d
 165         mwb [expr {$addr + 0x24}] 0x00
 166
 167         # FCR - clear and disable FIFOs
 168         mwb [expr {$addr + 0x08}] 0x07
 169         mwb [expr {$addr + 0x08}] 0x00
 170
 171         # IER - disable IRQs
 172         mwb [expr {$addr + 0x04}] 0x00
 173
 174         # LCR - 8-N-1
 175         mwb [expr {$addr + 0x0c}] 0x03
 176
 177         # MCR - no flow control or loopback
 178         mwb [expr {$addr + 0x10}] 0x00
 179
 180         # PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
 181         mww [expr {$addr + 0x30}] 0xe001
 182
 183
 184         ########################
 185
 186         # turn on icache - set I bit in cp15 register c1
 187         arm mcr 15 0 0 1 0 0x00051078
 188 }
 189
 190 # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
 191 #
 192 # NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
 193 # you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
 194 # use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
 195 # needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
 196 set _FLASHNAME $_CHIPNAME.boot
 197 nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
 198 set _FLASHNAME $_CHIPNAME.flash
 199 nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
 200
 201 # FIXME
 202 #  - support writing UBL with its header (new layout only with new ROMs)
 203 #  - support writing ABL/U-Boot with its header (new layout)