flash/nor/nrf5: handle ERROR_WAIT during nRF91 flash erase
[openocd.git] / contrib / loaders / flash / lpcspifi_init.S
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /***************************************************************************
4 * Copyright (C) 2012 by George Harris *
5 * george@luminairecoffee.com *
6 ***************************************************************************/
7
8 /***************************************************************************
9 * This is an algorithm for the LPC43xx family (and probably the LPC18xx *
10 * family as well, though they have not been tested) that will initialize *
11 * memory-mapped SPI flash accesses. Unfortunately NXP has published *
12 * neither the ROM source code that performs this initialization nor the *
13 * register descriptions necessary to do so, so this code is necessary to *
14 * call into the ROM SPIFI API. *
15 ***************************************************************************/
16
17 .text
18 .syntax unified
19 .arch armv7-m
20 .thumb
21 .thumb_func
22
23 .align 2
24
25 /*
26 * Params :
27 * r0 = spifi clock speed
28 */
29
30 #define IOCONFIG_BASE_HIGH 0x4008
31 #define IOCONFIG_BASE_LOW 0x6000
32 #define IOCONFIG_SCK_OFFSET 0x18c
33 #define IOCONFIG_HOLD_OFFSET 0x190
34 #define IOCONFIG_WP_OFFSET 0x194
35 #define IOCONFIG_MISO_OFFSET 0x198
36 #define IOCONFIG_MOSI_OFFSET 0x19c
37 #define IOCONFIG_CS_OFFSET 0x1a0
38
39 #define SPIFI_ROM_TABLE_BASE_HIGH 0x1040
40 #define SPIFI_ROM_TABLE_BASE_LOW 0x0118
41
42 code:
43 mov.w r8, r0
44 sub sp, #0x84
45 add r7, sp, #0x0
46 /* Initialize SPIFI pins */
47 mov.w r3, #IOCONFIG_BASE_LOW
48 movt r3, #IOCONFIG_BASE_HIGH
49 mov.w r2, #0xf3
50 str.w r2, [r3, #IOCONFIG_SCK_OFFSET]
51 mov.w r3, #IOCONFIG_BASE_LOW
52 movt r3, #IOCONFIG_BASE_HIGH
53 mov.w r2, #IOCONFIG_BASE_LOW
54 movt r2, #IOCONFIG_BASE_HIGH
55 mov.w r1, #IOCONFIG_BASE_LOW
56 movt r1, #IOCONFIG_BASE_HIGH
57 mov.w r0, #IOCONFIG_BASE_LOW
58 movt r0, #IOCONFIG_BASE_HIGH
59 mov.w r4, #0xd3
60 str.w r4, [r0, #IOCONFIG_MOSI_OFFSET]
61 mov r0, r4
62 str.w r0, [r1, #IOCONFIG_MISO_OFFSET]
63 mov r1, r0
64 str.w r1, [r2, #IOCONFIG_WP_OFFSET]
65 str.w r1, [r3, #IOCONFIG_HOLD_OFFSET]
66 mov.w r3, #IOCONFIG_BASE_LOW
67 movt r3, #IOCONFIG_BASE_HIGH
68 mov.w r2, #0x13
69 str.w r2, [r3, #IOCONFIG_CS_OFFSET]
70
71 /* Perform SPIFI init. See spifi_rom_api.h (in NXP lpc43xx driver package) for details */
72 /* on initialization arguments. */
73 movw r3, #SPIFI_ROM_TABLE_BASE_LOW /* The ROM API table is located @ 0x10400118, and */
74 movt r3, #SPIFI_ROM_TABLE_BASE_HIGH /* the first pointer in the struct is to the init function. */
75 ldr r3, [r3, #0x0]
76 ldr r4, [r3, #0x0] /* Grab the init function pointer from the table */
77 /* Set up function arguments */
78 movw r0, #0x3b4
79 movt r0, #0x1000 /* Pointer to a SPIFI data struct that we don't care about */
80 mov.w r1, #0x3 /* "csHigh". Not 100% sure what this does. */
81 mov.w r2, #0xc0 /* The configuration word: S_RCVCLOCK | S_FULLCLK */
82 mov.w r3, r8 /* SPIFI clock speed (12MHz) */
83 blx r4 /* Call the init function */
84 b done
85
86 done:
87 bkpt #0
88
89 .end

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