Tests should that it needs to be as low as 100kHz to be
stable.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
-# JTAG clock should be CCLK/6 (unless using adaptive clocking)
-# CCLK is 4 MHz after reset, and until board-specific code (like
-# a reset-init handler) speeds it up.
-#
# Although rclk "appears to work", it turns out that this yields
# 4MHz whereas the "correct" rate is CCLK/6, which is not what
# you get with rclk.
# Although rclk "appears to work", it turns out that this yields
# 4MHz whereas the "correct" rate is CCLK/6, which is not what
# you get with rclk.
-jtag_khz [ expr 4000 / 6 ]
-
-
+#
+# Also, crank down the frequency further as we're running of an
+# RC oscillator instead of crystal.
+#
+# Setting up XTAL in the reset-init sequence could be worth
+# the effort if you need to program the flash which is pretty
+# big on these devices.
+#
+jtag_khz 100
$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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