This is the very basic board config for the balloon3 board cpu JTAG
channel.
The rest of the config comprises another 14 .cfg files which I suspect
openocd doesn't really want all of. I'm still not sure how to deal
with this. I'll post another mail/patch to discuss.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
--- /dev/null
+# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
+# The board has separate JTAG ports for cpu and CPLD/FPGA devices
+# Chaining is done on IO interfaces if desired.
+
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# flash bank <driver> <base> <size> <chip_width> <bus_width>
+# 29LV650 64Mbit Flash
+flash bank cfi 0x00000000 0x800000 2 2 0
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Code Review / openocd.git / commitdiff