tcl/{board,target}: Add support for HiKey960 05/4805/1
authorJerome Forissier <jerome.forissier@linaro.org>
Tue, 11 Dec 2018 11:42:41 +0000 (12:42 +0100)
committerJerome Forissier <jerome.forissier@linaro.org>
Fri, 14 Dec 2018 08:41:31 +0000 (09:41 +0100)
HiKey960 [1] is an octo-core development board manufactured by LeMaker and
based on the Hisilicon Kirin 960 SoC (aka Hi3660). It contains four Cortex
A53 and four Cortex A73 CPUs.

This patch adds basic support for the Hi3660 target and the HiKey960
board.

Tested with the Bus Blaster v3c adapter.

[1] http://www.lemaker.org/product-hikeysecond-specification.html

Change-Id: I85aeb2f9c508a4821ed67ced0a92f386049cdf91
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
tcl/board/lemaker_hikey960.cfg [new file with mode: 0644]
tcl/target/hi3660.cfg [new file with mode: 0644]

diff --git a/tcl/board/lemaker_hikey960.cfg b/tcl/board/lemaker_hikey960.cfg
new file mode 100644 (file)
index 0000000..cc46bf9
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# Board configuration for LeMaker HiKey960
+#
+# Quick cheat sheet for Linux
+#
+# [target] # for f in /sys/devices/system/cpu/cpu*/cpuidle/state*/disable; do echo 1 >$f; done
+# [host]   $ export INTERFACE=ftdi/dp_busblaster_kt-link.cfg
+#          $ ./src/openocd -f tcl/interface/$INTERFACE -f tcl/board/lemaker_hikey960.cfg
+#          [...]
+#          Info : hi3660.cpu0: hardware has 6 breakpoints, 4 watchpoints
+#          [...]
+# [host]   $ telnet locahost 4444
+#          [...]
+#          > xs
+#          hi3660.cpu1: hardware has 6 breakpoints, 4 watchpoints
+#          hi3660.cpu2: hardware has 6 breakpoints, 4 watchpoints
+#          hi3660.cpu3: hardware has 6 breakpoints, 4 watchpoints
+#          hi3660.cpu4: hardware has 6 breakpoints, 4 watchpoints
+#          hi3660.cpu5: hardware has 6 breakpoints, 4 watchpoints
+#          hi3660.cpu6: hardware has 6 breakpoints, 4 watchpoints
+#          hi3660.cpu7: hardware has 6 breakpoints, 4 watchpoints
+#          >
+
+transport select jtag
+
+adapter_khz 10000
+
+reset_config srst_only srst_push_pull
+
+source [find tcl/target/hi3660.cfg]
+
diff --git a/tcl/target/hi3660.cfg b/tcl/target/hi3660.cfg
new file mode 100644 (file)
index 0000000..58a477b
--- /dev/null
@@ -0,0 +1,78 @@
+# Hisilicon Hi3660 Target
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME hi3660
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x5ba00477
+}
+
+# Declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
+
+# Create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# Declare the 8 main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+set $_TARGETNAME.cti(0) 0x80C20000
+set $_TARGETNAME.cti(1) 0x80D20000
+set $_TARGETNAME.cti(2) 0x80E20000
+set $_TARGETNAME.cti(3) 0x80F20000
+set $_TARGETNAME.cti(4) 0x81420000
+set $_TARGETNAME.cti(5) 0x81520000
+set $_TARGETNAME.cti(6) 0x81620000
+set $_TARGETNAME.cti(7) 0x81720000
+
+set $_TARGETNAME.dbg(0) 0x80C10000
+set $_TARGETNAME.dbg(1) 0x80D10000
+set $_TARGETNAME.dbg(2) 0x80E10000
+set $_TARGETNAME.dbg(3) 0x80F10000
+set $_TARGETNAME.dbg(4) 0x81410000
+set $_TARGETNAME.dbg(5) 0x81510000
+set $_TARGETNAME.dbg(6) 0x81610000
+set $_TARGETNAME.dbg(7) 0x81710000
+
+set _cores 8
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)]
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+                         -dbgbase [set $_TARGETNAME.dbg($_core)]"
+
+    if { $_core != 0 } {
+        # Non-boot core examination may fail (use the "xs" command below to
+        # trigger examination manually)
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+# Make cpu0 the default target
+targets ${_TARGETNAME}0
+
+# Examine secondary cores
+proc xs {} {
+  global _TARGETNAME
+  for { set _core 1 } { $_core < 8 } { incr _core 1 } {
+    ${_TARGETNAME}$_core arp_examine
+  }
+}