+ retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
+ if (ERROR_OK != retval)
+ return retval;
+
+ /* allocate a working area */
+ if (target->working_area_size < (uint32_t) nand->page_size + 0x200){
+ LOG_ERROR("Reserve at least 0x%x physical target working area",nand->page_size + 0x200);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ if (target->working_area_phys%4){
+ LOG_ERROR("Reserve the physical target working area at word boundary");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ if (target_alloc_working_area(target, target->working_area_size, &pworking_area) != ERROR_OK)
+ {
+ LOG_ERROR("no working area specified, can't read LPC internal flash");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ target_mem_base = target->working_area_phys;
+
+
+ if (nand->page_size == 2048)
+ {
+ page_buffer = malloc(2048);
+ }
+ else
+ {
+ page_buffer = malloc(512);
+ }
+
+ ecc_flash_buffer = malloc(64);
+
+ /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA write to SLC, WIDTH = bus_width) */
+ target_write_u32(target, 0x20020014, 0x3c);
+
+ if( data && !oob){
+ /* set DMA LLI-s in target memory and in DMA*/
+ for(i=0;i<nand->page_size/0x100;i++){
+
+ int tmp;
+ /* -------LLI for 256 byte block---------*/
+ /* DMACC0SrcAddr = SRAM */
+ target_write_u32(target,target_mem_base+0+i*32,target_mem_base+DATA_OFFS+i*256 );
+ if(i==0) target_write_u32(target,0x31000100,target_mem_base+DATA_OFFS );
+ /* DMACCxDestAddr = SLC_DMA_DATA */
+ target_write_u32(target,target_mem_base+4+i*32,0x20020038 );
+ if(i==0) target_write_u32(target,0x31000104,0x20020038 );
+ /* DMACCxLLI = next element */
+ tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
+ target_write_u32(target,target_mem_base+8+i*32, tmp );
+ if(i==0) target_write_u32(target,0x31000108, tmp );
+ /* DMACCxControl = TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
+ Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
+ Destination increment = 0, Terminal count interrupt enable bit = 0*/
+ target_write_u32(target,target_mem_base+12+i*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
+ if(i==0) target_write_u32(target,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
+
+ /* -------LLI for 3 byte ECC---------*/
+ /* DMACC0SrcAddr = SLC_ECC*/
+ target_write_u32(target,target_mem_base+16+i*32,0x20020034 );
+ /* DMACCxDestAddr = SRAM */
+ target_write_u32(target,target_mem_base+20+i*32,target_mem_base+SPARE_OFFS+8+16*(i>>1)+(i%2)*4 );
+ /* DMACCxLLI = next element */
+ tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
+ target_write_u32(target,target_mem_base+24+i*32, tmp );
+ /* DMACCxControl = TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
+ Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
+ Destination increment = 1, Terminal count interrupt enable bit = 0*/
+ target_write_u32(target,target_mem_base+28+i*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
+ }
+ }
+ else if (data && oob){
+ /* -------LLI for 512 or 2048 bytes page---------*/
+ /* DMACC0SrcAddr = SRAM */
+ target_write_u32(target,target_mem_base,target_mem_base+DATA_OFFS );
+ target_write_u32(target,0x31000100,target_mem_base+DATA_OFFS );
+ /* DMACCxDestAddr = SLC_DMA_DATA */
+ target_write_u32(target,target_mem_base+4,0x20020038 );
+ target_write_u32(target,0x31000104,0x20020038 );
+ /* DMACCxLLI = next element */
+ target_write_u32(target,target_mem_base+8, (target_mem_base+32)&0xfffffffc );
+ target_write_u32(target,0x31000108, (target_mem_base+32)&0xfffffffc );
+ /* DMACCxControl = TransferSize =512 or 128, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
+ Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
+ Destination increment = 0, Terminal count interrupt enable bit = 0*/
+ target_write_u32(target,target_mem_base+12,(nand->page_size==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
+ target_write_u32(target,0x3100010c,(nand->page_size==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
+ i = 1;
+ }
+ else if (!data && oob){
+ i = 0;
+ }
+
+ /* -------LLI for spare area---------*/
+ /* DMACC0SrcAddr = SRAM*/
+ target_write_u32(target,target_mem_base+0+i*32,target_mem_base+SPARE_OFFS );
+ if(i==0) target_write_u32(target,0x31000100,target_mem_base+SPARE_OFFS );
+ /* DMACCxDestAddr = SLC_DMA_DATA */
+ target_write_u32(target,target_mem_base+4+i*32,0x20020038 );
+ if(i==0) target_write_u32(target,0x31000104,0x20020038 );
+ /* DMACCxLLI = next element = NULL */
+ target_write_u32(target,target_mem_base+8+i*32, 0 );
+ if(i==0) target_write_u32(target,0x31000108,0 );
+ /* DMACCxControl = TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
+ Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
+ Destination increment = 0, Terminal count interrupt enable bit = 0*/
+ target_write_u32(target,target_mem_base+12+i*32, (nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
+ if(i==0) target_write_u32(target,0x3100010c,(nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31 );
+
+
+
+ memset(ecc_flash_buffer, 0xff, 64);
+ if( oob ){
+ memcpy(ecc_flash_buffer,oob, oob_size);
+ }
+ target_write_memory(target, target_mem_base+SPARE_OFFS, 4, 16, ecc_flash_buffer);
+
+ if (data){
+ memset(page_buffer, 0xff, nand->page_size == 2048?2048:512);
+ memcpy(page_buffer,data, data_size);
+ target_write_memory(target, target_mem_base+DATA_OFFS, 4, nand->page_size == 2048?512:128, page_buffer);
+ }
+
+ free(page_buffer);
+ free(ecc_flash_buffer);
+
+ /* Enable DMA after channel set up !
+ LLI only works when DMA is the flow controller!
+ */
+ /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
+ target_write_u32(target,0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
+
+
+
+ /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
+ target_write_u32(target, 0x20020010, 0x3);
+
+ /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
+ target_write_u32(target, 0x20020028, 2);
+
+ /* SLC_TC */
+ if (!data && oob)
+ target_write_u32(target, 0x20020030, (nand->page_size==2048?0x10:0x04));
+ else
+ target_write_u32(target, 0x20020030, (nand->page_size==2048?0x840:0x210));
+
+ nand_write_finish(nand);
+
+
+ if (!lpc3180_tc_ready(nand, 1000))
+ {
+ LOG_ERROR("timeout while waiting for completion of DMA");
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ target_free_working_area(target,pworking_area);
+
+ LOG_INFO("Page = 0x%x was written.",page);
+
+ }
+ else
+ return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
+ }
+