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this change is a preparation for STM32L5 support on top of L4 driver
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.
a table with register offset will be introduced, thus correct register
addresses will be obtained using this table and the driver internal
function 'stm32l4_get_flash_reg' will be responsible of this.
Change-Id: I74bf61a83fe53575623640af0328b3253ecc796f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5508
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Michael Jung <mijung@gmx.net>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
- struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
uint32_t buffer_size;
struct working_area *write_algorithm;
struct working_area *source;
uint32_t buffer_size;
struct working_area *write_algorithm;
struct working_area *source;
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[3].value, 0, 32, count);
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[3].value, 0, 32, count);
- buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base + STM32_FLASH_SR);
- buf_set_u32(reg_params[5].value, 0, 32, stm32l4_info->part_info->flash_regs_base + STM32_FLASH_CR);
+ buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg(bank, STM32_FLASH_SR));
+ buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg(bank, STM32_FLASH_CR));
retval = target_run_flash_async_algorithm(target, buffer, count, 8,
0, NULL,
retval = target_run_flash_async_algorithm(target, buffer, count, 8,
0, NULL,
if (retval != ERROR_OK)
goto err_lock;
if (retval != ERROR_OK)
goto err_lock;
- retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+ retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
err_lock:
retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
err_lock:
retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
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