David Claffey <dnclaffey@gmail.com> get rid of reset recursion

git-svn-id: svn://svn.berlios.de/openocd/trunk@2664 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg
index f2f5289ba448aa178b2e110e1467d70c43575e12..213048ae8f0a9da75c25a766aff2d03c9bd9cb98 100644 (file)
--- a/tcl/target/ar71xx.cfg
+++ b/tcl/target/ar71xx.cfg
@@ -13,16 +13,17 @@ jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
 set TARGETNAME [format "%s.cpu" $CHIPNAME]
 target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
 
 set TARGETNAME [format "%s.cpu" $CHIPNAME]
 target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
 

-$TARGETNAME configure -event reset-init {
+$TARGETNAME configure -event reset-halt-post {

        #setup PLL to lowest common denominator 300/300/150 setting
        mww 0xb8050000 0x000f40a3       # reset val + CPU:3 DDR:3 AHB:0
        mww 0xb8050000 0x800f40a3       # send to PLL
 
        #next command will reset for PLL changes to take effect
        mww 0xb8050008 3                # set reset_switch and clock_switch (resets SoC)
        #setup PLL to lowest common denominator 300/300/150 setting
        mww 0xb8050000 0x000f40a3       # reset val + CPU:3 DDR:3 AHB:0
        mww 0xb8050000 0x800f40a3       # send to PLL
 
        #next command will reset for PLL changes to take effect
        mww 0xb8050008 3                # set reset_switch and clock_switch (resets SoC)

-       reset halt                      # let openocd know that it is in the reset state
+}

 
 

-       #initialize_pll
+$TARGETNAME configure -event reset-init {
+       #complete pll initialization

        mww 0xb8050000 0x800f0080       # set sw_update bit
        mww 0xb8050008 0                # clear reset_switch bit
        mww 0xb8050000 0x800f00e8       # clr pwrdwn & bypass
        mww 0xb8050000 0x800f0080       # set sw_update bit
        mww 0xb8050008 0                # clear reset_switch bit
        mww 0xb8050000 0x800f00e8       # clr pwrdwn & bypass