STM32G4 cat.4 devices are up to 512 KB of flash memory (single bank)
organized into pages of 2KB each.
Reference: RM0440 rev.4
Change-Id: I0f510e2806c8f824fff8083e2d4f90d68f01046b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5793
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
/*
* STM32G4xxx series for reference.
*
/*
* STM32G4xxx series for reference.
*
- * RM0440 (STM32G43x/44x/47x/48x)
+ * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
* http://www.st.com/resource/en/reference_manual/dm00355726.pdf
*
* Cat. 2 devices have single bank only, page size is 2kByte.
* http://www.st.com/resource/en/reference_manual/dm00355726.pdf
*
* Cat. 2 devices have single bank only, page size is 2kByte.
*
* Bank mode is controlled by bit 22 (DBANK) in option bytes register.
* Both banks are treated as a single OpenOCD bank.
*
* Bank mode is controlled by bit 22 (DBANK) in option bytes register.
* Both banks are treated as a single OpenOCD bank.
+ *
+ * Cat. 4 devices have single bank only, page size is 2kByte.
*/
/* Erase time can be as high as 25ms, 10x this and assume it's toast... */
*/
/* Erase time can be as high as 25ms, 10x this and assume it's toast... */
+static const struct stm32l4_rev stm32_479_revs[] = {
+ { 0x1000, "A" },
+};
+
static const struct stm32l4_rev stm32_495_revs[] = {
{ 0x2001, "2.1" },
};
static const struct stm32l4_rev stm32_495_revs[] = {
{ 0x2001, "2.1" },
};
.flash_regs_base = 0x40022000,
.fsize_addr = 0x1FFF75E0,
},
.flash_regs_base = 0x40022000,
.fsize_addr = 0x1FFF75E0,
},
+ {
+ .id = 0x479,
+ .revs = stm32_479_revs,
+ .num_revs = ARRAY_SIZE(stm32_479_revs),
+ .device_str = "STM32G49/G4Axx",
+ .max_flash_size_kb = 512,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
{
.id = 0x495,
.revs = stm32_495_revs,
{
.id = 0x495,
.revs = stm32_495_revs,
case 0x464: /* STM32L41/L42xx */
case 0x466: /* STM32G03/G04xx */
case 0x468: /* STM32G43/G44xx */
case 0x464: /* STM32L41/L42xx */
case 0x466: /* STM32G03/G04xx */
case 0x468: /* STM32G43/G44xx */
+ case 0x479: /* STM32G49/G4Axx */
case 0x497: /* STM32WLEx */
/* single bank flash */
page_size_kb = 2;
case 0x497: /* STM32WLEx */
/* single bank flash */
page_size_kb = 2;
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