}
/* Mark registers in new context as dirty to force reload when run */
- for (i = 0; i < armv7m->core_cache->num_regs-1; i++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
+ for (i = 0; i < armv7m->core_cache->num_regs; i++)
{
armv7m->core_cache->reg_list[i].dirty = 1;
}
return ERROR_OK;
}
-
/* Core state functions */
-char enamebuf[32];
char *armv7m_exception_string(int number)
{
+ static char enamebuf[32];
+
if ((number < 0) | (number > 511))
return "Invalid exception";
if (number < 16)
{
if (i < ARMV7NUMCOREREGS)
(*reg_list)[i] = &armv7m->process_context->reg_list[i];
- /* (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; */
else
(*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
}
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
- enum armv7m_state core_state = armv7m->core_state;
- enum armv7m_mode core_mode = armv7m->core_mode;
int retval = ERROR_OK;
u32 pc;
- int exit_breakpoint_size = 0;
int i;
-
- armv7m->core_state = core_state;
- armv7m->core_mode = core_mode;
if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
{
}
/* ARMV7M always runs in Thumb state */
- exit_breakpoint_size = 2;
- if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
+ if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
{
ERROR("can't add breakpoint to finish algorithm execution");
return ERROR_TARGET_FAILURE;
target_write_u32(target, FP_CTRL, 3);
/* Restore FPB registers */
- for ( i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
+ for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
{
target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
}
/* Restore DWT registers */
- for ( i = 0; i < cortex_m3->dwt_num_comp; i++)
+ for (i = 0; i < cortex_m3->dwt_num_comp; i++)
{
target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp);
target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask);
return retval;
/* Examine target state and mode */
- /* First load register acessible through core debug port*/
+ /* First load register acessible through core debug port*/
for (i = 0; i < ARMV7M_PRIMASK; i++)
{
if (!armv7m->core_cache->reg_list[i].valid)
- armv7m->read_core_reg(target, i);
+ armv7m->read_core_reg(target, i);
}
xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
- /* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/
+ /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
if (xPSR & 0xf00)
{
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
cortex_m3_examine_exception_reason(target);
}
- DEBUG("entered debug state at PC 0x%x, target->state: %s ", *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
+ DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \
+ *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
if (armv7m->post_debug_entry)
armv7m->post_debug_entry(target);
/* Check that we are using process_context, or change and print warning */
if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
{
- WARNING("Incorrect context in resume");
+ DEBUG("Incorrect context in resume");
armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
}
cortex_m3_enable_breakpoints(target);
cortex_m3_enable_watchpoints(target);
- /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */
+ /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */
}
dcb_dhcsr = DBGKEY | C_DEBUGEN;
/* Check that we are using debug_context, or change and print warning */
if (armv7m_get_context(target) != ARMV7M_DEBUG_CONTEXT)
{
- WARNING("Incorrect context in debug_exec resume");
+ DEBUG("Incorrect context in debug_exec resume");
armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
}
/* Disable interrupts */
armv7m->arch_info = cortex_m3;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
- /* armv7m->full_context = cortex_m3_full_context; */
target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);