+
+static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
+}
+
+static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
+}
+
+static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32);
+}
+
+static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32, value);
+}
+
+static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
+}
+
+static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return armv4_5->core_state;
+}
+
+static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ armv4_5->core_state = mode;
+}
+
+
+static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
+{
+ armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+ return armv4_5->core_mode;
+}
+
+
+
+int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+
+ struct arm_sim_interface sim;
+
+ sim.user_data=armv4_5;
+ sim.get_reg=&armv4_5_get_reg;
+ sim.set_reg=&armv4_5_set_reg;
+ sim.get_reg_mode=&armv4_5_get_reg_mode;
+ sim.set_reg_mode=&armv4_5_set_reg_mode;
+ sim.get_cpsr=&armv4_5_get_cpsr;
+ sim.get_mode=&armv4_5_get_mode;
+ sim.get_state=&armv4_5_get_state;
+ sim.set_state=&armv4_5_set_state;
+
+ return arm_simulate_step_core(target, dry_run_pc, &sim);
+
+}
+