+adapter_khz 500
+
+source [find mem_helper.tcl]
+
+proc reset_peripherals {family} {
+
+ source [find chip/ti/lm3s/lm3s.tcl]
+
+ echo "Resetting Core Peripherals"
+
+ # Disable the PLL and the system clock divider (nop if disabled)
+ mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
+ mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
+
+ # RCC and RCC2 to their reset values
+ mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))]
+ mww $SYSCTL_RCC2 0x07806810
+ mww $SYSCTL_RCC 0x078e3ad1
+
+ # Reset the deep sleep clock configuration register
+ mww $SYSCTL_DSLPCLKCFG 0x07800000
+
+ # Reset the clock gating registers
+ mww $SYSCTL_RCGC0 0x00000040
+ mww $SYSCTL_RCGC1 0
+ mww $SYSCTL_RCGC2 0
+ mww $SYSCTL_SCGC0 0x00000040
+ mww $SYSCTL_SCGC1 0
+ mww $SYSCTL_SCGC2 0
+ mww $SYSCTL_DCGC0 0x00000040
+ mww $SYSCTL_DCGC1 0
+ mww $SYSCTL_DCGC2 0
+
+ # Reset the remaining SysCtl registers
+ mww $SYSCTL_PBORCTL 0
+ mww $SYSCTL_IMC 0
+ mww $SYSCTL_GPIOHBCTL 0
+ mww $SYSCTL_MOSCCTL 0
+ mww $SYSCTL_PIOSCCAL 0
+ mww $SYSCTL_I2SMCLKCFG 0
+
+ # Reset the peripherals
+ mww $SYSCTL_SRCR0 0xffffffff
+ mww $SYSCTL_SRCR1 0xffffffff
+ mww $SYSCTL_SRCR2 0xffffffff
+ mww $SYSCTL_SRCR0 0
+ mww $SYSCTL_SRCR1 0
+ mww $SYSCTL_SRCR2 0
+
+ # Clear any pending SysCtl interrupts
+ mww $SYSCTL_MISC 0xffffffff
+
+ # Wait for any pending flash operations to complete
+ while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 }
+ while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 }
+
+ # Reset the flash controller registers
+ mww $FLASH_FMA 0
+ mww $FLASH_FCIM 0
+ mww $FLASH_FCMISC 0xffffffff
+ mww $FLASH_FWBVAL 0
+}
+
+$_TARGETNAME configure -event reset-start {
+ adapter_khz 500
+
+ #
+ # When nRST is asserted on most Stellaris devices, it clears some of
+ # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
+ # and OpenOCD depends on those TRMs. So we won't use SRST on those
+ # chips. (Only power-on reset should affect debug state, beyond a
+ # few specified bits; not the chip's nRST input, wired to SRST.)
+ #
+ # REVISIT current errata specs don't seem to cover this issue.
+ # Do we have more details than this email?
+ # https://lists.berlios.de/pipermail
+ # /openocd-development/2008-August/003065.html
+ #
+
+ global _DEVICECLASS
+
+ if {$_DEVICECLASS != 0xff} {
+ set device_class $_DEVICECLASS
+ } else {
+ set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
+ }
+
+ if {$device_class == 0 || $device_class == 1 ||
+ $device_class == 3 || $device_class == 5 || $device_class == 0xa} {
+ if {![using_hla]} {
+ # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
+ cortex_m reset_config sysresetreq
+ }
+ } else {
+ if {![using_hla]} {
+ # Tempest and Firestorm default to using NVIC VECTRESET
+ # peripherals will need reseting manually, see proc reset_peripherals
+ cortex_m reset_config vectreset
+ }
+ # reset peripherals, based on code in
+ # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
+ reset_peripherals $device_class
+ }
+}