target/imx6ul: Initial support

[openocd.git] / tcl / target / omap3530.cfg

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index f9dcf7cbfe8a6fd47a03bdb0cc72823f1d9ce59c..078d7f24db97b3a431e8a7d8ba8b226bca019d3a 100644 (file)
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -20,9 +20,9 @@ if { [info exists DAP_TAPID] } {
 } else {
    set _DAP_TAPID 0x0b6d602f
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
        -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag configure $_CHIPNAME.cpu -event tap-enable \
        "icepick_c_tapenable $_CHIPNAME.jrc 3"
 
 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
@@ -36,7 +36,8 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 # SRAM: 64K at 0x4020.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
@@ -53,7 +54,7 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
 proc omap3_dbginit {target} {
-     # General Cortex A8 debug initialisation
+     # General Cortex-A8 debug initialisation
      cortex_a dbginit
      # Enable DBGU signal for OMAP353x
      $target mww phys 0x5401d030 0x00002000