TCL: fix non TCL comments

[openocd.git] / tcl / board / digi_connectcore_wi-9c.cfg

diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg
index 096af1b66d67c05e823b3effb836e1d8d1153f0b..094e70e909b4b2d8194068833c2d9d7b068667f6 100644 (file)
--- a/tcl/board/digi_connectcore_wi-9c.cfg
+++ b/tcl/board/digi_connectcore_wi-9c.cfg
@@ -48,31 +48,31 @@ target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNA
 
 $_TARGETNAME configure -event reset-init {
        mww 0x90600104 0x33313333
-       mww 0xA0700000 0x00000001  # Enable the memory controller.
-       mww 0xA0700024 0x00000006  # Set the refresh counter 6
-       mww 0xA0700028 0x00000001  #
-       mww 0xA0700030 0x00000001  # Set the precharge period
-       mww 0xA0700034 0x00000004  # Active to precharge command period is 16 clock cycles
-       mww 0xA070003C 0x00000001  # tAPR
-       mww 0xA0700040 0x00000005  # tDAL
-       mww 0xA0700044 0x00000001  # tWR
-       mww 0xA0700048 0x00000006  # tRC 32 clock cycles
-       mww 0xA070004C 0x00000006  # tRFC 32 clock cycles
-       mww 0xA0700054 0x00000001  # tRRD
-       mww 0xA0700058 0x00000001  # tMRD
-       mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4)
-       mww 0xA0700120 0x00004280  # Dynamic Config 1 (cs5)
-       mww 0xA0700140 0x00004280  # Dynamic Config 2 (cs6)
-       mww 0xA0700160 0x00004280  # Dynamic Config 3 (cs7)
+       mww 0xA0700000 0x00000001  ;# Enable the memory controller.
+       mww 0xA0700024 0x00000006  ;# Set the refresh counter 6
+       mww 0xA0700028 0x00000001  ;#
+       mww 0xA0700030 0x00000001  ;# Set the precharge period
+       mww 0xA0700034 0x00000004  ;# Active to precharge command period is 16 clock cycles
+       mww 0xA070003C 0x00000001  ;# tAPR
+       mww 0xA0700040 0x00000005  ;# tDAL
+       mww 0xA0700044 0x00000001  ;# tWR
+       mww 0xA0700048 0x00000006  ;# tRC 32 clock cycles
+       mww 0xA070004C 0x00000006  ;# tRFC 32 clock cycles
+       mww 0xA0700054 0x00000001  ;# tRRD
+       mww 0xA0700058 0x00000001  ;# tMRD
+       mww 0xA0700100 0x00004280  ;# Dynamic Config 0 (cs4)
+       mww 0xA0700120 0x00004280  ;# Dynamic Config 1 (cs5)
+       mww 0xA0700140 0x00004280  ;# Dynamic Config 2 (cs6)
+       mww 0xA0700160 0x00004280  ;# Dynamic Config 3 (cs7)
        #
-       mww 0xA0700104 0x00000203  # CAS latency is 2 at 100 MHz
-       mww 0xA0700124 0x00000203  # CAS latency is 2 at 100 MHz
-       mww 0xA0700144 0x00000203  # CAS latency is 2 at 100 MHz
-       mww 0xA0700164 0x00000203  # CAS latency is 2 at 100 MHz
+       mww 0xA0700104 0x00000203  ;# CAS latency is 2 at 100 MHz
+       mww 0xA0700124 0x00000203  ;# CAS latency is 2 at 100 MHz
+       mww 0xA0700144 0x00000203  ;# CAS latency is 2 at 100 MHz
+       mww 0xA0700164 0x00000203  ;# CAS latency is 2 at 100 MHz
        #
-       mww 0xA0700020 0x00000103  # issue SDRAM PALL command
+       mww 0xA0700020 0x00000103  ;# issue SDRAM PALL command
        #
-       mww 0xA0700024 0x00000001  # Set the refresh counter to be as small as possible
+       mww 0xA0700024 0x00000001  ;# Set the refresh counter to be as small as possible
        #
        # Add some dummy writes to give the SDRAM time to settle, it needs two
        # AHB clock cycles, here we poke in the debugger flag, this lets
@@ -89,19 +89,19 @@ $_TARGETNAME configure -event reset-init {
        mdw 0xA0900000
        mdw 0xA0900000
        #
-       mww 0xA0700024 0x00000030 # Set the refresh counter to 30
-       mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
+       mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
+       mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
        #
        # Next we perform a read of RAM.
        # mw = move word.
        mdw 0x00022000
        # mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
        #
-       mww 0xA0700020 0x00000003   # issue SDRAM NORMAL command
-       mww 0xA0700100 0x00084280   # Enable buffer access
-       mww 0xA0700120 0x00084280   # Enable buffer access
-       mww 0xA0700140 0x00084280   # Enable buffer access
-       mww 0xA0700160 0x00084280   # Enable buffer access
+       mww 0xA0700020 0x00000003   ;# issue SDRAM NORMAL command
+       mww 0xA0700100 0x00084280   ;# Enable buffer access
+       mww 0xA0700120 0x00084280   ;# Enable buffer access
+       mww 0xA0700140 0x00084280   ;# Enable buffer access
+       mww 0xA0700160 0x00084280   ;# Enable buffer access
 
        #Set byte lane state (static mem 1)"
        mww 0xA0700220 0x00000082