#include "mips32.h"
#include "mips_m4k.h"
+#include "mips32_dmaacc.h"
#include "jtag.h"
#include "log.h"
.assert_reset = mips_m4k_assert_reset,
.deassert_reset = mips_m4k_deassert_reset,
.soft_reset_halt = mips_m4k_soft_reset_halt,
-
+
.get_gdb_reg_list = mips32_get_gdb_reg_list,
.read_memory = mips_m4k_read_memory,
.bulk_write_memory = mips_m4k_bulk_write_memory,
.checksum_memory = NULL,
.blank_check_memory = NULL,
-
+
.run_algorithm = mips32_run_algorithm,
.add_breakpoint = mips_m4k_add_breakpoint,
.quit = mips_m4k_quit
};
+int mips_m4k_examine_debug_reason(target_t *target)
+{
+ int break_status;
+ int retval;
+
+ if ((target->debug_reason != DBG_REASON_DBGRQ)
+ && (target->debug_reason != DBG_REASON_SINGLESTEP))
+ {
+ /* get info about inst breakpoint support */
+ if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
+ return retval;
+ if (break_status & 0x1f)
+ {
+ /* we have halted on a breakpoint */
+ if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
+ return retval;
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ }
+
+ /* get info about data breakpoint support */
+ if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
+ return retval;
+ if (break_status & 0x1f)
+ {
+ /* we have halted on a breakpoint */
+ if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
+ return retval;
+ target->debug_reason = DBG_REASON_WATCHPOINT;
+ }
+ }
+
+ return ERROR_OK;
+}
+
int mips_m4k_debug_entry(target_t *target)
{
- u32 debug_reg;
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
+ u32 debug_reg;
+
/* read debug register */
mips_ejtag_read_debug(ejtag_info, &debug_reg);
-
- if ((target->debug_reason != DBG_REASON_DBGRQ)
- && (target->debug_reason != DBG_REASON_SINGLESTEP))
- {
-// if (cortex_m3->nvic_dfsr & DFSR_BKPT)
-// {
-// target->debug_reason = DBG_REASON_BREAKPOINT;
-// if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
-// target->debug_reason = DBG_REASON_WPTANDBKPT;
-// }
-// else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
-// target->debug_reason = DBG_REASON_WATCHPOINT;
- }
-
+
+ /* make sure break uit configured */
+ mips32_configure_break_unit(target);
+
+ /* attempt to find halt reason */
+ mips_m4k_examine_debug_reason(target);
+
+ /* clear single step if active */
if (debug_reg & EJTAG_DEBUG_DSS)
{
/* stopped due to single step - clear step bit */
mips_ejtag_config_step(ejtag_info, 0);
}
-
+
mips32_save_context(target);
-
- LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
- *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
+
+ LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
+ *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
-
+
return ERROR_OK;
}
int retval;
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
+ u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
+
/* read ejtag control reg */
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
-
- if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST)
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+
+ /* clear this bit before handling polling
+ * as after reset registers will read zero */
+ if (ejtag_ctrl & EJTAG_CTRL_ROCC)
+ {
+ /* we have detected a reset, clear flag
+ * otherwise ejtag will not work */
+ jtag_add_end_state(TAP_IDLE);
+ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
+
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ LOG_DEBUG("Reset Detected");
+ }
+
+ /* check for processor halted */
+ if (ejtag_ctrl & EJTAG_CTRL_BRKST)
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
-
+
target->state = TARGET_HALTED;
-
+
if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
return retval;
-
+
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
else if (target->state == TARGET_DEBUG_RUNNING)
{
target->state = TARGET_HALTED;
-
+
if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
return retval;
-
+
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
}
{
target->state = TARGET_RUNNING;
}
-
- if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_ROCC)
- {
- /* we have detected a reset, clear flag
- * otherwise ejtag will not work */
- jtag_add_end_state(TAP_RTI);
- ejtag_info->ejtag_ctrl &= ~EJTAG_CTRL_ROCC;
-
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
- LOG_DEBUG("Reset Detected");
- }
-
-// LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl);
-
+
+// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
+
return ERROR_OK;
}
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
- LOG_DEBUG("target->state: %s",
+
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
-
+
if (target->state == TARGET_HALTED)
{
LOG_DEBUG("target was already halted");
return ERROR_OK;
}
-
+
if (target->state == TARGET_UNKNOWN)
{
LOG_WARNING("target was in unknown state when halt was requested");
}
-
- if (target->state == TARGET_RESET)
+
+ if (target->state == TARGET_RESET)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
{
* debug entry was already prepared in mips32_prepare_reset_halt()
*/
target->debug_reason = DBG_REASON_DBGRQ;
-
+
return ERROR_OK;
}
}
-
+
/* break processor */
mips_ejtag_enter_debug(ejtag_info);
-
+
target->debug_reason = DBG_REASON_DBGRQ;
-
+
return ERROR_OK;
}
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
- LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
-
+ mips_m4k_common_t *mips_m4k = mips32->arch_info;
+
+ LOG_DEBUG("target->state: %s",
+ Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+
if (!(jtag_reset_config & RESET_HAS_SRST))
{
LOG_ERROR("Can't assert SRST");
return ERROR_FAIL;
}
-
+
if (target->reset_halt)
{
/* use hardware to catch reset */
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
}
else
{
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
}
-
- /* here we should issue a srst only, but we may have to assert trst as well */
- if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+
+ if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
{
- jtag_add_reset(1, 1);
+ u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
+ LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
}
else
{
- jtag_add_reset(0, 1);
+ /* here we should issue a srst only, but we may have to assert trst as well */
+ if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+ {
+ jtag_add_reset(1, 1);
+ }
+ else
+ {
+ jtag_add_reset(0, 1);
+ }
}
-
+
target->state = TARGET_RESET;
jtag_add_sleep(50000);
mips32_invalidate_core_regs(target);
- if (target->reset_halt)
- {
- int retval;
+ if (target->reset_halt)
+ {
+ int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
- }
-
-
+ }
+
return ERROR_OK;
}
int mips_m4k_deassert_reset(target_t *target)
{
- LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
-
+ LOG_DEBUG("target->state: %s",
+ Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+
/* deassert reset lines */
jtag_add_reset(0, 0);
-
+
return ERROR_OK;
}
return ERROR_OK;
}
+int mips_m4k_single_step_core(target_t *target)
+{
+ mips32_common_t *mips32 = target->arch_info;
+ mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+
+ /* configure single step mode */
+ mips_ejtag_config_step(ejtag_info, 1);
+
+ /* exit debug mode */
+ mips_ejtag_exit_debug(ejtag_info, 1);
+
+ mips_m4k_debug_entry(target);
+
+ return ERROR_OK;
+}
+
int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
breakpoint_t *breakpoint = NULL;
u32 resume_pc;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (!debug_execution)
{
target_free_all_working_areas(target);
mips_m4k_enable_breakpoints(target);
mips_m4k_enable_watchpoints(target);
}
-
+
/* current = 1: continue on current pc, otherwise continue at <address> */
- if (!current)
+ if (!current)
{
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
}
-
+
resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
-
+
mips32_restore_context(target);
-
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
{
{
LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
mips_m4k_unset_breakpoint(target, breakpoint);
- //mips_m4k_single_step_core(target);
+ mips_m4k_single_step_core(target);
mips_m4k_set_breakpoint(target, breakpoint);
}
}
-
+
/* exit debug mode - enable interrupts if required */
mips_ejtag_exit_debug(ejtag_info, !debug_execution);
-
+ target->debug_reason = DBG_REASON_NOTHALTED;
+
/* registers are now invalid */
mips32_invalidate_core_regs(target);
-
+
if (!debug_execution)
{
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
}
-
+
return ERROR_OK;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
-
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
mips_m4k_unset_breakpoint(target, breakpoint);
-
+
/* restore context */
mips32_restore_context(target);
-
+
/* configure single step mode */
mips_ejtag_config_step(ejtag_info, 1);
-
+
target->debug_reason = DBG_REASON_SINGLESTEP;
-
+
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-
+
/* exit debug mode */
mips_ejtag_exit_debug(ejtag_info, 1);
-
+
/* registers are now invalid */
mips32_invalidate_core_regs(target);
-
+
if (breakpoint)
mips_m4k_set_breakpoint(target, breakpoint);
LOG_DEBUG("target stepped ");
-
+
mips_m4k_debug_entry(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-
+
return ERROR_OK;
}
void mips_m4k_enable_breakpoints(struct target_s *target)
{
breakpoint_t *breakpoint = target->breakpoints;
-
+
/* set any pending breakpoints */
while (breakpoint)
{
int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- /* TODO */
+ mips32_common_t *mips32 = target->arch_info;
+ mips32_comparator_t * comparator_list = mips32->inst_break_list;
+
+ if (breakpoint->set)
+ {
+ LOG_WARNING("breakpoint already set");
+ return ERROR_OK;
+ }
+
+ if (breakpoint->type == BKPT_HARD)
+ {
+ int bp_num = 0;
+
+ while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
+ bp_num++;
+ if (bp_num >= mips32->num_inst_bpoints)
+ {
+ LOG_DEBUG("ERROR Can not find free FP Comparator");
+ LOG_WARNING("ERROR Can not find free FP Comparator");
+ exit(-1);
+ }
+ breakpoint->set = bp_num + 1;
+ comparator_list[bp_num].used = 1;
+ comparator_list[bp_num].bp_value = breakpoint->address;
+ target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
+ target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
+ target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
+ LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
+ }
+ else if (breakpoint->type == BKPT_SOFT)
+ {
+
+ }
+
return ERROR_OK;
}
int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- /* TODO */
+ /* get pointers to arch-specific information */
+ mips32_common_t *mips32 = target->arch_info;
+ mips32_comparator_t * comparator_list = mips32->inst_break_list;
+
+ if (!breakpoint->set)
+ {
+ LOG_WARNING("breakpoint not set");
+ return ERROR_OK;
+ }
+
+ if (breakpoint->type == BKPT_HARD)
+ {
+ int bp_num = breakpoint->set - 1;
+ if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
+ {
+ LOG_DEBUG("Invalid FP Comparator number in breakpoint");
+ return ERROR_OK;
+ }
+ comparator_list[bp_num].used = 0;
+ comparator_list[bp_num].bp_value = 0;
+ target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
+ }
+ else
+ {
+
+ }
+ breakpoint->set = 0;
+
return ERROR_OK;
}
int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- /* TODO */
+ mips32_common_t *mips32 = target->arch_info;
+
+ if (mips32->num_inst_bpoints_avail < 1)
+ {
+ LOG_INFO("no hardware breakpoint available");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ /* default to hardware for now */
+ breakpoint->type = BKPT_HARD;
+
+ mips32->num_inst_bpoints_avail--;
+ mips_m4k_set_breakpoint(target, breakpoint);
+
return ERROR_OK;
}
int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- /* TODO */
+ /* get pointers to arch-specific information */
+ mips32_common_t *mips32 = target->arch_info;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_WARNING("target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (breakpoint->set)
+ {
+ mips_m4k_unset_breakpoint(target, breakpoint);
+ }
+
+ if (breakpoint->type == BKPT_HARD)
+ mips32->num_inst_bpoints_avail++;
+
return ERROR_OK;
}
void mips_m4k_enable_watchpoints(struct target_s *target)
{
watchpoint_t *watchpoint = target->watchpoints;
-
+
/* set any pending watchpoints */
while (watchpoint)
{
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
+
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED)
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
-
+
switch (size)
{
case 4:
case 2:
case 1:
/* if noDMA off, use DMAACC mode for memory read */
- if(ejtag_info->impcode & (1<<14))
+ if(ejtag_info->impcode & EJTAG_IMP_NODMA)
return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
else
return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
+
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED)
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
-
+
switch (size)
{
case 4:
case 2:
case 1:
/* if noDMA off, use DMAACC mode for memory write */
- if(ejtag_info->impcode & (1<<14))
+ if(ejtag_info->impcode & EJTAG_IMP_NODMA)
mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
else
mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
exit(-1);
break;
}
-
+
return ERROR_OK;
}
int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
-
+
retval = mips32_register_commands(cmd_ctx);
return retval;
}
int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
mips32_build_reg_cache(target);
-
+
return ERROR_OK;
}
return ERROR_OK;
}
-int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int chain_pos, const char *variant)
+int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
{
mips32_common_t *mips32 = &mips_m4k->mips32_common;
-
+
if (variant)
{
mips_m4k->variant = strdup(variant);
{
mips_m4k->variant = strdup("");
}
-
+
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
-
+
/* initialize mips4k specific info */
- mips32_init_arch_info(target, mips32, chain_pos, variant);
+ mips32_init_arch_info(target, mips32, tap, variant);
mips32->arch_info = mips_m4k;
-
+
return ERROR_OK;
}
int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
{
mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
-
- mips_m4k_init_arch_info(target, mips_m4k, target->chain_position, target->variant);
-
+
+ mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
+
return ERROR_OK;
}
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
u32 idcode = 0;
-
- target->type->examined = 1;
-
- mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
-
- if (((idcode >> 1) & 0x7FF) == 0x29)
- {
- /* we are using a pic32mx so select ejtag port
- * as it is not selected by default */
- mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
- LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
- }
-
+
+ if (!target->type->examined)
+ {
+ mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
+
+ if (((idcode >> 1) & 0x7FF) == 0x29)
+ {
+ /* we are using a pic32mx so select ejtag port
+ * as it is not selected by default */
+ mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
+ LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
+ }
+ }
+
/* init rest of ejtag interface */
if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
return retval;
-
+
+ if ((retval = mips32_examine(target)) != ERROR_OK)
+ return retval;
+
return ERROR_OK;
}
Code Review / openocd.git / blobdiff