scan_field_t field;
u8 status;
- if (str9xpec_set_instr(tap, ISC_NOOP, TAP_PI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE) != ERROR_OK)
return ISC_STATUS_ERROR;
field.tap = tap;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_RTI);
+ jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
LOG_DEBUG("status: 0x%2.2x", status);
return ERROR_OK;
/* enter isc mode */
- if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_RTI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_ENABLE, TAP_IDLE) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* check ISC status */
if (!str9xpec_info->isc_enable)
return ERROR_OK;
- if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_RTI) != ERROR_OK)
+ if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_IDLE) != ERROR_OK)
return ERROR_TARGET_INVALID;
/* delay to handle aborts */
LOG_DEBUG("ISC_CONFIGURATION");
/* execute ISC_CONFIGURATION command */
- str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_PI);
+ str9xpec_set_instr(tap, ISC_CONFIGURATION, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_RTI);
+ jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
status = str9xpec_isc_status(tap);
armv4_5 = bank->target->arch_info;
arm7_9 = armv4_5->arch_info;
jtag_info = &arm7_9->jtag_info;
-
+
str9xpec_info->tap = jtag_TapByAbsPosition( jtag_info->tap->abs_chain_position - 1);
str9xpec_info->isc_enable = 0;
-
+
str9xpec_build_block_list(bank);
/* clear option byte register */
}
/* execute ISC_BLANK_CHECK command */
- str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_PI);
+ str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_RTI);
+ jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_add_sleep(40000);
/* read blank check result */
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_PI);
+ jtag_add_dr_scan(1, &field, TAP_IRPAUSE);
jtag_execute_queue();
status = str9xpec_isc_status(tap);
LOG_DEBUG("ISC_ERASE");
/* execute ISC_ERASE command */
- str9xpec_set_instr(tap, ISC_ERASE, TAP_PI);
+ str9xpec_set_instr(tap, ISC_ERASE, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_RTI);
+ jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
jtag_add_sleep(10);
str9xpec_set_address(bank, 0x80);
/* execute ISC_PROGRAM command */
- str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_RTI);
+ str9xpec_set_instr(tap, ISC_PROGRAM_SECURITY, TAP_IDLE);
- str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
tap = str9xpec_info->tap;
/* set flash controller address */
- str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_PI);
+ str9xpec_set_instr(tap, ISC_ADDRESS_SHIFT, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 8;
while (dwords_remaining > 0)
{
- str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_RTI);
+ jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
bytes_written++;
}
- str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_RTI);
+ jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
buffer = calloc(CEIL(32, 8), 1);
- str9xpec_set_instr(tap, ISC_IDCODE, TAP_PI);
+ str9xpec_set_instr(tap, ISC_IDCODE, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 32;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_RTI);
+ jtag_add_dr_scan(1, &field, TAP_IDLE);
jtag_execute_queue();
idcode = buf_get_u32(buffer, 0, 32);
str9xpec_set_address(bank, 0x50);
/* execute ISC_PROGRAM command */
- str9xpec_set_instr(tap, ISC_PROGRAM, TAP_PI);
+ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE);
field.tap = tap;
field.num_bits = 64;
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_dr_scan(1, &field, TAP_RTI);
+ jtag_add_dr_scan(1, &field, TAP_IDLE);
/* small delay before polling */
jtag_add_sleep(50);
- str9xpec_set_instr(tap, ISC_NOOP, TAP_PI);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE);
do {
field.tap = tap;
}
/* enable turbo mode - TURBO-PROG-ENABLE */
- str9xpec_set_instr(tap2, 0xD, TAP_RTI);
+ str9xpec_set_instr(tap2, 0xD, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
/* modify scan chain - str9 core has been removed */
tap1->enabled = 0;
-
+
return ERROR_OK;
}
if (tap == NULL)
return ERROR_FAIL;
-
+
/* exit turbo mode via TLR */
- str9xpec_set_instr(tap, ISC_NOOP, TAP_TLR);
+ str9xpec_set_instr(tap, ISC_NOOP, TAP_RESET);
jtag_execute_queue();
-
+
/* restore previous scan chain */
if (tap->next_tap) {
tap->next_tap->enabled = 1;
{{0x1f, 0x00}, {0x0c, 0x00}, {0x07, 0x00}, {0x97, 0x00}, {0x08, 0x00}, {0x00, 0x00}}, /* PI */
};
-jtag_interface_t amt_jtagaccel_interface =
+jtag_interface_t amt_jtagaccel_interface =
{
.name = "amt_jtagaccel",
-
+
.execute_queue = amt_jtagaccel_execute_queue,
- .speed = amt_jtagaccel_speed,
+ .speed = amt_jtagaccel_speed,
.register_commands = amt_jtagaccel_register_commands,
.init = amt_jtagaccel_init,
.quit = amt_jtagaccel_quit,
COMMAND_CONFIG, NULL);
register_command(cmd_ctx, NULL, "rtck", amt_jtagaccel_handle_rtck_command,
COMMAND_CONFIG, NULL);
-
+
return ERROR_OK;
}
aw_control_rst |= 0x1;
else if (srst == 0)
aw_control_rst &= ~0x1;
-
+
AMT_AW(aw_control_rst);
}
aw_control_baudrate &= 0xf0;
aw_control_baudrate |= speed & 0x0f;
AMT_AW(aw_control_baudrate);
-
+
return ERROR_OK;
}
{
int timeout = 4096;
u8 ar_status;
-
+
AMT_AR(ar_status);
while (((ar_status) & 0x80) && (timeout-- > 0))
AMT_AR(ar_status);
-
+
if (ar_status & 0x80)
{
LOG_ERROR("amt_jtagaccel timed out while waiting for end of scan, rtck was %s, last AR_STATUS: 0x%2.2x", (rtck_enabled) ? "enabled" : "disabled", ar_status);
{
u8 aw_scan_tms_5;
u8 tms_scan[2];
-
+
tms_scan[0] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][0];
tms_scan[1] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][1];
-
+
aw_scan_tms_5 = 0x40 | (tms_scan[0] & 0x1f);
AMT_AW(aw_scan_tms_5);
if (jtag_speed > 3 || rtck_enabled)
amt_wait_scan_busy();
-
+
if (tms_scan[0] & 0x80)
{
aw_scan_tms_5 = 0x40 | (tms_scan[1] & 0x1f);
if (jtag_speed > 3 || rtck_enabled)
amt_wait_scan_busy();
}
-
+
cur_state = end_state;
}
u8 aw_scan_tms_1to4;
enum tap_state saved_end_state = end_state;
-
+
/* only do a state_move when we're not already in RTI */
- if (cur_state != TAP_RTI)
+ if (cur_state != TAP_IDLE)
{
- amt_jtagaccel_end_state(TAP_RTI);
+ amt_jtagaccel_end_state(TAP_IDLE);
amt_jtagaccel_state_move();
}
-
+
while (num_cycles - i >= 5)
{
aw_scan_tms_5 = 0x40;
AMT_AW(aw_scan_tms_5);
i += 5;
}
-
+
if (num_cycles - i > 0)
{
aw_scan_tms_1to4 = 0x80 | ((num_cycles - i - 1) & 0x3) << 4;
AMT_AW(aw_scan_tms_1to4);
}
-
+
amt_jtagaccel_end_state(saved_end_state);
if (cur_state != end_state)
amt_jtagaccel_state_move();
u8 tms_scan[2];
if (ir_scan)
- amt_jtagaccel_end_state(TAP_SI);
+ amt_jtagaccel_end_state(TAP_IRSHIFT);
else
- amt_jtagaccel_end_state(TAP_SD);
+ amt_jtagaccel_end_state(TAP_DRSHIFT);
amt_jtagaccel_state_move();
amt_jtagaccel_end_state(saved_end_state);
{
aw_tdi_option = 0x30 | (((scan_size - 1) % 8) - 1);
AMT_AW(aw_tdi_option);
-
+
dw_tdi_scan = buf_get_u32(buffer, bit_count, (scan_size - 1) % 8) & 0xff;
AMT_DW(dw_tdi_scan);
if (jtag_speed > 3 || rtck_enabled)
dr_tdo = dr_tdo >> (8 - ((scan_size - 1) % 8));
buf_set_u32(buffer, bit_count, (scan_size - 1) % 8, dr_tdo);
}
-
+
bit_count += (scan_size - 1) % 8;
bits_left -= (scan_size - 1) % 8;
}
-
+
while (bits_left - 1 >= 8)
{
dw_tdi_scan = buf_get_u32(buffer, bit_count, 8) & 0xff;
AMT_DR(dr_tdo);
buf_set_u32(buffer, bit_count, 8, dr_tdo);
}
-
+
bit_count += 8;
bits_left -= 8;
}
-
+
tms_scan[0] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][0];
tms_scan[1] = amt_jtagaccel_tap_move[tap_move_map[cur_state]][tap_move_map[end_state]][1];
aw_tms_scan = 0x40 | (tms_scan[0] & 0x1f) | (buf_get_u32(buffer, bit_count, 1) << 5);
dr_tdo = dr_tdo >> 7;
buf_set_u32(buffer, bit_count, 1, dr_tdo);
}
-
+
if (tms_scan[0] & 0x80)
{
aw_tms_scan = 0x40 | (tms_scan[1] & 0x1f);
enum scan_type type;
u8 *buffer;
int retval;
-
+
/* return ERROR_OK, unless a jtag_read_buffer returns a failed check
* that wasn't handled by a caller-provided error handler
- */
+ */
retval = ERROR_OK;
-
+
while (cmd)
{
switch (cmd->type)
#endif
if (cmd->cmd.reset->trst == 1)
{
- cur_state = TAP_TLR;
+ cur_state = TAP_RESET;
}
amt_jtagaccel_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
}
cmd = cmd->next;
}
-
+
return retval;
}
version.dwOSVersionInfoSize = sizeof version;
if (!GetVersionEx( &version )) {
- errno = EINVAL;
- return -1;
+ errno = EINVAL;
+ return -1;
}
if (version.dwPlatformId != VER_PLATFORM_WIN32_NT)
- return 0;
+ return 0;
h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
if (h == INVALID_HANDLE_VALUE) {
- errno = ENODEV;
- return -1;
+ errno = ENODEV;
+ return -1;
}
CloseHandle( h );
u8 status_port;
#endif
u8 ar_status;
-
+
#if PARPORT_USE_PPDEV == 1
if (device_handle > 0)
{
snprintf(buffer, 256, "/dev/parport%d", amt_jtagaccel_port);
device_handle = open(buffer, O_RDWR);
-
+
if (device_handle < 0)
{
LOG_ERROR("cannot open device. check it exists and that user read and write rights are set");
LOG_ERROR(" cannot set compatible mode to device");
return ERROR_JTAG_INIT_FAILED;
}
-
+
control_port = 0x00;
i = ioctl(device_handle, PPWCONTROL, &control_port);
#if PARPORT_USE_GIVEIO == 1
if (amt_jtagaccel_get_giveio_access() != 0) {
-#else /* PARPORT_USE_GIVEIO */
+#else /* PARPORT_USE_GIVEIO */
if (ioperm(amt_jtagaccel_port, 5, 1) != 0) {
#endif /* PARPORT_USE_GIVEIO */
LOG_ERROR("missing privileges for direct i/o");
return ERROR_JTAG_INIT_FAILED;
}
-
+
/* prepare epp port */
/* clear timeout */
status_port = inb(amt_jtagaccel_port + 1);
outb(status_port | 0x1, amt_jtagaccel_port + 1);
-
+
/* reset epp port */
outb(0x00, amt_jtagaccel_port + 2);
outb(0x04, amt_jtagaccel_port + 2);
#endif
-
+
if (rtck_enabled)
- {
+ {
/* set RTCK enable bit */
aw_control_fsm |= 0x02;
}
-
+
/* enable JTAG port */
aw_control_fsm |= 0x04;
AMT_AW(aw_control_fsm);
-
+
amt_jtagaccel_speed(jtag_speed);
-
+
if (jtag_reset_config & RESET_TRST_OPEN_DRAIN)
aw_control_rst &= ~0x8;
else
aw_control_rst |= 0x8;
-
+
if (jtag_reset_config & RESET_SRST_PUSH_PULL)
aw_control_rst &= ~0x2;
else
aw_control_rst |= 0x2;
-
+
amt_jtagaccel_reset(0, 0);
-
+
/* read status register */
AMT_AR(ar_status);
LOG_DEBUG("AR_STATUS: 0x%2.2x", ar_status);
-
+
return ERROR_OK;
}
int amt_jtagaccel_quit(void)
{
-
+
return ERROR_OK;
}
rtck_enabled = 0;
}
}
-
+
return ERROR_OK;
}
/* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
- *
+ *
* Set this to 1 and str912 reset halt will fail.
- *
+ *
* If someone can submit a patch with an explanation it will be greatly
* appreciated, but as far as I can tell (ØH) DCLK is generated upon
- * clk=0 in TAP_RTI. Good luck deducing that from the ARM documentation!
- * The ARM documentation uses the term "DCLK is asserted while in the TAP_RTI
+ * clk=0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
+ * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
* state". With hardware there is no such thing as *while* in a state. There
* are only edges. So clk => 0 is in fact a very subtle state transition that
- * happens *while* in the TAP_RTI state. "#&¤"#¤&"#&"#&
- *
+ * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
+ *
* For "reset halt" the last thing that happens before srst is asserted
* is that the breakpoint is set up. If DCLK is not wiggled one last
* time before the reset, then the breakpoint is not set up and
* "reset halt" will fail to halt.
- *
+ *
*/
-#define CLOCK_IDLE() 0
+#define CLOCK_IDLE() 0
int bitbang_execute_queue(void);
}
void bitbang_state_move(void) {
-
+
int i=0, tms=0;
u8 tms_scan = TAP_MOVE(cur_state, end_state);
-
+
for (i = 0; i < 7; i++)
{
tms = (tms_scan >> i) & 1;
bitbang_interface->write(1, tms, 0);
}
bitbang_interface->write(CLOCK_IDLE(), tms, 0);
-
+
cur_state = end_state;
}
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[cmd->path[state_count]]);
exit(-1);
}
-
+
bitbang_interface->write(0, tms, 0);
bitbang_interface->write(1, tms, 0);
state_count++;
num_states--;
}
-
+
bitbang_interface->write(CLOCK_IDLE(), tms, 0);
end_state = cur_state;
void bitbang_runtest(int num_cycles)
{
int i;
-
+
enum tap_state saved_end_state = end_state;
-
+
/* only do a state_move when we're not already in RTI */
- if (cur_state != TAP_RTI)
+ if (cur_state != TAP_IDLE)
{
- bitbang_end_state(TAP_RTI);
+ bitbang_end_state(TAP_IDLE);
bitbang_state_move();
}
-
+
/* execute num_cycles */
for (i = 0; i < num_cycles; i++)
{
bitbang_interface->write(1, 0, 0);
}
bitbang_interface->write(CLOCK_IDLE(), 0, 0);
-
+
/* finish in end_state */
bitbang_end_state(saved_end_state);
if (cur_state != end_state)
{
enum tap_state saved_end_state = end_state;
int bit_cnt;
-
- if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
+
+ if (!((!ir_scan && (cur_state == TAP_DRSHIFT)) || (ir_scan && (cur_state == TAP_IRSHIFT))))
{
if (ir_scan)
- bitbang_end_state(TAP_SI);
+ bitbang_end_state(TAP_IRSHIFT);
else
- bitbang_end_state(TAP_SD);
+ bitbang_end_state(TAP_DRSHIFT);
bitbang_state_move();
bitbang_end_state(saved_end_state);
/* if we're just reading the scan, but don't care about the output
* default to outputting 'low', this also makes valgrind traces more readable,
* as it removes the dependency on an uninitialised value
- */
+ */
tdi=0;
if ((type != SCAN_IN) && (buffer[bytec] & bcval))
tdi=1;
val=bitbang_interface->read();
bitbang_interface->write(1, tms, tdi);
-
+
if (type != SCAN_OUT)
{
if (val)
buffer[bytec] &= ~bcval;
}
}
-
- /* TAP_SD & TAP_SI are illegal end states, so we always transition to the pause
+
+ /* TAP_DRSHIFT & TAP_IRSHIFT are illegal end states, so we always transition to the pause
* state which is a legal stable state from which statemove will work.
- *
- * Exit1 -> Pause
+ *
+ * Exit1 -> Pause
*/
bitbang_interface->write(0, 0, 0);
bitbang_interface->write(1, 0, 0);
bitbang_interface->write(CLOCK_IDLE(), 0, 0);
-
+
if (ir_scan)
- cur_state = TAP_PI;
+ cur_state = TAP_IRPAUSE;
else
- cur_state = TAP_PD;
-
+ cur_state = TAP_DRPAUSE;
+
if (cur_state != end_state)
bitbang_state_move();
}
enum scan_type type;
u8 *buffer;
int retval;
-
+
if (!bitbang_interface)
{
LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
exit(-1);
}
-
+
/* return ERROR_OK, unless a jtag_read_buffer returns a failed check
* that wasn't handled by a caller-provided error handler
- */
+ */
retval = ERROR_OK;
-
+
if(bitbang_interface->blink)
bitbang_interface->blink(1);
#endif
if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
{
- cur_state = TAP_TLR;
+ cur_state = TAP_RESET;
}
bitbang_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
}
if(bitbang_interface->blink)
bitbang_interface->blink(0);
-
+
return retval;
}
int i;
/* only do a state_move when we're not already in RTI */
- if (cur_state != TAP_RTI) bitq_state_move(TAP_RTI);
+ if (cur_state != TAP_IDLE) bitq_state_move(TAP_IDLE);
/* execute num_cycles */
for (i = 0; i < num_cycles; i++)
if (pause) {
bitq_io(0,0,0);
- if (cur_state==TAP_SI) cur_state=TAP_PI;
- else if (cur_state==TAP_SD) cur_state=TAP_PD;
+ if (cur_state==TAP_IRSHIFT) cur_state=TAP_IRPAUSE;
+ else if (cur_state==TAP_DRSHIFT) cur_state=TAP_DRPAUSE;
}
}
{
int i;
- if (cmd->ir_scan) bitq_state_move(TAP_SI);
- else bitq_state_move(TAP_SD);
+ if (cmd->ir_scan) bitq_state_move(TAP_IRSHIFT);
+ else bitq_state_move(TAP_DRSHIFT);
for (i=0; i < cmd->num_fields-1; i++)
bitq_scan_field(&cmd->fields[i], 0);
#endif
if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
{
- cur_state = TAP_TLR;
+ cur_state = TAP_RESET;
}
bitq_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
if (bitq_interface->in_rdy()) bitq_in_proc();
#define BUFFER_ADD ft2232_buffer[ft2232_buffer_size++]
#define BUFFER_READ ft2232_buffer[ft2232_read_pointer++]
-jtag_interface_t ft2232_interface =
+jtag_interface_t ft2232_interface =
{
.name = "ft2232",
.execute_queue = ft2232_execute_queue,
.speed = ft2232_speed,
.speed_div = ft2232_speed_div,
- .khz = ft2232_khz,
+ .khz = ft2232_khz,
.register_commands = ft2232_register_commands,
.init = ft2232_init,
.quit = ft2232_quit,
else
{
*bytes_written = dw_bytes_written;
- return ERROR_OK;
+ return ERROR_OK;
}
#elif BUILD_FT2232_LIBFTDI == 1
int retval;
else
{
*bytes_written = retval;
- return ERROR_OK;
+ return ERROR_OK;
}
#endif
}
while ((*bytes_read < size) && timeout--)
{
- if ((status = FT_Read(ftdih, buf + *bytes_read, size -
- *bytes_read, &dw_bytes_read)) != FT_OK)
+ if ((status = FT_Read(ftdih, buf + *bytes_read, size -
+ *bytes_read, &dw_bytes_read)) != FT_OK)
{
- *bytes_read = 0;
+ *bytes_read = 0;
LOG_ERROR("FT_Read returned: %lu", status);
return ERROR_JTAG_DEVICE_ERROR;
}
- *bytes_read += dw_bytes_read;
+ *bytes_read += dw_bytes_read;
}
#elif BUILD_FT2232_LIBFTDI == 1
int retval;
int timeout = 100;
*bytes_read = 0;
-
+
while ((*bytes_read < size) && timeout--)
{
if ((retval = ftdi_read_data(&ftdic, buf + *bytes_read, size - *bytes_read)) < 0)
LOG_ERROR("couldn't read the requested number of bytes from FT2232 device (%i < %i)", *bytes_read, size);
return ERROR_JTAG_DEVICE_ERROR;
}
-
+
return ERROR_OK;
}
buf[0] = 0x86; /* command "set divisor" */
buf[1] = speed & 0xff; /* valueL (0=6MHz, 1=3MHz, 2=2.0MHz, ...*/
buf[2] = (speed >> 8) & 0xff; /* valueH */
-
+
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
if (((retval = ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
int ft2232_speed_div(int speed, int *khz)
{
- /* Take a look in the FT2232 manual,
+ /* Take a look in the FT2232 manual,
* AN2232C-01 Command Processor for
* MPSSE and MCU Host Bus. Chapter 3.8 */
-
+
*khz = 6000 / (1+speed);
-
+
return ERROR_OK;
}
LOG_ERROR("RCLK not supported");
return ERROR_FAIL;
}
- /* Take a look in the FT2232 manual,
+ /* Take a look in the FT2232 manual,
* AN2232C-01 Command Processor for
* MPSSE and MCU Host Bus. Chapter 3.8
- *
+ *
* We will calc here with a multiplier
* of 10 for better rounding later. */
-
+
/* Calc speed, (6000 / khz) - 1 */
/* Use 65000 for better rounding */
*jtag_speed = (60000 / khz) - 10;
-
+
/* Add 0.9 for rounding */
*jtag_speed += 9;
-
+
/* Calc real speed */
*jtag_speed = *jtag_speed / 10;
-
+
/* Check if speed is greater than 0 */
if (*jtag_speed < 0)
{
*jtag_speed = 0;
}
-
+
/* Check max value */
if (*jtag_speed > 0xFFFF)
{
*jtag_speed = 0xFFFF;
}
-
+
return ERROR_OK;
}
int i;
char line[256];
char *line_p = line;
-
+
for (i = 0; i < ft2232_buffer_size; i++)
{
line_p += snprintf(line_p, 256 - (line_p - line), "%2.2x ", ft2232_buffer[i]);
line_p = line;
}
}
-
+
if (line_p != line)
LOG_DEBUG("%s", line);
}
int retval;
u32 bytes_written;
u32 bytes_read;
-
+
#ifdef _DEBUG_USB_IO_
struct timeval start, inter, inter2, end;
struct timeval d_inter, d_inter2, d_end;
#endif
#ifdef _DEBUG_USB_IO_
- gettimeofday(&start, NULL);
+ gettimeofday(&start, NULL);
#endif
if ((retval = ft2232_write(ft2232_buffer, ft2232_buffer_size, &bytes_written)) != ERROR_OK)
LOG_ERROR("couldn't write MPSSE commands to FT2232");
return retval;
}
-
+
#ifdef _DEBUG_USB_IO_
- gettimeofday(&inter, NULL);
+ gettimeofday(&inter, NULL);
#endif
-
+
if (ft2232_expect_read)
{
int timeout = 100;
ft2232_buffer_size = 0;
-
+
#ifdef _DEBUG_USB_IO_
- gettimeofday(&inter2, NULL);
+ gettimeofday(&inter2, NULL);
#endif
-
+
if ((retval = ft2232_read(ft2232_buffer, ft2232_expect_read, &bytes_read)) != ERROR_OK)
{
LOG_ERROR("couldn't read from FT2232");
return retval;
}
-
+
#ifdef _DEBUG_USB_IO_
- gettimeofday(&end, NULL);
+ gettimeofday(&end, NULL);
timeval_subtract(&d_inter, &inter, &start);
timeval_subtract(&d_inter2, &inter2, &start);
LOG_INFO("inter: %i.%i, inter2: %i.%i end: %i.%i", d_inter.tv_sec, d_inter.tv_usec, d_inter2.tv_sec, d_inter2.tv_usec, d_end.tv_sec, d_end.tv_usec);
#endif
-
-
+
+
ft2232_buffer_size = bytes_read;
-
+
if (ft2232_expect_read != ft2232_buffer_size)
{
LOG_ERROR("ft2232_expect_read (%i) != ft2232_buffer_size (%i) (%i retries)", ft2232_expect_read, ft2232_buffer_size, 100 - timeout);
- ft2232_debug_dump_buffer();
+ ft2232_debug_dump_buffer();
exit(-1);
}
ft2232_expect_read = 0;
ft2232_read_pointer = 0;
-
+
/* return ERROR_OK, unless a jtag_read_buffer returns a failed check
* that wasn't handled by a caller-provided error handler
- */
+ */
retval = ERROR_OK;
-
+
cmd = first;
while (cmd != last)
{
}
cmd = cmd->next;
}
-
+
ft2232_buffer_size = 0;
return retval;
while (num_states)
{
int bit_count = 0;
-
+
int num_states_batch = num_states > 7 ? 7 : num_states;
tms_byte = 0x0;
BUFFER_ADD = 0x4b;
/* number of states remaining */
BUFFER_ADD = num_states_batch - 1;
-
+
while (num_states_batch--)
{
if (tap_transitions[cur_state].low == cmd->path[state_count])
state_count++;
num_states--;
}
-
+
BUFFER_ADD = tms_byte;
}
-
+
end_state = cur_state;
}
int cur_byte = 0;
int last_bit;
- if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
+ if (!((!ir_scan && (cur_state == TAP_DRSHIFT)) || (ir_scan && (cur_state == TAP_IRSHIFT))))
{
/* command "Clock Data to TMS/CS Pin (no Read)" */
BUFFER_ADD = 0x4b;
/* TMS data bits */
if (ir_scan)
{
- BUFFER_ADD = TAP_MOVE(cur_state, TAP_SI);
- cur_state = TAP_SI;
+ BUFFER_ADD = TAP_MOVE(cur_state, TAP_IRSHIFT);
+ cur_state = TAP_IRSHIFT;
}
else
{
- BUFFER_ADD = TAP_MOVE(cur_state, TAP_SD);
- cur_state = TAP_SD;
+ BUFFER_ADD = TAP_MOVE(cur_state, TAP_DRSHIFT);
+ cur_state = TAP_DRSHIFT;
}
/* LOG_DEBUG("added TMS scan (no read)"); */
}
-
+
/* add command for complete bytes */
while (num_bytes > 1)
{
bits_left -= 8 * (thisrun_bytes);
}
}
-
+
/* the most signifcant bit is scanned during TAP movement */
if (type != SCAN_IN)
last_bit = (buffer[cur_byte] >> (bits_left - 1)) & 0x1;
BUFFER_ADD = buffer[cur_byte];
}
- if ((ir_scan && (end_state == TAP_SI)) ||
- (!ir_scan && (end_state == TAP_SD)))
+ if ((ir_scan && (end_state == TAP_IRSHIFT)) ||
+ (!ir_scan && (end_state == TAP_DRSHIFT)))
{
if (type == SCAN_IO)
{
u32 bytes_read;
int retval;
int thisrun_read = 0;
-
+
if (cmd->ir_scan)
{
LOG_ERROR("BUG: large IR scans are not supported");
exit(-1);
}
- if (cur_state != TAP_SD)
+ if (cur_state != TAP_DRSHIFT)
{
/* command "Clock Data to TMS/CS Pin (no Read)" */
BUFFER_ADD = 0x4b;
/* scan 7 bit */
BUFFER_ADD = 0x6;
/* TMS data bits */
- BUFFER_ADD = TAP_MOVE(cur_state, TAP_SD);
- cur_state = TAP_SD;
+ BUFFER_ADD = TAP_MOVE(cur_state, TAP_DRSHIFT);
+ cur_state = TAP_DRSHIFT;
}
-
+
if ((retval = ft2232_write(ft2232_buffer, ft2232_buffer_size, &bytes_written)) != ERROR_OK)
{
LOG_ERROR("couldn't write MPSSE commands to FT2232");
}
LOG_DEBUG("ft2232_buffer_size: %i, bytes_written: %i", ft2232_buffer_size, bytes_written);
ft2232_buffer_size = 0;
-
+
/* add command for complete bytes */
while (num_bytes > 1)
{
int thisrun_bytes;
-
+
if (type == SCAN_IO)
{
/* Clock Data Bytes In and Out LSB First */
}
LOG_DEBUG("ft2232_buffer_size: %i, bytes_written: %i", ft2232_buffer_size, bytes_written);
ft2232_buffer_size = 0;
-
+
if (type != SCAN_OUT)
{
if ((retval = ft2232_read(receive_pointer, thisrun_read, &bytes_read)) != ERROR_OK)
receive_pointer += bytes_read;
}
}
-
+
thisrun_read = 0;
-
+
/* the most signifcant bit is scanned during TAP movement */
if (type != SCAN_IN)
last_bit = (buffer[cur_byte] >> (bits_left - 1)) & 0x1;
BUFFER_ADD = bits_left - 2;
if (type != SCAN_IN)
BUFFER_ADD = buffer[cur_byte];
-
+
if (type != SCAN_OUT)
thisrun_read += 2;
}
- if (end_state == TAP_SD)
+ if (end_state == TAP_DRSHIFT)
{
if (type == SCAN_IO)
{
BUFFER_ADD = TAP_MOVE(cur_state, end_state) | (last_bit << 7);
cur_state = end_state;
}
-
+
if (type != SCAN_OUT)
thisrun_read += 1;
-
+
if ((retval = ft2232_write(ft2232_buffer, ft2232_buffer_size, &bytes_written)) != ERROR_OK)
{
LOG_ERROR("couldn't write MPSSE commands to FT2232");
}
LOG_DEBUG("ft2232_buffer_size: %i, bytes_written: %i", ft2232_buffer_size, bytes_written);
ft2232_buffer_size = 0;
-
+
if (type != SCAN_OUT)
{
if ((retval = ft2232_read(receive_pointer, thisrun_read, &bytes_read)) != ERROR_OK)
LOG_DEBUG("thisrun_read: %i, bytes_read: %i", thisrun_read, bytes_read);
receive_pointer += bytes_read;
}
-
+
return ERROR_OK;
}
{
int predicted_size = 3;
int num_bytes = (scan_size - 1) / 8;
-
- if (cur_state != TAP_SD)
+
+ if (cur_state != TAP_DRSHIFT)
predicted_size += 3;
-
+
if (type == SCAN_IN) /* only from device to host */
{
/* complete bytes */
int ft2232_predict_scan_in(int scan_size, enum scan_type type)
{
int predicted_size = 0;
-
+
if (type != SCAN_OUT)
{
/* complete bytes */
/* last bit (from TMS scan) */
predicted_size += 1;
}
-
+
/* LOG_DEBUG("scan_size: %i, predicted_size: %i", scan_size, predicted_size); */
return predicted_size;
else
low_direction &= ~nSRSTnOE; /* switch to input pin (high-Z) */
}
-
+
/* command "set data bits low byte" */
BUFFER_ADD = 0x80;
BUFFER_ADD = low_output;
else
high_output |= nSRSTnOE;
}
-
+
/* command "set data bits high byte" */
BUFFER_ADD = 0x82;
BUFFER_ADD = high_output;
{
if (trst == 1)
{
- cur_state = TAP_TLR;
+ cur_state = TAP_RESET;
high_output &= ~nTRST;
}
else if (trst == 0)
void turtle_reset(int trst, int srst)
{
trst = trst;
-
+
if (srst == 1)
{
low_output |= nSRST;
{
low_output &= ~nSRST;
}
-
+
/* command "set data bits low byte" */
BUFFER_ADD = 0x80;
BUFFER_ADD = low_output;
{
high_output |= nSRST;
}
-
+
/* command "set data bits high byte" */
BUFFER_ADD = 0x82;
BUFFER_ADD = high_output;
{
low_output |= nSRST;
}
-
+
/* command "set data bits low byte" */
BUFFER_ADD = 0x80;
BUFFER_ADD = low_output;
BUFFER_ADD = low_direction;
-
+
/* command "set data bits high byte" */
BUFFER_ADD = 0x82;
BUFFER_ADD = high_output;
int predicted_size = 0;
int require_send = 0;
int retval;
-
+
/* return ERROR_OK, unless ft2232_send_and_recv reports a failed check
* that wasn't handled by a caller-provided error handler
- */
+ */
retval = ERROR_OK;
ft2232_buffer_size = 0;
ft2232_expect_read = 0;
-
+
/* blink, if the current layout has that feature */
if (layout->blink)
layout->blink();
if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
{
- cur_state = TAP_TLR;
+ cur_state = TAP_RESET;
}
layout->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
require_send = 1;
-
-#ifdef _DEBUG_JTAG_IO_
+
+#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("trst: %i, srst: %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);
#endif
break;
case JTAG_RUNTEST:
/* only send the maximum buffer size that FT2232C can handle */
predicted_size = 0;
- if (cur_state != TAP_RTI)
+ if (cur_state != TAP_IDLE)
predicted_size += 3;
predicted_size += 3 * CEIL(cmd->cmd.runtest->num_cycles, 7);
- if ((cmd->cmd.runtest->end_state != -1) && (cmd->cmd.runtest->end_state != TAP_RTI))
+ if ((cmd->cmd.runtest->end_state != -1) && (cmd->cmd.runtest->end_state != TAP_IDLE))
predicted_size += 3;
- if ((cmd->cmd.runtest->end_state == -1) && (end_state != TAP_RTI))
+ if ((cmd->cmd.runtest->end_state == -1) && (end_state != TAP_IDLE))
predicted_size += 3;
if (ft2232_buffer_size + predicted_size + 1 > FT2232_BUFFER_SIZE)
{
require_send = 0;
first_unsent = cmd;
}
- if (cur_state != TAP_RTI)
+ if (cur_state != TAP_IDLE)
{
/* command "Clock Data to TMS/CS Pin (no Read)" */
BUFFER_ADD = 0x4b;
/* scan 7 bit */
BUFFER_ADD = 0x6;
/* TMS data bits */
- BUFFER_ADD = TAP_MOVE(cur_state, TAP_RTI);
- cur_state = TAP_RTI;
+ BUFFER_ADD = TAP_MOVE(cur_state, TAP_IDLE);
+ cur_state = TAP_IDLE;
require_send = 1;
}
i = cmd->cmd.runtest->num_cycles;
BUFFER_ADD = (i > 7) ? 6 : (i - 1);
/* TMS data bits */
BUFFER_ADD = 0x0;
- cur_state = TAP_RTI;
+ cur_state = TAP_IDLE;
i -= (i > 7) ? 7 : i;
/* LOG_DEBUG("added TMS scan (no read)"); */
}
/* LOG_DEBUG("added TMS scan (no read)"); */
}
require_send = 1;
-#ifdef _DEBUG_JTAG_IO_
+#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("runtest: %i, end in %i", cmd->cmd.runtest->num_cycles, end_state);
#endif
break;
/* LOG_DEBUG("added TMS scan (no read)"); */
cur_state = end_state;
require_send = 1;
-#ifdef _DEBUG_JTAG_IO_
+#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("statemove: %i", end_state);
#endif
break;
}
ft2232_add_pathmove(cmd->cmd.pathmove);
require_send = 1;
-#ifdef _DEBUG_JTAG_IO_
+#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("pathmove: %i states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]);
#endif
break;
if (first_unsent != cmd)
if (ft2232_send_and_recv(first_unsent, cmd) != ERROR_OK)
retval = ERROR_JTAG_QUEUE_FAILED;
-
+
/* current command */
if (cmd->cmd.scan->end_state != -1)
ft2232_end_state(cmd->cmd.scan->end_state);
require_send = 1;
if (buffer)
free(buffer);
-#ifdef _DEBUG_JTAG_IO_
+#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("%s scan, %i bit, end in %i", (cmd->cmd.scan->ir_scan) ? "IR" : "DR", scan_size, end_state);
#endif
break;
retval = ERROR_JTAG_QUEUE_FAILED;
first_unsent = cmd->next;
jtag_sleep(cmd->cmd.sleep->us);
-#ifdef _DEBUG_JTAG_IO_
+#ifdef _DEBUG_JTAG_IO_
LOG_DEBUG("sleep %i usec", cmd->cmd.sleep->us);
#endif
break;
LOG_WARNING("can't open by device description and serial number, giving precedence to serial");
ft2232_device_desc = NULL;
}
-
+
if (ft2232_device_desc)
{
openex_string = ft2232_device_desc;
{
LOG_ERROR("neither device description nor serial number specified");
LOG_ERROR("please add \"ft2232_device_desc <string>\" or \"ft2232_serial <string>\" to your .cfg file");
-
- return ERROR_JTAG_INIT_FAILED;
+
+ return ERROR_JTAG_INIT_FAILED;
}
if ((status = FT_OpenEx(openex_string, openex_flags, &ftdih)) != FT_OK)
{
DWORD num_devices;
-
+
if (more) {
LOG_WARNING("unable to open ftdi device (trying more): %lu", status);
*try_more = 1;
for (i = 0; i < num_devices; i++)
LOG_ERROR("%i: %s", i, desc_array[i]);
}
-
+
for (i = 0; i < num_devices; i++)
free(desc_array[i]);
free(desc_array);
LOG_ERROR("unable to set latency timer: %lu", status);
return ERROR_JTAG_INIT_FAILED;
}
-
+
if ((status = FT_GetLatencyTimer(ftdih, &latency_timer)) != FT_OK)
{
LOG_ERROR("unable to get latency timer: %lu", status);
{
LOG_DEBUG("current latency timer: %i", latency_timer);
}
-
+
if ((status = FT_SetTimeouts(ftdih, 5000, 5000)) != FT_OK)
{
LOG_ERROR("unable to set timeouts: %lu", status);
LOG_ERROR("unable to set latency timer");
return ERROR_JTAG_INIT_FAILED;
}
-
+
if (ftdi_get_latency_timer(&ftdic, &latency_timer) < 0)
{
LOG_ERROR("unable to get latency timer");
u32 bytes_written;
ft2232_layout_t *cur_layout = ft2232_layouts;
int i;
-
+
if ((ft2232_layout == NULL) || (ft2232_layout[0] == 0))
{
ft2232_layout = "usbjtag";
LOG_WARNING("No ft2232 layout specified, using default 'usbjtag'");
}
-
+
while (cur_layout->name)
{
if (strcmp(cur_layout->name, ft2232_layout) == 0)
LOG_ERROR("No matching layout found for %s", ft2232_layout);
return ERROR_JTAG_INIT_FAILED;
}
-
+
for (i = 0; 1; i++) {
/*
* "more indicates that there are more IDs to try, so we should
#elif BUILD_FT2232_LIBFTDI == 1
retval = ft2232_init_libftdi(ft2232_vid[i], ft2232_pid[i],
more, &try_more);
-#endif
+#endif
if (retval >= 0)
break;
if (!more || !try_more)
return ft2232_purge_ftd2xx();
#elif BUILD_FT2232_LIBFTDI == 1
return ft2232_purge_libftdi();
-#endif
+#endif
return ERROR_OK;
}
{
u8 buf[3];
u32 bytes_written;
-
+
low_output = 0x08;
low_direction = 0x0b;
-
+
if (strcmp(ft2232_layout, "usbjtag") == 0)
{
nTRST = 0x10;
else
{
LOG_ERROR("BUG: usbjtag_init called for unknown layout '%s'", ft2232_layout);
- return ERROR_JTAG_INIT_FAILED;
+ return ERROR_JTAG_INIT_FAILED;
}
-
+
if (jtag_reset_config & RESET_TRST_OPEN_DRAIN)
{
low_direction &= ~nTRSTnOE; /* nTRST input */
low_direction |= nTRSTnOE; /* nTRST output */
low_output |= nTRST; /* nTRST = 1 */
}
-
+
if (jtag_reset_config & RESET_SRST_PUSH_PULL)
{
low_direction |= nSRSTnOE; /* nSRST output */
low_direction &= ~nSRSTnOE; /* nSRST input */
low_output &= ~nSRST; /* nSRST = 0 */
}
-
+
/* initialize low byte for jtag */
buf[0] = 0x80; /* command "set data bits low byte" */
buf[1] = low_output; /* value (TMS=1,TCK=0, TDI=0, xRST high) */
buf[2] = low_direction; /* dir (output=1), TCK/TDI/TMS=out, TDO=in */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'USBJTAG' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'USBJTAG' layout");
return ERROR_JTAG_INIT_FAILED;
}
{
u8 buf[3];
u32 bytes_written;
-
+
low_output = 0x08;
low_direction = 0x2b;
-
+
/* initialize low byte for jtag */
buf[0] = 0x80; /* command "set data bits low byte" */
buf[1] = low_output; /* value (TMS=1,TCK=0, TDI=0, nOE=0) */
buf[2] = low_direction; /* dir (output=1), TCK/TDI/TMS=out, TDO=in, nOE=out */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
return ERROR_JTAG_INIT_FAILED;
}
nTRST = 0x08;
nTRSTnOE = 0x0; /* No output enable for TRST*/
nSRST = 0x04;
- nSRSTnOE = 0x0; /* No output enable for SRST*/
+ nSRSTnOE = 0x0; /* No output enable for SRST*/
}
else
{
LOG_ERROR("BUG: axm0432_jtag_init called for non axm0432 layout");
exit(-1);
}
-
+
high_output = 0x0;
high_direction = 0x0c;
{
high_output |= nSRST;
}
-
+
/* initialize high port */
buf[0] = 0x82; /* command "set data bits high byte" */
buf[1] = high_output; /* value */
buf[2] = high_direction; /* all outputs (xRST and xRSTnOE) */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'Dicarlo' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'Dicarlo' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
return ERROR_OK;
}
{
u8 buf[3];
u32 bytes_written;
-
+
low_output = 0x08;
low_direction = 0x1b;
-
+
/* initialize low byte for jtag */
buf[0] = 0x80; /* command "set data bits low byte" */
buf[1] = low_output; /* value (TMS=1,TCK=0, TDI=0, nOE=0) */
buf[2] = low_direction; /* dir (output=1), TCK/TDI/TMS=out, TDO=in, nOE=out */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
if (strcmp(layout->name, "jtagkey") == 0)
{
nTRST = 0x01;
LOG_ERROR("BUG: jtagkey_init called for non jtagkey layout");
exit(-1);
}
-
+
high_output = 0x0;
high_direction = 0x0f;
high_output &= ~nTRSTnOE;
high_output |= nTRST;
}
-
+
if (jtag_reset_config & RESET_SRST_PUSH_PULL)
{
high_output &= ~nSRSTnOE;
high_output |= nSRSTnOE;
high_output &= ~nSRST;
}
-
+
/* initialize high port */
buf[0] = 0x82; /* command "set data bits high byte" */
buf[1] = high_output; /* value */
buf[2] = high_direction; /* all outputs (xRST and xRSTnOE) */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
return ERROR_OK;
}
{
u8 buf[3];
u32 bytes_written;
-
+
low_output = 0x08;
low_direction = 0x1b;
-
+
/* initialize low byte for jtag */
buf[0] = 0x80; /* command "set data bits low byte" */
buf[1] = low_output; /* value (TMS=1,TCK=0, TDI=0, nOE=0) */
buf[2] = low_direction; /* dir (output=1), TCK/TDI/TMS=out, TDO=in, nOE=out */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
nTRST = 0x01;
nTRSTnOE = 0x4;
nSRST = 0x02;
high_output &= ~nTRSTnOE;
high_output |= nTRST;
}
-
+
if (jtag_reset_config & RESET_SRST_PUSH_PULL)
{
LOG_ERROR("can't set nSRST to push-pull on the Olimex ARM-USB-OCD");
{
high_output &= ~nSRST;
}
-
+
/* turn red LED on */
high_output |= 0x08;
-
+
/* initialize high port */
buf[0] = 0x82; /* command "set data bits high byte" */
buf[1] = high_output; /* value */
buf[2] = high_direction; /* all outputs (xRST and xRSTnOE) */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'JTAGkey' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
return ERROR_OK;
}
{
u8 buf[3];
u32 bytes_written;
-
+
low_output = 0x18;
low_direction = 0xfb;
-
+
/* initialize low byte for jtag */
buf[0] = 0x80; /* command "set data bits low byte" */
buf[1] = low_output; /* value (TMS=1,TCK=0, TDI=0, nOE=0) */
buf[2] = low_direction; /* dir (output=1), TCK/TDI/TMS=out, TDO=in, nOE[12]=out, n[ST]srst=out */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'flyswatter' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'flyswatter' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
nTRST = 0x10;
nTRSTnOE = 0x0; /* not output enable for nTRST */
nSRST = 0x20;
/* turn red LED1 on, LED2 off */
high_output |= 0x08;
-
+
/* initialize high port */
buf[0] = 0x82; /* command "set data bits high byte" */
buf[1] = high_output; /* value */
buf[2] = high_direction; /* all outputs (xRST and xRSTnOE) */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'flyswatter' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'flyswatter' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
return ERROR_OK;
}
{
u8 buf[3];
u32 bytes_written;
-
+
low_output = 0x08;
low_direction = 0x5b;
-
+
/* initialize low byte for jtag */
buf[0] = 0x80; /* command "set data bits low byte" */
buf[1] = low_output; /* value (TMS=1,TCK=0, TDI=0, nOE=0) */
buf[2] = low_direction; /* dir (output=1), TCK/TDI/TMS=out, TDO=in, nOE=out */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'turtelizer2' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'turtelizer2' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
nSRST = 0x40;
-
+
high_output = 0x00;
high_direction = 0x0C;
-
+
/* initialize high port */
buf[0] = 0x82; /* command "set data bits high byte" */
buf[1] = high_output;
buf[2] = high_direction;
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'turtelizer2' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'turtelizer2' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
return ERROR_OK;
}
{
u8 buf[3];
u32 bytes_written;
-
+
low_output = 0x08;
low_direction = 0x0b;
-
+
/* initialize low byte for jtag */
buf[0] = 0x80; /* command "set data bits low byte" */
buf[1] = low_output; /* value (TMS=1,TCK=0, TDI=0, nOE=0) */
buf[2] = low_direction; /* dir (output=1), TCK/TDI/TMS=out, TDO=in, nOE=out */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'comstick' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'comstick' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
nTRST = 0x01;
nTRSTnOE = 0x00; /* no output enable for nTRST */
nSRST = 0x02;
nSRSTnOE = 0x00; /* no output enable for nSRST */
-
+
high_output = 0x03;
high_direction = 0x03;
-
+
/* initialize high port */
buf[0] = 0x82; /* command "set data bits high byte" */
buf[1] = high_output;
buf[2] = high_direction;
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'comstick' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'comstick' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
return ERROR_OK;
}
{
u8 buf[3];
u32 bytes_written;
-
+
low_output = 0x88;
low_direction = 0x8b;
-
+
/* initialize low byte for jtag */
buf[0] = 0x80; /* command "set data bits low byte" */
buf[1] = low_output; /* value (TMS=1,TCK=0, TDI=0, nOE=0) */
buf[2] = low_direction; /* dir (output=1), TCK/TDI/TMS=out, TDO=in, nOE=out */
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'stm32stick' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'stm32stick' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
nTRST = 0x01;
nTRSTnOE = 0x00; /* no output enable for nTRST */
nSRST = 0x80;
nSRSTnOE = 0x00; /* no output enable for nSRST */
-
+
high_output = 0x01;
high_direction = 0x03;
-
+
/* initialize high port */
buf[0] = 0x82; /* command "set data bits high byte" */
buf[1] = high_output;
buf[2] = high_direction;
LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
-
+
if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
{
- LOG_ERROR("couldn't initialize FT2232 with 'stm32stick' layout");
+ LOG_ERROR("couldn't initialize FT2232 with 'stm32stick' layout");
return ERROR_JTAG_INIT_FAILED;
}
-
+
return ERROR_OK;
}
/* set port pin low */
high_output |= 0x08;
}
-
+
BUFFER_ADD = 0x82;
BUFFER_ADD = high_output;
BUFFER_ADD = high_direction;
void turtle_jtag_blink(void)
{
- /*
+ /*
* Turtelizer2 has two LEDs connected to ACBUS2 and ACBUS3
*/
if (high_output & 0x08)
{
high_output = 0x08;
}
-
+
BUFFER_ADD = 0x82;
BUFFER_ADD = high_output;
BUFFER_ADD = high_direction;
status = FT_Close(ftdih);
#elif BUILD_FT2232_LIBFTDI == 1
ftdi_disable_bitbang(&ftdic);
-
+
ftdi_usb_close(&ftdic);
-
+
ftdi_deinit(&ftdic);
#endif
{
LOG_ERROR("expected exactly one argument to ft2232_device_desc <description>");
}
-
+
return ERROR_OK;
}
{
LOG_ERROR("expected exactly one argument to ft2232_serial <serial-number>");
}
-
+
return ERROR_OK;
}
{
LOG_ERROR("expected exactly one argument to ft2232_latency <ms>");
}
-
+
return ERROR_OK;
}
int gw16012_handle_parport_port_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-jtag_interface_t gw16012_interface =
+jtag_interface_t gw16012_interface =
{
.name = "gw16012",
-
+
.execute_queue = gw16012_execute_queue,
- .speed = gw16012_speed,
+ .speed = gw16012_speed,
.register_commands = gw16012_register_commands,
.init = gw16012_init,
.quit = gw16012_quit,
{
register_command(cmd_ctx, NULL, "parport_port", gw16012_handle_parport_port_command,
COMMAND_CONFIG, NULL);
-
+
return ERROR_OK;
}
#ifdef _DEBUG_GW16012_IO_
LOG_DEBUG("%2.2x", value);
#endif
-
+
#if PARPORT_USE_PPDEV == 1
ioctl(device_handle, PPWDATA, &value);
#else
#else
outb(value, gw16012_port);
#endif
- #endif
+ #endif
}
void gw16012_control(u8 value)
{
int i=0, tms=0;
u8 tms_scan = TAP_MOVE(cur_state, end_state);
-
+
gw16012_control(0x0); /* single-bit mode */
-
+
for (i = 0; i < 7; i++)
{
tms = (tms_scan >> i) & 1;
gw16012_data(tms << 1); /* output next TMS bit */
}
-
+
cur_state = end_state;
}
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[cmd->path[state_count]]);
exit(-1);
}
-
+
cur_state = cmd->path[state_count];
state_count++;
num_states--;
}
-
+
end_state = cur_state;
}
{
enum tap_state saved_end_state = end_state;
int i;
-
+
/* only do a state_move when we're not already in RTI */
- if (cur_state != TAP_RTI)
+ if (cur_state != TAP_IDLE)
{
- gw16012_end_state(TAP_RTI);
+ gw16012_end_state(TAP_IDLE);
gw16012_state_move();
}
-
+
for (i = 0; i < num_cycles; i++)
{
gw16012_control(0x0); /* single-bit mode */
gw16012_data(0x0); /* TMS cycle with TMS low */
}
-
+
gw16012_end_state(saved_end_state);
if (cur_state != end_state)
gw16012_state_move();
u8 scan_out, scan_in;
/* only if we're not already in the correct Shift state */
- if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
+ if (!((!ir_scan && (cur_state == TAP_DRSHIFT)) || (ir_scan && (cur_state == TAP_IRSHIFT))))
{
if (ir_scan)
- gw16012_end_state(TAP_SI);
+ gw16012_end_state(TAP_IRSHIFT);
else
- gw16012_end_state(TAP_SD);
+ gw16012_end_state(TAP_DRSHIFT);
gw16012_state_move();
gw16012_end_state(saved_end_state);
bit_count += 7;
bits_left -= 7;
}
-
+
gw16012_control(0x0); /* single-bit mode */
while (bits_left-- > 0)
{
u8 tms = 0;
-
+
scan_out = buf_get_u32(buffer, bit_count, 1);
-
+
if (bits_left == 0) /* last bit */
{
- if ((ir_scan && (end_state == TAP_SI))
- || (!ir_scan && (end_state == TAP_SD)))
+ if ((ir_scan && (end_state == TAP_IRSHIFT))
+ || (!ir_scan && (end_state == TAP_DRSHIFT)))
{
- tms = 0;
+ tms = 0;
}
else
{
{
gw16012_input(&scan_in);
buf_set_u32(buffer, bit_count, 1, ((scan_in & 0x08) >> 3));
- }
+ }
bit_count++;
}
- if (!((ir_scan && (end_state == TAP_SI)) ||
- (!ir_scan && (end_state == TAP_SD))))
+ if (!((ir_scan && (end_state == TAP_IRSHIFT)) ||
+ (!ir_scan && (end_state == TAP_DRSHIFT))))
{
gw16012_data(0x0);
if (ir_scan)
- cur_state = TAP_PI;
+ cur_state = TAP_IRPAUSE;
else
- cur_state = TAP_PD;
-
+ cur_state = TAP_DRPAUSE;
+
if (cur_state != end_state)
gw16012_state_move();
}
enum scan_type type;
u8 *buffer;
int retval;
-
+
/* return ERROR_OK, unless a jtag_read_buffer returns a failed check
* that wasn't handled by a caller-provided error handler
- */
+ */
retval = ERROR_OK;
-
+
while (cmd)
{
switch (cmd->type)
#endif
if (cmd->cmd.reset->trst == 1)
{
- cur_state = TAP_TLR;
+ cur_state = TAP_RESET;
}
gw16012_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
type = jtag_scan_type(cmd->cmd.scan);
#ifdef _DEBUG_JTAG_IO_
- LOG_DEBUG("%s scan (%i) %i bit end in %i", (cmd->cmd.scan->ir_scan) ? "ir" : "dr",
+ LOG_DEBUG("%s scan (%i) %i bit end in %i", (cmd->cmd.scan->ir_scan) ? "ir" : "dr",
type, scan_size, cmd->cmd.scan->end_state);
#endif
gw16012_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
}
cmd = cmd->next;
}
-
+
return retval;
}
version.dwOSVersionInfoSize = sizeof version;
if (!GetVersionEx( &version )) {
- errno = EINVAL;
- return -1;
+ errno = EINVAL;
+ return -1;
}
if (version.dwPlatformId != VER_PLATFORM_WIN32_NT)
- return 0;
+ return 0;
h = CreateFile( "\\\\.\\giveio", GENERIC_READ, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL );
if (h == INVALID_HANDLE_VALUE) {
- errno = ENODEV;
- return -1;
+ errno = ENODEV;
+ return -1;
}
CloseHandle( h );
int i = 0;
#endif
u8 status_port;
-
+
#if PARPORT_USE_PPDEV == 1
if (device_handle>0)
{
snprintf(buffer, 256, "/dev/parport%d", gw16012_port);
device_handle = open(buffer, O_WRONLY);
-#endif
+#endif
if (device_handle<0)
{
LOG_ERROR("cannot open device. check it exists and that user read and write rights are set");
gw16012_port = 0x378;
LOG_WARNING("No gw16012 port specified, using default '0x378' (LPT1)");
}
-
+
LOG_DEBUG("requesting privileges for parallel port 0x%lx...", (long unsigned)(gw16012_port) );
#if PARPORT_USE_GIVEIO == 1
if (gw16012_get_giveio_access() != 0)
outb(0x0, gw16012_port + 2);
#endif
#endif /* PARPORT_USE_PPDEV */
-
+
gw16012_input(&status_port);
gw16012_msb = (status_port & 0x80) ^ 0x80;
-
+
gw16012_speed(jtag_speed);
gw16012_reset(0, 0);
-
+
return ERROR_OK;
}
int gw16012_quit(void)
{
-
+
return ERROR_OK;
}
int scan_size;
enum scan_type type;
u8 *buffer;
-
+
while (cmd != NULL)
{
switch (cmd->type)
{
case JTAG_END_STATE:
DEBUG_JTAG_IO("end_state: %i", cmd->cmd.end_state->end_state);
-
+
if (cmd->cmd.end_state->end_state != -1)
{
jlink_end_state(cmd->cmd.end_state->end_state);
}
break;
-
+
case JTAG_RUNTEST:
DEBUG_JTAG_IO( "runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, \
cmd->cmd.runtest->end_state);
-
+
if (cmd->cmd.runtest->end_state != -1)
{
jlink_end_state(cmd->cmd.runtest->end_state);
}
jlink_runtest(cmd->cmd.runtest->num_cycles);
break;
-
+
case JTAG_STATEMOVE:
DEBUG_JTAG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
-
+
if (cmd->cmd.statemove->end_state != -1)
{
jlink_end_state(cmd->cmd.statemove->end_state);
}
jlink_state_move();
break;
-
+
case JTAG_PATHMOVE:
DEBUG_JTAG_IO("pathmove: %i states, end in %i", \
cmd->cmd.pathmove->num_states, \
cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]);
-
+
jlink_path_move(cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path);
break;
-
+
case JTAG_SCAN:
DEBUG_JTAG_IO("scan end in %i", cmd->cmd.scan->end_state);
-
+
if (cmd->cmd.scan->end_state != -1)
{
jlink_end_state(cmd->cmd.scan->end_state);
}
-
+
scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
DEBUG_JTAG_IO("scan input, length = %d", scan_size);
-
+
#ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(buffer, (scan_size + 7) / 8);
#endif
type = jtag_scan_type(cmd->cmd.scan);
jlink_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size, cmd->cmd.scan);
break;
-
+
case JTAG_RESET:
DEBUG_JTAG_IO("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);
-
+
jlink_tap_execute();
-
+
if (cmd->cmd.reset->trst == 1)
{
- cur_state = TAP_TLR;
+ cur_state = TAP_RESET;
}
jlink_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
-
+
case JTAG_SLEEP:
DEBUG_JTAG_IO("sleep %i", cmd->cmd.sleep->us);
jlink_tap_execute();
jtag_sleep(cmd->cmd.sleep->us);
break;
-
+
default:
LOG_ERROR("BUG: unknown JTAG command type encountered");
exit(-1);
}
cmd = cmd->next;
}
-
+
return jlink_tap_execute();
}
int jlink_speed(int speed)
{
int result;
-
+
if (speed <= JLINK_MAX_SPEED)
{
/* check for RTCK setting */
if (speed == 0)
speed = -1;
-
+
usb_out_buffer[0] = EMU_CMD_SET_SPEED;
usb_out_buffer[1] = (speed >> 0) & 0xff;
usb_out_buffer[2] = (speed >> 8) & 0xff;
-
+
result = jlink_usb_write(jlink_jtag_handle, 3);
-
+
if (result == 3)
{
return ERROR_OK;
{
LOG_INFO("Requested speed %dkHz exceeds maximum of %dkHz, ignored", speed, JLINK_MAX_SPEED);
}
-
+
return ERROR_OK;
}
int jlink_khz(int khz, int *jtag_speed)
{
*jtag_speed = khz;
-
+
return ERROR_OK;
}
int jlink_init(void)
{
- int check_cnt;
-
+ int check_cnt;
+
jlink_jtag_handle = jlink_usb_open();
-
+
if (jlink_jtag_handle == 0)
{
LOG_ERROR("Cannot find jlink Interface! Please check connection and permissions.");
return ERROR_JTAG_INIT_FAILED;
}
-
+
check_cnt = 0;
while (check_cnt < 3)
{
jlink_get_status();
break;
}
-
+
check_cnt++;
}
{
LOG_INFO("J-Link initial read failed, don't worry");
}
-
+
LOG_INFO("J-Link JTAG Interface ready");
-
+
jlink_reset(0, 0);
jlink_tap_init();
-
+
return ERROR_OK;
}
int i;
int tms = 0;
u8 tms_scan = TAP_MOVE(cur_state, end_state);
-
+
for (i = 0; i < 7; i++)
{
tms = (tms_scan >> i) & 1;
jlink_tap_append_step(tms, 0);
}
-
+
cur_state = end_state;
}
void jlink_path_move(int num_states, enum tap_state *path)
{
int i;
-
+
for (i = 0; i < num_states; i++)
{
if (path[i] == tap_transitions[cur_state].low)
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[path[i]]);
exit(-1);
}
-
+
cur_state = path[i];
}
-
+
end_state = cur_state;
}
void jlink_runtest(int num_cycles)
{
int i;
-
+
enum tap_state saved_end_state = end_state;
-
+
/* only do a state_move when we're not already in RTI */
- if (cur_state != TAP_RTI)
+ if (cur_state != TAP_IDLE)
{
- jlink_end_state(TAP_RTI);
+ jlink_end_state(TAP_IDLE);
jlink_state_move();
}
-
+
/* execute num_cycles */
for (i = 0; i < num_cycles; i++)
{
jlink_tap_append_step(0, 0);
}
-
+
/* finish in end_state */
jlink_end_state(saved_end_state);
if (cur_state != end_state)
void jlink_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
{
enum tap_state saved_end_state;
-
+
jlink_tap_ensure_space(1, scan_size + 8);
-
+
saved_end_state = end_state;
-
+
/* Move to appropriate scan state */
- jlink_end_state(ir_scan ? TAP_SI : TAP_SD);
-
+ jlink_end_state(ir_scan ? TAP_IRSHIFT : TAP_DRSHIFT);
+
jlink_state_move();
jlink_end_state(saved_end_state);
-
+
/* Scan */
jlink_tap_append_scan(scan_size, buffer, command);
-
+
/* We are in Exit1, go to Pause */
jlink_tap_append_step(0, 0);
-
- cur_state = ir_scan ? TAP_PI : TAP_PD;
-
+
+ cur_state = ir_scan ? TAP_IRPAUSE : TAP_DRPAUSE;
+
if (cur_state != end_state)
{
jlink_state_move();
void jlink_reset(int trst, int srst)
{
LOG_DEBUG("trst: %i, srst: %i", trst, srst);
-
+
/* Signals are active low */
if (srst == 0)
{
{
jlink_simple_command(EMU_CMD_HW_RESET0);
}
-
+
if (trst == 0)
{
jlink_simple_command(EMU_CMD_HW_TRST1);
void jlink_simple_command(u8 command)
{
int result;
-
+
DEBUG_JTAG_IO("0x%02x", command);
-
+
usb_out_buffer[0] = command;
result = jlink_usb_write(jlink_jtag_handle, 1);
-
+
if (result != 1)
{
LOG_ERROR("J-Link command 0x%02x failed (%d)", command, result);
int jlink_get_status(void)
{
int result;
-
+
jlink_simple_command(EMU_CMD_GET_STATE);
result = jlink_usb_read(jlink_jtag_handle);
-
+
if (result == 8)
{
int vref = usb_in_buffer[0] + (usb_in_buffer[1] << 8);
vref / 1000, vref % 1000, \
usb_in_buffer[2], usb_in_buffer[3], usb_in_buffer[4], \
usb_in_buffer[5], usb_in_buffer[6], usb_in_buffer[7]);
-
+
if (vref < 1500)
{
LOG_ERROR("Vref too low. Check Target Power\n");
{
LOG_ERROR("J-Link command EMU_CMD_GET_STATE failed (%d)\n", result);
}
-
+
return ERROR_OK;
}
{
int result;
int len = 0;
-
+
/* query hardware version */
jlink_simple_command(EMU_CMD_VERSION);
result = jlink_usb_read(jlink_jtag_handle);
-
+
if (result == 2)
{
len = buf_get_u32(usb_in_buffer, 0, 16);
result = jlink_usb_read(jlink_jtag_handle);
-
+
if (result == len)
{
usb_in_buffer[result] = 0;
return ERROR_OK;
}
}
-
+
LOG_ERROR("J-Link command EMU_CMD_VERSION failed (%d)\n", result);
return ERROR_JTAG_DEVICE_ERROR;
}
/* attempt to get status */
jlink_get_status();
}
-
+
return ERROR_OK;
}
{
int available_scans = MAX_PENDING_SCAN_RESULTS - pending_scan_results_length;
int available_bits = JLINK_TAP_BUFFER_SIZE * 8 - tap_length;
-
+
if (scans > available_scans || bits > available_bits)
{
jlink_tap_execute();
{
last_tms = tms;
int index = tap_length / 8;
-
+
if (index < JLINK_TAP_BUFFER_SIZE)
{
int bit_index = tap_length % 8;
u8 bit = 1 << bit_index;
-
+
if (tms)
{
tms_buffer[index] |= bit;
{
tms_buffer[index] &= ~bit;
}
-
+
if (tdi)
{
tdi_buffer[index] |= bit;
{
tdi_buffer[index] &= ~bit;
}
-
+
tap_length++;
}
else
{
pending_scan_result_t *pending_scan_result = &pending_scan_results_buffer[pending_scan_results_length];
int i;
-
+
pending_scan_result->first = tap_length;
pending_scan_result->length = length;
pending_scan_result->command = command;
pending_scan_result->buffer = buffer;
-
+
for (i = 0; i < length; i++)
{
jlink_tap_append_step((i < length-1 ? 0 : 1), (buffer[i/8] >> (i%8)) & 1);
int tdi_offset;
int i;
int result;
-
+
if (tap_length > 0)
{
/* Pad last byte so that tap_length is divisible by 8 */
* analogous to free-running JTAG interfaces. */
jlink_tap_append_step(last_tms, 0);
}
-
+
byte_length = tap_length / 8;
-
+
usb_out_buffer[0] = EMU_CMD_HW_JTAG3;
usb_out_buffer[1] = 0;
usb_out_buffer[2] = (tap_length >> 0) & 0xff;
usb_out_buffer[3] = (tap_length >> 8) & 0xff;
-
+
tms_offset = 4;
for (i = 0; i < byte_length; i++)
{
usb_out_buffer[tms_offset + i] = tms_buffer[i];
}
-
+
tdi_offset = tms_offset + byte_length;
for (i = 0; i < byte_length; i++)
{
usb_out_buffer[tdi_offset + i] = tdi_buffer[i];
}
-
+
result = jlink_usb_message(jlink_jtag_handle, 4 + 2 * byte_length, byte_length);
-
+
if (result == byte_length)
{
for (i = 0; i < byte_length; i++)
{
tdo_buffer[i] = usb_in_buffer[i];
}
-
+
for (i = 0; i < pending_scan_results_length; i++)
{
pending_scan_result_t *pending_scan_result = &pending_scan_results_buffer[i];
int length = pending_scan_result->length;
int first = pending_scan_result->first;
scan_command_t *command = pending_scan_result->command;
-
+
/* Copy to buffer */
buf_set_buf(tdo_buffer, first, buffer, 0, length);
-
+
DEBUG_JTAG_IO("pending scan result, length = %d", length);
-
+
#ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(buffer, byte_length);
#endif
-
+
if (jtag_read_buffer(buffer, command) != ERROR_OK)
{
jlink_tap_init();
return ERROR_JTAG_QUEUE_FAILED;
}
-
+
if (pending_scan_result->buffer != NULL)
{
free(pending_scan_result->buffer);
LOG_ERROR("jlink_tap_execute, wrong result %d, expected %d", result, byte_length);
return ERROR_JTAG_QUEUE_FAILED;
}
-
+
jlink_tap_init();
}
-
+
return ERROR_OK;
}
struct usb_bus *busses;
struct usb_bus *bus;
struct usb_device *dev;
-
+
jlink_jtag_t *result;
-
+
result = (jlink_jtag_t*) malloc(sizeof(jlink_jtag_t));
-
+
usb_init();
usb_find_busses();
usb_find_devices();
-
+
busses = usb_get_busses();
-
+
/* find jlink_jtag device in usb bus */
-
+
for (bus = busses; bus; bus = bus->next)
{
for (dev = bus->devices; dev; dev = dev->next)
if ((dev->descriptor.idVendor == VID) && (dev->descriptor.idProduct == PID))
{
result->usb_handle = usb_open(dev);
-
+
/* usb_set_configuration required under win32 */
usb_set_configuration(result->usb_handle, dev->config[0].bConfigurationValue);
usb_claim_interface(result->usb_handle, 0);
-
+
#if 0
- /*
+ /*
* This makes problems under Mac OS X. And is not needed
* under Windows. Hopefully this will not break a linux build
*/
usb_set_altinterface(result->usb_handle, 0);
-#endif
+#endif
return result;
}
}
}
-
+
free(result);
return NULL;
}
{
int result;
int result2;
-
+
result = jlink_usb_write(jlink_jtag, out_length);
if (result == out_length)
{
else
{
LOG_ERROR("jlink_usb_read_emu_result (requested=0, result=%d)", usb_emu_result_buffer[0]);
- return -1;
+ return -1;
}
}
else
else
{
LOG_ERROR("jlink_usb_read_emu_result (requested=0, result=%d)", usb_in_buffer[result]);
- return -1;
+ return -1;
}
}
}
int jlink_usb_write(jlink_jtag_t *jlink_jtag, int out_length)
{
int result;
-
+
if (out_length > JLINK_OUT_BUFFER_SIZE)
{
LOG_ERROR("jlink_jtag_write illegal out_length=%d (max=%d)", out_length, JLINK_OUT_BUFFER_SIZE);
return -1;
}
-
+
result = usb_bulk_write(jlink_jtag->usb_handle, JLINK_WRITE_ENDPOINT, \
usb_out_buffer, out_length, JLINK_USB_TIMEOUT);
-
+
DEBUG_JTAG_IO("jlink_usb_write, out_length = %d, result = %d", out_length, result);
-
+
#ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(usb_out_buffer, out_length);
#endif
usb_in_buffer, JLINK_IN_BUFFER_SIZE, JLINK_USB_TIMEOUT);
DEBUG_JTAG_IO("jlink_usb_read, result = %d", result);
-
+
#ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(usb_in_buffer, result);
#endif
usb_emu_result_buffer, JLINK_EMU_RESULT_BUFFER_SIZE, JLINK_USB_TIMEOUT);
DEBUG_JTAG_IO("jlink_usb_read_result, result = %d", result);
-
+
#ifdef _DEBUG_USB_COMMS_
jlink_debug_buffer(usb_emu_result_buffer, result);
#endif
char s[4];
int i;
int j;
-
+
for (i = 0; i < length; i += BYTES_PER_LINE)
{
snprintf(line, 5, "%04x", i);
tap_transition_t tap_transitions[16] =
{
- {TAP_TLR, TAP_RTI}, /* TLR */
- {TAP_SIS, TAP_CD}, /* SDS */
- {TAP_E1D, TAP_SD}, /* CD */
- {TAP_E1D, TAP_SD}, /* SD */
- {TAP_UD, TAP_PD}, /* E1D */
- {TAP_E2D, TAP_PD}, /* PD */
- {TAP_UD, TAP_SD}, /* E2D */
- {TAP_SDS, TAP_RTI}, /* UD */
- {TAP_SDS, TAP_RTI}, /* RTI */
- {TAP_TLR, TAP_CI}, /* SIS */
- {TAP_E1I, TAP_SI}, /* CI */
- {TAP_E1I, TAP_SI}, /* SI */
- {TAP_UI, TAP_PI}, /* E1I */
- {TAP_E2I, TAP_PI}, /* PI */
- {TAP_UI, TAP_SI}, /* E2I */
- {TAP_SDS, TAP_RTI} /* UI */
+ {TAP_RESET, TAP_IDLE}, /* TLR */
+ {TAP_IRSELECT, TAP_DRCAPTURE}, /* SDS */
+ {TAP_DREXIT1, TAP_DRSHIFT}, /* CD */
+ {TAP_DREXIT1, TAP_DRSHIFT}, /* SD */
+ {TAP_DRUPDATE, TAP_DRPAUSE}, /* E1D */
+ {TAP_DREXIT2, TAP_DRPAUSE}, /* PD */
+ {TAP_DRUPDATE, TAP_DRSHIFT}, /* E2D */
+ {TAP_DRSELECT, TAP_IDLE}, /* UD */
+ {TAP_DRSELECT, TAP_IDLE}, /* RTI */
+ {TAP_RESET, TAP_IRCAPTURE}, /* SIS */
+ {TAP_IREXIT1, TAP_IRSHIFT}, /* CI */
+ {TAP_IREXIT1, TAP_IRSHIFT}, /* SI */
+ {TAP_IRUPDATE, TAP_IRPAUSE}, /* E1I */
+ {TAP_IREXIT2, TAP_IRPAUSE}, /* PI */
+ {TAP_IRUPDATE, TAP_IRSHIFT}, /* E2I */
+ {TAP_DRSELECT, TAP_IDLE} /* UI */
};
char* jtag_event_strings[] =
* inside the drivers, but we don't want to break
* linking the drivers!!!!
*/
-enum tap_state end_state = TAP_TLR;
-enum tap_state cur_state = TAP_TLR;
+enum tap_state end_state = TAP_RESET;
+enum tap_state cur_state = TAP_RESET;
int jtag_trst = 0;
int jtag_srst = 0;
static jtag_tap_t *jtag_all_taps = NULL;
enum reset_types jtag_reset_config = RESET_NONE;
-enum tap_state cmd_queue_end_state = TAP_TLR;
-enum tap_state cmd_queue_cur_state = TAP_TLR;
+enum tap_state cmd_queue_end_state = TAP_RESET;
+enum tap_state cmd_queue_cur_state = TAP_RESET;
int jtag_verify_capture_ir = 1;
* alignment.
*
* What I do not/have is a reasonable portable means
- * to align by...
+ * to align by...
*
* The solution here, is based on these suggestions.
* http://gcc.gnu.org/ml/gcc-help/2008-12/msg00041.html
// The alignment process.
size = (size + ALIGN_SIZE -1) & (~(ALIGN_SIZE-1));
- // Done...
-
+ // Done...
+
if (*p_page)
{
return;
}
- if (cmd_queue_end_state == TAP_TLR)
+ if (cmd_queue_end_state == TAP_RESET)
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
}
void jtag_add_tlr(void)
{
- jtag_prelude(TAP_TLR);
+ jtag_prelude(TAP_RESET);
int retval;
retval=interface_jtag_add_tlr();
int MINIDRIVER(interface_jtag_add_tlr)()
{
- enum tap_state state = TAP_TLR;
+ enum tap_state state = TAP_RESET;
jtag_command_t **last_cmd = jtag_get_last_command_p();
/* allocate memory for a new list member */
for (i=0; i<num_states; i++)
{
- if (path[i] == TAP_TLR)
+ if (path[i] == TAP_RESET)
{
- LOG_ERROR("BUG: TAP_TLR is not a valid state for pathmove sequences");
+ LOG_ERROR("BUG: TAP_RESET is not a valid state for pathmove sequences");
exit(-1);
}
if ((tap_transitions[cur_state].low != path[i])&&
if (trst_with_tlr)
{
LOG_DEBUG("JTAG reset with TLR instead of TRST");
- jtag_add_end_state(TAP_TLR);
+ jtag_add_end_state(TAP_RESET);
jtag_add_tlr();
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
return;
* and inform possible listeners about this
*/
LOG_DEBUG("TRST line asserted");
- cmd_queue_cur_state = TAP_TLR;
+ cmd_queue_cur_state = TAP_RESET;
jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
}
else
void jtag_add_end_state(enum tap_state state)
{
cmd_queue_end_state = state;
- if ((cmd_queue_end_state == TAP_SD)||(cmd_queue_end_state == TAP_SI))
+ if ((cmd_queue_end_state == TAP_DRSHIFT)||(cmd_queue_end_state == TAP_IRSHIFT))
{
- LOG_ERROR("BUG: TAP_SD/SI can't be end state. Calling code should use a larger scan field");
+ LOG_ERROR("BUG: TAP_DRSHIFT/SI can't be end state. Calling code should use a larger scan field");
}
}
buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF);
}
- jtag_add_plain_dr_scan(1, &field, TAP_TLR);
+ jtag_add_plain_dr_scan(1, &field, TAP_RESET);
jtag_execute_queue();
for (i = 0; i < JTAG_MAX_CHAIN_SIZE * 4; i++)
break;
}
}
-
+
/* If none of the expected ids matched, log an error */
if (ii == tap->expected_ids_cnt) {
LOG_ERROR("JTAG tap: %s got: 0x%08x (mfg: 0x%3.3x, part: 0x%4.4x, ver: 0x%1.1x)",
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_plain_ir_scan(1, &field, TAP_TLR);
+ jtag_add_plain_ir_scan(1, &field, TAP_RESET);
jtag_execute_queue();
tap = NULL;
memcpy(new_expected_ids, pTap->expected_ids, sizeof(u32) * pTap->expected_ids_cnt);
new_expected_ids[pTap->expected_ids_cnt] = w;
-
- free(pTap->expected_ids);
+
+ free(pTap->expected_ids);
pTap->expected_ids = new_expected_ids;
pTap->expected_ids_cnt++;
break;
#define _DEBUG_JTAG_IO_
#endif
-/* Tap States
- * TLR - Test-Logic-Reset, RTI - Run-Test/Idle,
- * SDS - Select-DR-Scan, CD - Capture-DR, SD - Shift-DR, E1D - Exit1-DR,
- * PD - Pause-DR, E2D - Exit2-DR, UD - Update-DR,
- * SIS - Select-IR-Scan, CI - Capture-IR, SI - Shift-IR, E1I - Exit1-IR,
- * PI - Pause-IR, E2I - Exit2-IR, UI - Update-IR
+/* 16 Tap States, from page 21 of ASSET InterTech, Inc.'s svf.pdf
*/
enum tap_state
{
- TAP_TLR = 0x0, TAP_RTI = 0x8,
- TAP_SDS = 0x1, TAP_CD = 0x2, TAP_SD = 0x3, TAP_E1D = 0x4,
- TAP_PD = 0x5, TAP_E2D = 0x6, TAP_UD = 0x7,
- TAP_SIS = 0x9, TAP_CI = 0xa, TAP_SI = 0xb, TAP_E1I = 0xc,
- TAP_PI = 0xd, TAP_E2I = 0xe, TAP_UI = 0xf
+ TAP_RESET = 0x0, TAP_IDLE = 0x8,
+ TAP_DRSELECT = 0x1, TAP_DRCAPTURE = 0x2, TAP_DRSHIFT = 0x3, TAP_DREXIT1 = 0x4,
+ TAP_DRPAUSE = 0x5, TAP_DREXIT2 = 0x6, TAP_DRUPDATE = 0x7,
+ TAP_IRSELECT = 0x9, TAP_IRCAPTURE = 0xa, TAP_IRSHIFT = 0xb, TAP_IREXIT1 = 0xc,
+ TAP_IRPAUSE = 0xd, TAP_IREXIT2 = 0xe, TAP_IRUPDATE = 0xf
};
typedef struct tap_transition_s
/* JTAG interface, can be implemented with a software or hardware fifo
*
- * TAP_SD and TAP_SI are illegal end states. TAP_SD/SI as end states
+ * TAP_DRSHIFT and TAP_IRSHIFT are illegal end states. TAP_DRSHIFT/SI as end states
* can be emulated by using a larger scan.
*
* Code that is relatively insensitive to the path(as long
extern int interface_jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern void jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
extern int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state endstate);
-/* run a TAP_TLR reset. End state is TAP_TLR, regardless
+/* run a TAP_RESET reset. End state is TAP_RESET, regardless
* of start state.
*/
extern void jtag_add_tlr(void);
* all drivers can support this, but it is required for e.g.
* XScale and Xilinx support
*
- * Note! TAP_TLR must not be used in the path!
+ * Note! TAP_RESET must not be used in the path!
*
* Note that the first on the list must be reachable
* via a single transition from the current state.
*/
extern void jtag_add_pathmove(int num_states, enum tap_state *path);
extern int interface_jtag_add_pathmove(int num_states, enum tap_state *path);
-/* go to TAP_RTI, if we're not already there and cycle
- * precisely num_cycles in the TAP_RTI after which move
- * to the end state, if it is != TAP_RTI
+/* go to TAP_IDLE, if we're not already there and cycle
+ * precisely num_cycles in the TAP_IDLE after which move
+ * to the end state, if it is != TAP_IDLE
*
* nb! num_cycles can be 0, in which case the fn will navigate
- * to endstate via TAP_RTI
+ * to endstate via TAP_IDLE
*/
extern void jtag_add_runtest(int num_cycles, enum tap_state endstate);
extern int interface_jtag_add_runtest(int num_cycles, enum tap_state endstate);
#define MINIDRIVER(a) a
/* jtag_add_dr_out() is a faster version of jtag_add_dr_scan()
*
- * Current or end_state can not be TAP_TLR. end_state can be -1
+ * Current or end_state can not be TAP_RESET. end_state can be -1
*
* num_bits[i] is the number of bits to clock out from value[i] LSB first.
*
#endif
if (cmd->cmd.reset->trst == 1)
{
- cur_state = TAP_TLR;
+ cur_state = TAP_RESET;
}
usbprog_reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
break;
int i;
/* only do a state_move when we're not already in RTI */
- if (cur_state != TAP_RTI)
+ if (cur_state != TAP_IDLE)
{
- usbprog_end_state(TAP_RTI);
+ usbprog_end_state(TAP_IDLE);
usbprog_state_move();
}
enum tap_state saved_end_state = end_state;
if (ir_scan)
- usbprog_end_state(TAP_SI);
+ usbprog_end_state(TAP_IRSHIFT);
else
- usbprog_end_state(TAP_SD);
+ usbprog_end_state(TAP_DRSHIFT);
/* usbprog_jtag_tms_send(usbprog_jtag_handle); */
}
if (ir_scan)
- cur_state = TAP_PI;
+ cur_state = TAP_IRPAUSE;
else
- cur_state = TAP_PD;
+ cur_state = TAP_DRPAUSE;
if (cur_state != end_state)
usbprog_state_move();
else
{
/* Danger!!! if clk!=0 when in
- * idle in TAP_RTI, reset halt on str912 will fail.
+ * idle in TAP_IDLE, reset halt on str912 will fail.
*/
ZY1000_POKE(ZY1000_JTAG_BASE+0x10, 0x00000001);
}
{
waitIdle();
/* we're now in the TLR state until trst is deasserted */
- ZY1000_POKE(ZY1000_JTAG_BASE+0x20, TAP_TLR);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x20, TAP_RESET);
} else
{
/* We'll get RCLK failure when we assert TRST, so clear any false positives here */
if (fread(*data, 1, *len, pFile)!=*len)
{
fclose(pFile);
- free(*data);
+ free(*data);
LOG_ERROR("Can't open %s\n", fileName);
return ERROR_JTAG_DEVICE_ERROR;
}
enum tap_state pause_state;
int l;
k=num_bits-j;
- pause_state=(shiftState==TAP_SD)?TAP_SD:TAP_SI;
+ pause_state=(shiftState==TAP_DRSHIFT)?TAP_DRSHIFT:TAP_IRSHIFT;
if (k>32)
{
k=32;
} else if (pause&&(i == num_fields-1))
{
/* this was the last to shift out this time */
- pause_state=(shiftState==TAP_SD)?TAP_PD:TAP_PI;
+ pause_state=(shiftState==TAP_DRSHIFT)?TAP_DRPAUSE:TAP_IRPAUSE;
}
// we have (num_bits+7)/8 bytes of bits to toggle out.
fields[j].in_check_mask = tap->expected_mask;
}
- scanFields(1, fields+j, TAP_SI, pause);
+ scanFields(1, fields+j, TAP_IRSHIFT, pause);
/* update device information */
buf_cpy(fields[j].out_value, tap->cur_instr, scan_size);
memset(&tmp, 0, sizeof(tmp));
tmp.out_value = ones;
tmp.num_bits = scan_size;
- scanFields(1, &tmp, TAP_SI, pause);
+ scanFields(1, &tmp, TAP_IRSHIFT, pause);
/* update device information */
buf_cpy(tmp.out_value, tap->cur_instr, scan_size);
tap->bypass = 1;
int interface_jtag_add_plain_ir_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
- scanFields(num_fields, fields, TAP_SI, 1);
+ scanFields(num_fields, fields, TAP_IRSHIFT, 1);
gotoEndState();
return ERROR_OK;
{
found = 1;
- scanFields(1, fields+j, TAP_SD, pause);
+ scanFields(1, fields+j, TAP_DRSHIFT, pause);
}
}
if (!found)
tmp.in_handler = NULL;
tmp.in_handler_priv = NULL;
- scanFields(1, &tmp, TAP_SD, pause);
+ scanFields(1, &tmp, TAP_DRSHIFT, pause);
}
else
{
int interface_jtag_add_plain_dr_scan(int num_fields, scan_field_t *fields, enum tap_state state)
{
- scanFields(num_fields, fields, TAP_SD, 1);
+ scanFields(num_fields, fields, TAP_DRSHIFT, 1);
gotoEndState();
return ERROR_OK;
}
int interface_jtag_add_tlr()
{
- setCurrentState(TAP_TLR);
+ setCurrentState(TAP_RESET);
return ERROR_OK;
}
int interface_jtag_add_runtest(int num_cycles, enum tap_state state)
{
/* num_cycles can be 0 */
- setCurrentState(TAP_RTI);
+ setCurrentState(TAP_IDLE);
/* execute num_cycles, 32 at the time. */
int i;
{
num=num_cycles-i;
}
- shiftValueInner(TAP_RTI, TAP_RTI, num, 0);
+ shiftValueInner(TAP_IDLE, TAP_IDLE, num, 0);
}
#if !TEST_MANUAL()
/* finish in end_state */
setCurrentState(state);
#else
- enum tap_state t=TAP_RTI;
+ enum tap_state t=TAP_IDLE;
/* test manual drive code on any target */
int tms;
u8 tms_scan = TAP_MOVE(t, state);
int i;
for (i = 0; i < count; i++)
{
- shiftValueInner(TAP_SD, TAP_SD, 32, fast_target_buffer_get_u32(buffer, 1));
- shiftValueInner(TAP_SD, end_state, 6, reg_addr|(1<<5));
+ shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 1));
+ shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
buffer+=4;
}
} else
int i;
for (i = 0; i < count; i++)
{
- shiftValueInner(TAP_SD, TAP_SD, 32, fast_target_buffer_get_u32(buffer, 0));
- shiftValueInner(TAP_SD, end_state, 6, reg_addr|(1<<5));
+ shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 0));
+ shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
buffer+=4;
}
}
field.in_handler = NULL;
field.in_handler_priv = NULL;
- jtag_add_ir_scan(1, &field, TAP_RTI);
+ jtag_add_ir_scan(1, &field, TAP_IDLE);
free(field.out_value);
}
virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */
- jtag_add_dr_scan(1, &scan_field, TAP_PD);
+ jtag_add_dr_scan(1, &scan_field, TAP_DRPAUSE);
free(values);
while (num_words--)
{
scan_field.in_handler_priv = words++;
- jtag_add_dr_scan(1, &scan_field, TAP_PD);
+ jtag_add_dr_scan(1, &scan_field, TAP_DRPAUSE);
}
return ERROR_OK;
if ((retval = xilinx_read_bit_file(&bit_file, filename)) != ERROR_OK)
return retval;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */
jtag_execute_queue();
jtag_add_sleep(1000);
field.num_bits = bit_file.length * 8;
field.out_value = bit_file.data;
- jtag_add_dr_scan(1, &field, TAP_PD);
+ jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
jtag_execute_queue();
jtag_add_tlr();
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
- jtag_add_runtest(13, TAP_RTI);
+ jtag_add_runtest(13, TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
- jtag_add_runtest(13, TAP_RTI);
+ jtag_add_runtest(13, TAP_IDLE);
virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
jtag_execute_queue();
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
else
{
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
arm11_record_register_history(arm11);
return ERROR_OK;
}
- arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
+ arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
arm11_leave_debug_state(arm11);
- arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
+ arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
arm11_leave_debug_state(arm11);
- arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
+ arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
- arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
+ arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
/* check DIDR */
arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
- arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
+ arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval;
{
jtag_tap_t *tap;
target_t * t;
-
+
tap = jtag_TapByString( arg );
if( !tap ){
return NULL;
enum tap_state arm11_move_pi_to_si_via_ci[] =
{
- TAP_E2I, TAP_UI, TAP_SDS, TAP_SIS, TAP_CI, TAP_SI
+ TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
};
int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
{
- if (cmd_queue_cur_state == TAP_PI)
+ if (cmd_queue_cur_state == TAP_IRPAUSE)
jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
jtag_add_ir_scan(num_fields, fields, state);
enum tap_state arm11_move_pd_to_sd_via_cd[] =
{
- TAP_E2D, TAP_UD, TAP_SDS, TAP_CD, TAP_SD
+ TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
{
- if (cmd_queue_cur_state == TAP_PD)
+ if (cmd_queue_cur_state == TAP_DRPAUSE)
jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
jtag_add_dr_scan(num_fields, fields, state);
jtag_tap_t *tap;
tap = arm11->jtag_info.tap;
if( tap == NULL ){
- /* FIX!!!! error is logged, but not propagated back up the call stack... */
+ /* FIX!!!! error is logged, but not propagated back up the call stack... */
LOG_ERROR( "tap is null here! This is bad!");
return;
}
arm11_setup_field(arm11, 5, &instr, NULL, &field);
- arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_PI : state);
+ arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_IRPAUSE : state);
}
/** Verify shifted out data from Scan Chain Register (SCREG)
if (v != 0x10)
{
- LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
- return ERROR_FAIL;
+ LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
+ return ERROR_FAIL;
}
JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
field.in_handler = arm11_in_handler_SCAN_N;
- arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_PD : state);
+ arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_DRPAUSE : state);
}
/** Write an instruction into the ITR register
* \remarks By default this ends with Run-Test/Idle state
* and causes the instruction to be executed. If
* a subsequent write to DTR is needed before
- * executing the instruction then TAP_PD should be
+ * executing the instruction then TAP_DRPAUSE should be
* passed to \p state.
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
- arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_RTI : state);
+ arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_IDLE : state);
}
/** Read the Debug Status and Control Register (DSCR)
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
- arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD);
+ arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
jtag_execute_queue();
if (arm11->last_dscr != dscr)
- JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
+ JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
- arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD);
+ arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
jtag_execute_queue();
while (count--)
{
- arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_RTI);
+ arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
while (1)
{
u8 flag;
- arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_RTI : TAP_PD);
+ arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
jtag_execute_queue();
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
- arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
+ arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, -1);
{
Data = *data;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_RTI);
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
jtag_execute_queue();
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
{
Data = 0;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_execute_queue();
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
/** JTAG path for arm11_run_instr_data_to_core_noack
*
- * The repeated TAP_RTI's do not cause a repeated execution
+ * The repeated TAP_IDLE's do not cause a repeated execution
* if passed without leaving the state.
*
* Since this is more than 7 bits (adjustable via adding more
- * TAP_RTI's) it produces an artificial delay in the lower
+ * TAP_IDLE's) it produces an artificial delay in the lower
* layer (FT2232) that is long enough to finish execution on
* the core but still shorter than any manually inducible delays.
*
*/
enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] =
{
- TAP_E2D, TAP_UD, TAP_RTI, TAP_RTI, TAP_RTI, TAP_SDS, TAP_CD, TAP_SD
+ TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
- arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
+ arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
arm11_add_IR(arm11, ARM11_EXTEST, -1);
if (count)
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_PD);
+ jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay),
arm11_MOVE_PD_RTI_PD_with_delay);
}
else
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_RTI);
+ jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
}
}
chain5_fields[0].out_value = 0;
chain5_fields[1].in_value = ReadyPos++;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_execute_queue();
{
arm11_add_IR(arm11, ARM11_ITRSEL, -1);
- arm11_add_debug_INST(arm11, opcode, NULL, TAP_RTI);
+ arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
arm11_add_IR(arm11, ARM11_INTEST, -1);
{
do
{
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_RTI : TAP_PD);
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
jtag_execute_queue();
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
AddressOut = 0;
}
- do
+ do
{
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
- arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_PD);
+ arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
jtag_execute_queue();
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm720t_soft_reset_halt,
-
+
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm720t_read_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
-
+
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint,
scan_field_t fields[2];
u8 out_buf[4];
u8 instruction_buf = instruction;
-
+
buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
-
- jtag_add_end_state(TAP_PD);
+
+ jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
{
return retval;
}
-
+
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &instruction_buf;
}
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
-
+
jtag_add_dr_scan(2, fields, -1);
if (clock)
arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
/* "EXECUTE" stage (3), CDATA is read */
arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
-
+
return ERROR_OK;
}
arm720t_read_cp15(target, 0xee120f10, &ttb);
jtag_execute_queue();
-
+
ttb &= 0xffffc000;
-
+
return ttb;
}
/* read cp15 control register */
arm720t_read_cp15(target, 0xee110f10, &cp15_control);
jtag_execute_queue();
-
+
if (mmu)
cp15_control &= ~0x1U;
-
+
if (d_u_cache || i_cache)
cp15_control &= ~0x4U;
/* read cp15 control register */
arm720t_read_cp15(target, 0xee110f10, &cp15_control);
jtag_execute_queue();
-
+
if (mmu)
cp15_control |= 0x1U;
-
+
if (d_u_cache || i_cache)
cp15_control |= 0x4U;
-
+
arm720t_write_cp15(target, 0xee010f10, cp15_control);
}
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info;
-
+
/* examine cp15 control reg */
arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
jtag_execute_queue();
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info;
-
+
/* restore i/d fault status and address register */
arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
arm7_9_common_t *arm7_9;
arm7tdmi_common_t *arm7tdmi;
arm720t_common_t *arm720t;
-
+
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
return -1;
}
-
+
arm7_9 = armv4_5->arch_info;
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
{
return -1;
}
-
+
arm7tdmi = arm7_9->arch_info;
if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
{
return -1;
}
-
+
arm720t = arm7tdmi->arch_info;
if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
{
return -1;
}
-
+
*armv4_5_p = armv4_5;
*arm7_9_p = arm7_9;
*arm7tdmi_p = arm7tdmi;
*arm720t_p = arm720t;
-
+
return ERROR_OK;
}
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info;
-
- char *state[] =
+
+ char *state[] =
{
"disabled", "enabled"
};
-
+
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
-
+
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, Cache: %s",
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm720t->armv4_5_mmu.mmu_enabled],
state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
-
+
return ERROR_OK;
}
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info;
-
+
/* disable cache, but leave MMU enabled */
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
arm720t_disable_mmu_caches(target, 0, 1, 0);
-
+
retval = arm7_9_read_memory(target, address, size, count, buffer);
-
+
if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
arm720t_enable_mmu_caches(target, 0, 1, 0);
-
+
return retval;
}
int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
{
int retval;
-
+
if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
return retval;
arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
arm720t_common_t *arm720t = arm7tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
-
+
if ((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
-
+
long long then=timeval_ms();
int timeout;
while (!(timeout=((timeval_ms()-then)>1000)))
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
-
+
target->state = TARGET_HALTED;
-
+
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
-
+
/* start fetching from 0x0 */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
armv4_5->core_cache->reg_list[15].dirty = 1;
armv4_5->core_cache->reg_list[15].valid = 1;
-
+
armv4_5->core_mode = ARMV4_5_MODE_SVC;
armv4_5->core_state = ARMV4_5_STATE_ARM;
-
+
arm720t_disable_mmu_caches(target, 1, 1, 1);
arm720t->armv4_5_mmu.mmu_enabled = 0;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
{
return retval;
}
-
+
return ERROR_OK;
}
int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
arm7tdmi_init_target(cmd_ctx, target);
-
+
return ERROR_OK;
-
+
}
int arm720t_quit(void)
{
-
+
return ERROR_OK;
}
{
arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
-
+
arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant);
arm7tdmi->arch_info = arm720t;
arm720t->common_magic = ARM720T_COMMON_MAGIC;
-
+
arm7_9->post_debug_entry = arm720t_post_debug_entry;
arm7_9->pre_restore_context = arm720t_pre_restore_context;
-
+
arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
arm720t->armv4_5_mmu.has_tiny_pages = 0;
arm720t->armv4_5_mmu.mmu_enabled = 0;
-
+
return ERROR_OK;
}
int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
{
arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
-
+
arm720t_init_arch_info(target, arm720t, target->tap, target->variant);
return ERROR_OK;
{
int retval;
command_t *arm720t_cmd;
-
-
+
+
retval = arm7tdmi_register_commands(cmd_ctx);
-
+
arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
-
+
return ERROR_OK;
}
command_print(cmd_ctx, "current target isn't an ARM720t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
{
return retval;
}
-
+
command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
}
else if (argc == 2)
}
int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
+{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
command_print(cmd_ctx, "current target isn't an ARM720t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK;
}
-
+
return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
}
int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
+{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
command_print(cmd_ctx, "current target isn't an ARM720t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK;
}
-
+
return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
}
int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
+{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
command_print(cmd_ctx, "current target isn't an ARM720t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK;
}
-
+
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
}
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL);
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
arm_jtag_set_instr(jtag_info, 0xf, NULL);
}
arm_jtag_set_instr(jtag_info, 0x4, NULL);
- jtag_add_runtest(1, TAP_RTI);
+ jtag_add_runtest(1, TAP_IDLE);
return jtag_execute_queue();
}
/* target function declarations */
int arm7tdmi_poll(struct target_s *target);
int arm7tdmi_halt(target_t *target);
-
+
target_type_t arm7tdmi_target =
{
.name = "arm7tdmi",
.soft_reset_halt = arm7_9_soft_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
+
.read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
-
+
.run_algorithm = armv4_5_run_algorithm,
-
+
.add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint,
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
scan_field_t fields[2];
u8 databus[4];
u8 breakpoint;
-
- jtag_add_end_state(TAP_PD);
+
+ jtag_add_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 1;
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
-
+
fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
-
+
if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
- jtag_add_dr_scan(2, fields, TAP_PD);
+ jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
fields[0].in_value = NULL;
fields[0].out_value = &breakpoint;
fields[1].in_value = NULL;
fields[1].out_value = databus;
-
- jtag_add_dr_scan(2, fields, TAP_PD);
+
+ jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
if (breakpoint & 1)
- target->debug_reason = DBG_REASON_WATCHPOINT;
+ target->debug_reason = DBG_REASON_WATCHPOINT;
else
- target->debug_reason = DBG_REASON_BREAKPOINT;
+ target->debug_reason = DBG_REASON_BREAKPOINT;
}
return ERROR_OK;
static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
{
u32 values[2]={breakpoint, flip_u32(out, 32)};
-
+
jtag_add_dr_out(jtag_info->tap,
2,
arm7tdmi_num_bits,
values,
-1);
-
+
jtag_add_runtest(0, -1);
return ERROR_OK;
/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
{
- jtag_add_end_state(TAP_PD);
+ jtag_add_end_state(TAP_DRPAUSE);
arm_jtag_scann(jtag_info, 0x1);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
+
return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
}
int retval = ERROR_OK;
scan_field_t fields[2];
- jtag_add_end_state(TAP_PD);
+ jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
+
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
-
+
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
jtag_add_dr_scan(2, fields, -1);
jtag_add_runtest(0, -1);
-
+
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
if (in)
{
LOG_DEBUG("in: 0x%8.8x", *in);
/* clock the target, and read the databus
* the *in pointer points to a buffer where elements of 'size' bytes
* are stored in big (be==1) or little (be==0) endianness
- */
+ */
int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{
int retval = ERROR_OK;
scan_field_t fields[2];
- jtag_add_end_state(TAP_PD);
+ jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
+
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
-
+
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
jtag_add_dr_scan(2, fields, -1);
jtag_add_runtest(0, -1);
-
+
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
if (in)
{
LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
- /* save r0 before using it and put system in ARM state
+
+ /* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */
-
+
/* fetch STR r0, [r0] */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* nothing fetched, STR r0, [r0] in Execute (2) */
arm7tdmi_clock_data_in(jtag_info, r0);
- /* MOV r0, r15 fetched, STR in Decode */
+ /* MOV r0, r15 fetched, STR in Decode */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
/* nothing fetched, data from previous cycle is written to register */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-
+
/* fetch BX */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
/* NOP fetched, BX in Decode, MOV in Execute */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* NOP fetched, BX in Execute (1) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-
+
jtag_execute_queue();
-
+
/* fix program counter:
* MOV r0, r15 was the 4th instruction (+6)
* reading PC in Thumb state gives address of instruction + 4
*/
*pc -= 0xa;
-
+
}
void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
u32 *buf_u32 = buffer;
u16 *buf_u16 = buffer;
u8 *buf_u8 = buffer;
-
+
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
}
}
}
-
+
}
void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* MRS r0, cpsr */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
-
+
/* STR r0, [r15] */
arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
/* fetch NOP, STR in DECODE stage */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
/* MSR1 fetched */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
-
+
/* MSR fetched */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
/* NOP fetched, MSR in DECODE */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* nothing fetched, MSR in EXECUTE (2) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-
+
}
void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
}
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
-
+
}
void arm7tdmi_load_word_regs(target_t *target, u32 mask)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* put system-speed load half-word into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
-
+
}
void arm7tdmi_store_hword_reg(target_t *target, int num)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
void arm7tdmi_branch_resume_thumb(target_t *target)
{
LOG_DEBUG("-");
-
+
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
/* Branch and eXchange */
arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
-
+
embeddedice_read_reg(dbg_stat);
-
+
/* fetch NOP, BX in DECODE stage */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-
+
/* target is now in Thumb state */
embeddedice_read_reg(dbg_stat);
-
+
/* fetch NOP, BX in EXECUTE stage (1st cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-
+
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
embeddedice_read_reg(dbg_stat);
-
+
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
}
-
+
void arm7tdmi_build_reg_cache(target_t *target)
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
if (t==NULL)
return ERROR_FAIL;
-
+
(*cache_p) = t;
arm7_9->eice_cache = (*cache_p);
-
+
if (arm7_9->etm_ctx)
{
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
-
+
arm7tdmi_build_reg_cache(target);
-
+
return ERROR_OK;
-
+
}
int arm7tdmi_quit(void)
{
-
+
return ERROR_OK;
}
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
-
+
arm7_9 = &arm7tdmi->arm7_9_common;
armv4_5 = &arm7_9->armv4_5_common;
-
+
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 4;
-
+
/* register arch-specific functions */
arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
arm7_9->change_to_arm = arm7tdmi_change_to_arm;
arm7_9->read_core_regs = arm7tdmi_read_core_regs;
arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
arm7_9->read_xpsr = arm7tdmi_read_xpsr;
-
+
arm7_9->write_xpsr = arm7tdmi_write_xpsr;
arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
arm7_9->write_core_regs = arm7tdmi_write_core_regs;
-
+
arm7_9->load_word_regs = arm7tdmi_load_word_regs;
arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
-
+
arm7_9->store_word_regs = arm7tdmi_store_word_regs;
arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
-
+
arm7_9->write_pc = arm7tdmi_write_pc;
arm7_9->branch_resume = arm7tdmi_branch_resume;
arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
-
+
arm7_9->enable_single_step = arm7_9_enable_eice_step;
arm7_9->disable_single_step = arm7_9_disable_eice_step;
-
+
arm7_9->pre_debug_entry = NULL;
arm7_9->post_debug_entry = NULL;
-
+
arm7_9->pre_restore_context = NULL;
arm7_9->post_restore_context = NULL;
-
+
/* initialize arch-specific breakpoint handling */
arm7_9->arm_bkpt = 0xdeeedeee;
arm7_9->thumb_bkpt = 0xdeee;
-
+
arm7_9->dbgreq_adjust_pc = 2;
arm7_9->arch_info = arm7tdmi;
arm7tdmi->arch_info = NULL;
arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
-
+
if (variant)
{
arm7tdmi->variant = strdup(variant);
{
arm7tdmi->variant = strdup("");
}
-
+
arm7_9_init_arch_info(target, arm7_9);
return ERROR_OK;
int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
{
arm7tdmi_common_t *arm7tdmi;
-
+
arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
-
+
arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant);
-
+
return ERROR_OK;
}
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
-
+
retval = arm7_9_register_commands(cmd_ctx);
-
+
return retval;
}
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm920t_soft_reset_halt,
-
+
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm920t_read_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
-
+
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint,
u8 access_type_buf = 1;
u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 0;
-
- jtag_add_end_state(TAP_RTI);
+
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[3].in_check_mask = NULL;
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
-
+
jtag_add_dr_scan(4, fields, -1);
fields[1].in_handler_priv = value;
u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 1;
u8 value_buf[4];
-
+
buf_set_u32(value_buf, 0, 32, value);
-
- jtag_add_end_state(TAP_RTI);
+
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[3].in_check_mask = NULL;
fields[3].in_handler = NULL;
fields[3].in_handler_priv = NULL;
-
+
jtag_add_dr_scan(4, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
u8 reg_addr_buf = 0x0;
u8 nr_w_buf = 0;
u8 cp15_opcode_buf[4];
-
- jtag_add_end_state(TAP_RTI);
+
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
+
buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
fields[0].tap = jtag_info->tap;
retval = arm7_9_execute_sys_speed(target);
if (retval != ERROR_OK)
return retval;
-
+
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("failed executing JTAG queue, exiting");
return retval;
}
-
+
return ERROR_OK;
}
/* load address into R1 */
regs[1] = address;
- arm9tdmi_write_core_regs(target, 0x2, regs);
-
- /* read-modify-write CP15 test state register
+ arm9tdmi_write_core_regs(target, 0x2, regs);
+
+ /* read-modify-write CP15 test state register
* to enable interpreted access mode */
- arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+ arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
jtag_execute_queue();
cp15c15 |= 1; /* set interpret mode */
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
/* execute CP15 instruction and ARM load (reading from coprocessor) */
arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
-
+
/* disable interpreted access mode */
cp15c15 &= ~1U; /* clear interpret mode */
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
regs_p[0] = value;
arm9tdmi_read_core_regs(target, 0x1, regs_p);
jtag_execute_queue();
-
+
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
#endif
regs[1] = address;
arm9tdmi_write_core_regs(target, 0x3, regs);
- /* read-modify-write CP15 test state register
+ /* read-modify-write CP15 test state register
* to enable interpreted access mode */
arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
jtag_execute_queue();
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
-
+
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
-
+
return ERROR_OK;
}
/* read cp15 control register */
arm920t_read_cp15_physical(target, 0x2, &cp15_control);
jtag_execute_queue();
-
+
if (mmu)
cp15_control &= ~0x1U;
-
+
if (d_u_cache)
cp15_control &= ~0x4U;
-
+
if (i_cache)
cp15_control &= ~0x1000U;
/* read cp15 control register */
arm920t_read_cp15_physical(target, 0x2, &cp15_control);
jtag_execute_queue();
-
+
if (mmu)
cp15_control |= 0x1U;
-
+
if (d_u_cache)
cp15_control |= 0x4U;
-
+
if (i_cache)
cp15_control |= 0x1000U;
-
+
arm920t_write_cp15_physical(target, 0x2, cp15_control);
}
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm920t_common_t *arm920t = arm9tdmi->arch_info;
-
+
/* examine cp15 control reg */
arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
jtag_execute_queue();
arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
-
+
LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
- arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
+ arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
if (arm920t->preserve_cache)
{
- /* read-modify-write CP15 test state register
+ /* read-modify-write CP15 test state register
* to disable I/D-cache linefills */
arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
jtag_execute_queue();
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm920t_common_t *arm920t = arm9tdmi->arch_info;
-
+
/* restore i/d fault status and address register */
arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
-
- /* read-modify-write CP15 test state register
+
+ /* read-modify-write CP15 test state register
* to reenable I/D-cache linefills */
if (arm920t->preserve_cache)
{
arm7_9_common_t *arm7_9;
arm9tdmi_common_t *arm9tdmi;
arm920t_common_t *arm920t;
-
+
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
return -1;
}
-
+
arm7_9 = armv4_5->arch_info;
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
{
return -1;
}
-
+
arm9tdmi = arm7_9->arch_info;
if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
{
return -1;
}
-
+
arm920t = arm9tdmi->arch_info;
if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
{
return -1;
}
-
+
*armv4_5_p = armv4_5;
*arm7_9_p = arm7_9;
*arm9tdmi_p = arm9tdmi;
*arm920t_p = arm920t;
-
+
return ERROR_OK;
}
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm920t_common_t *arm920t = arm9tdmi->arch_info;
-
- char *state[] =
+
+ char *state[] =
{
"disabled", "enabled"
};
-
+
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
-
+
LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm920t->armv4_5_mmu.mmu_enabled],
- state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
+ state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
-
+
return ERROR_OK;
}
int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
{
int retval;
-
+
retval = arm7_9_read_memory(target, address, size, count, buffer);
-
+
return retval;
}
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm920t_common_t *arm920t = arm9tdmi->arch_info;
-
+
if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
return retval;
if (cb == 3)
armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
}
-
+
if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
{
LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
arm920t_common_t *arm920t = arm9tdmi->arch_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
-
+
if((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
-
+
long long then=timeval_ms();
int timeout;
while (!(timeout=((timeval_ms()-then)>1000)))
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
-
+
target->state = TARGET_HALTED;
-
+
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
-
+
/* start fetching from 0x0 */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
armv4_5->core_cache->reg_list[15].dirty = 1;
armv4_5->core_cache->reg_list[15].valid = 1;
-
+
armv4_5->core_mode = ARMV4_5_MODE_SVC;
armv4_5->core_state = ARMV4_5_STATE_ARM;
-
+
arm920t_disable_mmu_caches(target, 1, 1, 1);
arm920t->armv4_5_mmu.mmu_enabled = 0;
arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
{
return retval;
}
-
+
return ERROR_OK;
}
int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
arm9tdmi_init_target(cmd_ctx, target);
-
+
return ERROR_OK;
-
+
}
int arm920t_quit(void)
{
-
+
return ERROR_OK;
}
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
-
+
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm920t;
arm920t->common_magic = ARM920T_COMMON_MAGIC;
-
+
arm7_9->post_debug_entry = arm920t_post_debug_entry;
arm7_9->pre_restore_context = arm920t_pre_restore_context;
-
+
arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
arm920t->armv4_5_mmu.has_tiny_pages = 1;
arm920t->armv4_5_mmu.mmu_enabled = 0;
-
+
/* disabling linefills leads to lockups, so keep them enabled for now
* this doesn't affect correctness, but might affect timing issues, if
* important data is evicted from the cache during the debug session
* */
arm920t->preserve_cache = 0;
-
+
/* override hw single-step capability from ARM9TDMI */
arm7_9->has_single_step = 1;
-
+
return ERROR_OK;
}
int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
{
arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
-
+
arm920t_init_arch_info(target, arm920t, target->tap, target->variant);
return ERROR_OK;
{
int retval;
command_t *arm920t_cmd;
-
-
+
+
retval = arm9tdmi_register_commands(cmd_ctx);
-
+
arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
FILE *output;
arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
int segment, index;
-
+
if (argc != 1)
{
command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
return ERROR_OK;
}
-
+
if ((output = fopen(args[0], "w")) == NULL)
{
LOG_DEBUG("error opening cache content file");
return ERROR_OK;
}
-
+
for (i = 0; i < 16; i++)
regs_p[i] = ®s[i];
-
+
if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
{
command_print(cmd_ctx, "current target isn't an ARM920t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
if((retval = jtag_execute_queue()) != ERROR_OK)
cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
- /* read CP15 test state register */
+ /* read CP15 test state register */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
jtag_execute_queue();
-
+
/* read DCache content */
fprintf(output, "DCache:\n");
-
- /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
+
+ /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
{
fprintf(output, "\nsegment: %i\n----------", segment);
-
+
/* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
regs[0] = 0x0 | (segment << 5);
arm9tdmi_write_core_regs(target, 0x1, regs);
-
+
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* D CAM Read, loads current victim into C15.C.D.Ind */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
-
+
/* read current victim */
arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Write DCache victim */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
-
+
/* Read D RAM */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
-
+
/* Read D CAM */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
}
d_cache[segment][index].cam = regs[9];
-
+
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
-
+
for (i = 1; i < 9; i++)
{
d_cache[segment][index].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
}
-
+
}
-
+
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Write DCache victim */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
/* read ICache content */
fprintf(output, "ICache:\n");
-
- /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
+
+ /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
{
fprintf(output, "segment: %i\n----------", segment);
-
+
/* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
regs[0] = 0x0 | (segment << 5);
arm9tdmi_write_core_regs(target, 0x1, regs);
-
+
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* I CAM Read, loads current victim into C15.C.I.Ind */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
-
+
/* read current victim */
arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Write ICache victim */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
-
+
/* Read I RAM */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
-
+
/* Read I CAM */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
}
i_cache[segment][index].cam = regs[9];
-
+
/* mask LFSR[6] */
regs[9] &= 0xfffffffe;
fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
-
+
for (i = 1; i < 9; i++)
{
i_cache[segment][index].data[i] = regs[i];
fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
}
-
+
}
-
-
+
+
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Write ICache victim */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
}
-
+
/* restore CP15 MMU and Cache settings */
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
-
+
command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
-
+
fclose(output);
-
+
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
-
+
return ERROR_OK;
}
u32 Dlockdown, Ilockdown;
arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
int victim;
-
+
if (argc != 1)
{
command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
return ERROR_OK;
}
-
+
if ((output = fopen(args[0], "w")) == NULL)
{
LOG_DEBUG("error opening mmu content file");
return ERROR_OK;
}
-
+
for (i = 0; i < 16; i++)
regs_p[i] = ®s[i];
-
+
if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
{
command_print(cmd_ctx, "current target isn't an ARM920t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
if((retval = jtag_execute_queue()) != ERROR_OK)
cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
- /* read CP15 test state register */
+ /* read CP15 test state register */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
- /* prepare reading D TLB content
+ /* prepare reading D TLB content
* */
-
+
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Read D TLB lockdown */
arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
-
+
/* read D TLB lockdown stored to r1 */
arm9tdmi_read_core_regs(target, 0x2, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
}
Dlockdown = regs[1];
-
+
for (victim = 0; victim < 64; victim += 8)
{
- /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
+ /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63 */
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
-
+
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Write D TLB lockdown */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
-
+
/* Read D TLB CAM */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
-
+
/* read D TLB CAM content stored to r2-r9 */
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
for (i = 0; i < 8; i++)
- d_tlb[victim + i].cam = regs[i + 2];
+ d_tlb[victim + i].cam = regs[i + 2];
}
for (victim = 0; victim < 64; victim++)
{
- /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
+ /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63 */
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
-
+
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Write D TLB lockdown */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
-
+
/* Read D TLB RAM1 */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
/* Read D TLB RAM2 */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
-
+
/* read D TLB RAM content stored to r2 and r3 */
arm9tdmi_read_core_regs(target, 0xc, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
}
- d_tlb[victim].ram1 = regs[2];
- d_tlb[victim].ram2 = regs[3];
+ d_tlb[victim].ram1 = regs[2];
+ d_tlb[victim].ram2 = regs[3];
}
-
+
/* restore D TLB lockdown */
regs[1] = Dlockdown;
arm9tdmi_write_core_regs(target, 0x2, regs);
-
+
/* Write D TLB lockdown */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
- /* prepare reading I TLB content
+ /* prepare reading I TLB content
* */
-
+
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Read I TLB lockdown */
arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
-
+
/* read I TLB lockdown stored to r1 */
arm9tdmi_read_core_regs(target, 0x2, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
}
Ilockdown = regs[1];
-
+
for (victim = 0; victim < 64; victim += 8)
{
- /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
+ /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63 */
regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
-
+
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Write I TLB lockdown */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
-
+
/* Read I TLB CAM */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
-
+
/* read I TLB CAM content stored to r2-r9 */
arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
for (i = 0; i < 8; i++)
- i_tlb[i + victim].cam = regs[i + 2];
+ i_tlb[i + victim].cam = regs[i + 2];
}
for (victim = 0; victim < 64; victim++)
{
- /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
+ /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63 */
regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
-
+
/* set interpret mode */
cp15c15 |= 0x1;
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
-
+
/* Write I TLB lockdown */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
-
+
/* Read I TLB RAM1 */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
/* Read I TLB RAM2 */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
-
+
/* clear interpret mode */
cp15c15 &= ~0x1;
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
-
+
/* read I TLB RAM content stored to r2 and r3 */
arm9tdmi_read_core_regs(target, 0xc, regs_p);
if((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
}
- i_tlb[victim].ram1 = regs[2];
- i_tlb[victim].ram2 = regs[3];
+ i_tlb[victim].ram1 = regs[2];
+ i_tlb[victim].ram2 = regs[3];
}
-
+
/* restore I TLB lockdown */
regs[1] = Ilockdown;
arm9tdmi_write_core_regs(target, 0x2, regs);
-
+
/* Write I TLB lockdown */
arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
-
+
/* restore CP15 MMU and Cache settings */
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
- /* output data to file */
+ /* output data to file */
fprintf(output, "D TLB content:\n");
for (i = 0; i < 64; i++)
{
{
fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
}
-
+
command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
-
+
fclose(output);
-
+
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
-
+
return ERROR_OK;
}
int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
command_print(cmd_ctx, "current target isn't an ARM920t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
{
return retval;
}
-
+
command_print(cmd_ctx, "%i: %8.8x", address, value);
}
else if (argc == 2)
command_print(cmd_ctx, "current target isn't an ARM920t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
return ERROR_OK;
}
-
+
command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
}
else if (argc == 2)
arm7_9_common_t *arm7_9;
arm9tdmi_common_t *arm9tdmi;
arm920t_common_t *arm920t;
-
+
if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
{
command_print(cmd_ctx, "current target isn't an ARM920t target");
return ERROR_OK;
}
-
+
return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
}
int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
+{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
command_print(cmd_ctx, "current target isn't an ARM920t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK;
}
-
+
return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
}
int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
+{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
command_print(cmd_ctx, "current target isn't an ARM920t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK;
}
-
+
return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
}
int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
+{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
command_print(cmd_ctx, "current target isn't an ARM920t target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK;
}
-
+
return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
}
buf_set_u32(address_buf, 0, 14, address);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
buf_set_u32(address_buf, 0, 14, address);
buf_set_u32(value_buf, 0, 32, value);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
default:
LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
target->debug_reason = DBG_REASON_DBGRQ;
- /* if we fail here, we won't talk to the target and it will
+ /* if we fail here, we won't talk to the target and it will
* be reported to be in the halted state */
retval = ERROR_TARGET_FAILURE;
break;
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
-
+
.run_algorithm = armv4_5_run_algorithm,
-
+
.add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint,
int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
arm9tdmi_init_target(cmd_ctx, target);
-
+
return ERROR_OK;
}
int arm966e_quit(void)
{
-
+
return ERROR_OK;
}
{
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
-
+
arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant);
arm9tdmi->arch_info = arm966e;
arm966e->common_magic = ARM966E_COMMON_MAGIC;
-
+
/* The ARM966E-S implements the ARMv5TE architecture which
* has the BKPT instruction, so we don't have to use a watchpoint comparator
*/
arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
-
+
return ERROR_OK;
}
int arm966e_target_create( struct target_s *target, Jim_Interp *interp )
{
arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
-
+
arm966e_init_arch_info(target, arm966e, target->tap, target->variant);
return ERROR_OK;
arm7_9_common_t *arm7_9;
arm9tdmi_common_t *arm9tdmi;
arm966e_common_t *arm966e;
-
+
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
return -1;
}
-
+
arm7_9 = armv4_5->arch_info;
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
{
return -1;
}
-
+
arm9tdmi = arm7_9->arch_info;
if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
{
return -1;
}
-
+
arm966e = arm9tdmi->arch_info;
if (arm966e->common_magic != ARM966E_COMMON_MAGIC)
{
return -1;
}
-
+
*armv4_5_p = armv4_5;
*arm7_9_p = arm7_9;
*arm9tdmi_p = arm9tdmi;
*arm966e_p = arm966e;
-
+
return ERROR_OK;
}
scan_field_t fields[3];
u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 0;
-
- jtag_add_end_state(TAP_RTI);
+
+ jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
-
+
jtag_add_dr_scan(3, fields, -1);
fields[0].in_handler_priv = value;
u8 reg_addr_buf = reg_addr & 0x3f;
u8 nr_w_buf = 1;
u8 value_buf[4];
-
+
buf_set_u32(value_buf, 0, 32, value);
-
- jtag_add_end_state(TAP_RTI);
+
+ jtag_add_end_state(TAP_IDLE);
if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
{
return retval;
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
-
+
jtag_add_dr_scan(3, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
command_print(cmd_ctx, "current target isn't an ARM966e target");
return ERROR_OK;
}
-
+
jtag_info = &arm7_9->jtag_info;
-
+
if (target->state != TARGET_HALTED)
{
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
{
return retval;
}
-
+
command_print(cmd_ctx, "%i: %8.8x", address, value);
}
else if (argc == 2)
{
int retval;
command_t *arm966e_cmd;
-
+
retval = arm9tdmi_register_commands(cmd_ctx);
arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands");
register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
-
+
return retval;
}
int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm9tdmi_quit(void);
-
+
target_type_t arm9tdmi_target =
{
.name = "arm9tdmi",
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
-
+
.run_algorithm = armv4_5_run_algorithm,
-
+
.add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint,
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
u8 instructionbus[4];
u8 debug_reason;
- jtag_add_end_state(TAP_PD);
+ jtag_add_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 32;
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
-
+
fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
-
+
fields[2].tap = arm7_9->jtag_info.tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
-
+
if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
- jtag_add_dr_scan(3, fields, TAP_PD);
+ jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
fields[0].in_value = NULL;
fields[0].out_value = databus;
fields[1].in_value = NULL;
fields[1].out_value = &debug_reason;
fields[2].in_value = NULL;
fields[2].out_value = instructionbus;
-
- jtag_add_dr_scan(3, fields, TAP_PD);
+
+ jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
if (debug_reason & 0x4)
if (debug_reason & 0x2)
u8 out_buf[4];
u8 instr_buf[4];
u8 sysspeed_buf = 0x0;
-
+
/* prepare buffer */
buf_set_u32(out_buf, 0, 32, out);
-
+
buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
-
+
if (sysspeed)
buf_set_u32(&sysspeed_buf, 2, 1, 1);
-
- jtag_add_end_state(TAP_PD);
+
+ jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
-
+
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
+
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
}
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
-
+
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
-
+
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1);
-
+
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
if (in)
{
LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
int retval = ERROR_OK;;
scan_field_t fields[3];
- jtag_add_end_state(TAP_PD);
+ jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
-
+
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
+
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_handler_priv = in;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
-
+
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
-
+
jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1);
-
+
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
if (in)
{
LOG_DEBUG("in: 0x%8.8x", *in);
{
int retval = ERROR_OK;
scan_field_t fields[3];
-
- jtag_add_end_state(TAP_PD);
+
+ jtag_add_end_state(TAP_DRPAUSE);
if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
{
return retval;
}
-
+
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
+
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_handler_priv = in;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
-
+
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
-
+
jtag_add_dr_scan(3, fields, -1);
jtag_add_runtest(0, -1);
-
+
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
-
+
if (in)
{
LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
- /* save r0 before using it and put system in ARM state
+
+ /* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */
-
+
/* fetch STR r0, [r0] */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
/* STR r0, [r0] in Memory */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
- /* MOV r0, r15 fetched, STR in Decode */
+ /* MOV r0, r15 fetched, STR in Decode */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
/* NOP fetched, BX in Execute (1) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
-
+
if((retval = jtag_execute_queue()) != ERROR_OK)
{
return;
}
-
+
/* fix program counter:
* MOV r0, r15 was the 5th instruction (+8)
* reading PC in Thumb state gives address of instruction + 4
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
u32 *buf_u32 = buffer;
u16 *buf_u16 = buffer;
u8 *buf_u8 = buffer;
-
+
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
/* MSR1 fetched */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
-
+
/* MSR fetched */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
/* NOP fetched, MSR in DECODE */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
/* NOP fetched, MSR in EXECUTE (1) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
-
+
/* rot == 4 writes flags, which takes only one cycle */
if (rot != 4)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
}
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
-
+
}
void arm9tdmi_load_word_regs(target_t *target, u32 mask)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* put system-speed load half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
void arm9tdmi_branch_resume_thumb(target_t *target)
{
LOG_DEBUG("-");
-
+
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
/* Branch and eXchange */
arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
-
+
embeddedice_read_reg(dbg_stat);
-
+
/* fetch NOP, BX in DECODE stage */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
-
+
embeddedice_read_reg(dbg_stat);
-
+
/* fetch NOP, BX in EXECUTE stage (1st cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
-
+
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
embeddedice_read_reg(dbg_stat);
-
+
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+
if (arm7_9->has_single_step)
{
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+
if (arm7_9->has_single_step)
{
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
return ERROR_FAIL;
(*cache_p) = t;
arm7_9->eice_cache = (*cache_p);
-
+
if (arm7_9->etm_ctx)
{
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
-
+
arm9tdmi_build_reg_cache(target);
-
+
return ERROR_OK;
-
+
}
int arm9tdmi_quit(void)
{
-
+
return ERROR_OK;
}
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
-
+
arm7_9 = &arm9tdmi->arm7_9_common;
armv4_5 = &arm7_9->armv4_5_common;
-
+
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 5;
-
+
/* register arch-specific functions */
arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
arm7_9->change_to_arm = arm9tdmi_change_to_arm;
arm7_9->read_core_regs = arm9tdmi_read_core_regs;
arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
arm7_9->read_xpsr = arm9tdmi_read_xpsr;
-
+
arm7_9->write_xpsr = arm9tdmi_write_xpsr;
arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
arm7_9->write_core_regs = arm9tdmi_write_core_regs;
-
+
arm7_9->load_word_regs = arm9tdmi_load_word_regs;
arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
-
+
arm7_9->store_word_regs = arm9tdmi_store_word_regs;
arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
-
+
arm7_9->write_pc = arm9tdmi_write_pc;
arm7_9->branch_resume = arm9tdmi_branch_resume;
arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
arm7_9->enable_single_step = arm9tdmi_enable_single_step;
arm7_9->disable_single_step = arm9tdmi_disable_single_step;
-
+
arm7_9->pre_debug_entry = NULL;
arm7_9->post_debug_entry = NULL;
-
+
arm7_9->pre_restore_context = NULL;
arm7_9->post_restore_context = NULL;
/* initialize arch-specific breakpoint handling */
arm7_9->arm_bkpt = 0xdeeedeee;
arm7_9->thumb_bkpt = 0xdeee;
-
+
arm7_9->dbgreq_adjust_pc = 3;
arm7_9->arch_info = arm9tdmi;
-
+
arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
arm9tdmi->arch_info = NULL;
{
arm9tdmi->variant = strdup("");
}
-
+
arm7_9_init_arch_info(target, arm7_9);
/* override use of DBGRQ, this is safe on ARM9TDMI */
/* all ARM9s have the vector catch register */
arm7_9->has_vector_catch = 1;
-
+
return ERROR_OK;
}
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9;
arm9tdmi_common_t *arm9tdmi;
-
+
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
return -1;
}
-
+
arm7_9 = armv4_5->arch_info;
if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
{
return -1;
}
-
+
arm9tdmi = arm7_9->arch_info;
if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
{
return -1;
}
-
+
*armv4_5_p = armv4_5;
*arm7_9_p = arm7_9;
*arm9tdmi_p = arm9tdmi;
-
+
return ERROR_OK;
}
arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant);
-
+
return ERROR_OK;
}
int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
-
+
command_t *arm9tdmi_cmd;
-
-
+
+
retval = arm7_9_register_commands(cmd_ctx);
-
+
arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
-
-
+
+
return retval;
}
reg_t *vector_catch;
u32 vector_catch_value;
int i, j;
-
+
if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
{
command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
return ERROR_OK;
}
-
+
vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
-
+
/* read the vector catch register if necessary */
if (!vector_catch->valid)
embeddedice_read_reg(vector_catch);
-
+
/* get the current setting */
vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
-
+
if (argc > 0)
{
vector_catch_value = 0x0;
break;
}
}
-
+
/* complain if vector wasn't found */
if (!arm9tdmi_vectors[j].name)
{
command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
-
+
/* reread current setting */
vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
-
+
break;
}
}
}
-
+
/* store new settings */
buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
embeddedice_store_reg(vector_catch);
}
-
+
/* output current settings (skip RESERVED vector) */
for (i = 0; i < 8; i++)
{
{
command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
(vector_catch_value & (1 << i)) ? "catch" : "don't catch");
- }
+ }
}
return ERROR_OK;
/*
* Transaction Mode:
* swjdp->trans_mode = TRANS_MODE_COMPOSITE;
- * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
+ * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
* result checking until swjdp_end_transaction()
* This must be done before using or deallocating any return variables.
* swjdp->trans_mode == TRANS_MODE_ATOMIC
{
scan_field_t fields[2];
u8 out_addr_buf;
-
- jtag_add_end_state(TAP_RTI);
+
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_set_instr(jtag_info, instr, NULL);
fields[0].tap = jtag_info->tap;
scan_field_t fields[2];
u8 out_value_buf[4];
u8 out_addr_buf;
-
- jtag_add_end_state(TAP_RTI);
+
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_set_instr(jtag_info, instr, NULL);
fields[0].tap = jtag_info->tap;
return ERROR_OK;
}
-/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
+/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
{
swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
{
swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
}
-
+
/* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
{
{
swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
}
-
+
/* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
{
u32 ctrlstat;
keep_alive();
-
+
/* Danger!!!! BROKEN!!!! */
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
+ /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
R956 introduced the check on return value here and now Michael Schwingen reports
that this code no longer works....
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
if ((retval=jtag_execute_queue())!=ERROR_OK)
return retval;
-
+
swjdp->ack = swjdp->ack & 0x7;
-
+
long long then=timeval_ms();
while (swjdp->ack != 2)
{
else
{
u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
-
+
if (ctrlstat & SSTICKYORUN)
LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
-
+
if (ctrlstat & SSTICKYERR)
LOG_ERROR("SWJ-DP STICKY ERROR");
-
+
/* Clear Sticky Error Bits */
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
return retval;
LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
-
- /* Can we find out the reason for the error ?? */
+
+ /* Can we find out the reason for the error ?? */
ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
{
u8 out_value_buf[4];
-
+
buf_set_u32(out_value_buf, 0, 32, value);
swjdp_bankselect_apacc(swjdp, reg_addr);
scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
swjdp->ap_tar_value = tar;
}
if (csw & CSW_ADDRINC_MASK)
- {
+ {
/* Do not cache TAR value when autoincrementing */
swjdp->ap_tar_value = -1;
}
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
-
+
return ERROR_OK;
}
int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
{
ahbap_read_system_u32(swjdp, address, value);
-
+
return swjdp_transaction_endcheck(swjdp);
}
int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
{
ahbap_write_system_u32(swjdp, address, value);
-
+
return swjdp_transaction_endcheck(swjdp);
}
int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
u32 adr = address;
u8* pBuffer = buffer;
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
count >>= 2;
wcount = count;
-
+
/* if we have an unaligned access - reorder data */
if (adr & 0x3u)
{
{
int i;
outvalue = *((u32*)pBuffer);
-
+
for (i = 0; i < 4; i++ )
{
*((u8*)pBuffer + (adr & 0x3)) = outvalue;
pBuffer += 4;
}
}
-
+
while (wcount > 0)
{
/* Adjust to write blocks within 4K aligned boundaries */
blocksize = (0x1000 - (0xFFF & address)) >> 2;
if (wcount < blocksize)
blocksize = wcount;
-
+
/* handle unaligned data at 4k boundary */
if (blocksize == 0)
blocksize = 1;
-
+
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
-
+
for (writecount = 0; writecount < blocksize; writecount++)
{
ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
}
-
+
if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
{
wcount = wcount - blocksize;
{
errorcount++;
}
-
+
if (errorcount > 1)
{
LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
return ERROR_JTAG_DEVICE_ERROR;
}
}
-
+
return retval;
}
u32 outvalue;
int retval = ERROR_OK;
int wcount, blocksize, writecount, i;
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
wcount = count >> 1;
-
+
while (wcount > 0)
{
int nbytes;
-
+
/* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address)) >> 1;
-
+
if (wcount < blocksize)
blocksize = wcount;
-
+
/* handle unaligned data at 4k boundary */
if (blocksize == 0)
blocksize = 1;
-
+
ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
writecount = blocksize;
-
+
do
{
nbytes = MIN((writecount << 1), 4);
-
+
if (nbytes < 4 )
{
if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
-
+
address += nbytes >> 1;
}
else
{
outvalue = *((u32*)buffer);
-
+
for (i = 0; i < nbytes; i++ )
{
*((u8*)buffer + (address & 0x3)) = outvalue;
outvalue >>= 8;
address++;
}
-
+
outvalue = *((u32*)buffer);
ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
return ERROR_JTAG_DEVICE_ERROR;
}
}
-
+
buffer += nbytes >> 1;
writecount -= nbytes >> 1;
-
+
} while (writecount);
wcount -= blocksize;
}
-
+
return retval;
}
{
u32 outvalue;
int retval = ERROR_OK;
-
+
if (count >= 4)
return ahbap_write_buf_packed_u16(swjdp, buffer, count, address);
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
while (count > 0)
{
ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
u32 outvalue;
int retval = ERROR_OK;
int wcount, blocksize, writecount, i;
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
wcount = count;
-
+
while (wcount > 0)
{
int nbytes;
-
+
/* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address));
-
+
if (wcount < blocksize)
blocksize = wcount;
-
+
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
writecount = blocksize;
-
+
do
{
nbytes = MIN(writecount, 4);
-
+
if (nbytes < 4 )
{
if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
-
+
address += nbytes;
}
else
{
outvalue = *((u32*)buffer);
-
+
for (i = 0; i < nbytes; i++ )
{
*((u8*)buffer + (address & 0x3)) = outvalue;
outvalue >>= 8;
address++;
}
-
+
outvalue = *((u32*)buffer);
ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
return ERROR_JTAG_DEVICE_ERROR;
}
}
-
+
buffer += nbytes;
writecount -= nbytes;
-
+
} while (writecount);
wcount -= blocksize;
}
-
+
return retval;
}
{
u32 outvalue;
int retval = ERROR_OK;
-
+
if (count >= 4)
return ahbap_write_buf_packed_u8(swjdp, buffer, count, address);
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
while (count > 0)
{
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
address++;
buffer++;
}
-
+
return retval;
}
int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
u32 adr = address;
u8* pBuffer = buffer;
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
count >>= 2;
wcount = count;
-
+
while (wcount > 0)
{
/* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address)) >> 2;
if (wcount < blocksize)
blocksize = wcount;
-
+
/* handle unaligned data at 4k boundary */
if (blocksize == 0)
blocksize = 1;
-
+
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
-
+
/* Scan out first read */
swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
for (readcount = 0; readcount < blocksize - 1; readcount++)
/* Scan out read instruction and scan in previous value */
swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
}
-
+
/* Scan in last value */
swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
{
wcount = wcount - blocksize;
address += 4 * blocksize;
- buffer += 4 * blocksize;
+ buffer += 4 * blocksize;
}
else
{
errorcount++;
}
-
+
if (errorcount > 1)
{
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
-
+
/* if we have an unaligned access - reorder data */
if (adr & 0x3u)
{
{
int i;
u32 data = *((u32*)pBuffer);
-
+
for (i = 0; i < 4; i++ )
{
*((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
}
}
}
-
+
return retval;
}
u32 invalue;
int retval = ERROR_OK;
int wcount, blocksize, readcount, i;
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
wcount = count >> 1;
-
+
while (wcount > 0)
{
int nbytes;
-
+
/* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address)) >> 1;
if (wcount < blocksize)
blocksize = wcount;
-
+
ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
-
+
/* handle unaligned data at 4k boundary */
if (blocksize == 0)
blocksize = 1;
readcount = blocksize;
-
+
do
{
ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
-
+
nbytes = MIN((readcount << 1), 4);
-
+
for (i = 0; i < nbytes; i++ )
{
*((u8*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++;
address++;
}
-
+
readcount -= (nbytes >> 1);
} while (readcount);
wcount -= blocksize;
}
-
+
return retval;
}
{
u32 invalue, i;
int retval = ERROR_OK;
-
+
if (count >= 4)
return ahbap_read_buf_packed_u16(swjdp, buffer, count, address);
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
while (count > 0)
{
ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
u32 invalue;
int retval = ERROR_OK;
int wcount, blocksize, readcount, i;
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
wcount = count;
-
+
while (wcount > 0)
{
int nbytes;
-
+
/* Adjust to read within 4K block boundaries */
blocksize = (0x1000 - (0xFFF & address));
-
+
if (wcount < blocksize)
blocksize = wcount;
-
+
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
readcount = blocksize;
-
+
do
{
ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
-
+
nbytes = MIN(readcount, 4);
-
+
for (i = 0; i < nbytes; i++ )
{
*((u8*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++;
address++;
}
-
+
readcount -= nbytes;
} while (readcount);
wcount -= blocksize;
}
-
+
return retval;
}
{
u32 invalue;
int retval = ERROR_OK;
-
+
if (count >= 4)
return ahbap_read_buf_packed_u8(swjdp, buffer, count, address);
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
while (count > 0)
{
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
{
int retval;
u32 dcrdr;
-
+
/* because the DCB_DCRDR is used for the emulated dcc channel
* we gave to save/restore the DCB_DCRDR when used */
-
+
ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
/* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
/* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
-
+
retval = swjdp_transaction_endcheck(swjdp);
ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
return retval;
{
int retval;
u32 dcrdr;
-
+
/* because the DCB_DCRDR is used for the emulated dcc channel
* we gave to save/restore the DCB_DCRDR when used */
-
+
ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
-
+
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
+
/* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
/* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
-
+
retval = swjdp_transaction_endcheck(swjdp);
ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
return retval;
u32 ctrlstat;
int cnt = 0;
int retval;
-
+
LOG_DEBUG(" ");
-
+
swjdp->ap_csw_value = -1;
swjdp->ap_tar_value = -1;
swjdp->trans_mode = TRANS_MODE_ATOMIC;
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
-
+
swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
-
+
ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
-
+
LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
-
+
return ERROR_OK;
}
u8 field1_out[1];
u8 field2_out[1];
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
u8 field1_out[1];
u8 field2_out[1];
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(ice_reg->jtag_info, 0x2);
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
u8 field1_out[1];
u8 field2_out[1];
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
else
return ERROR_INVALID_ARGUMENTS;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
scan_field_t fields[3];
int i;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
LOG_DEBUG("%i", etb_reg->addr);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
LOG_DEBUG("%i", etm_reg->addr);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
.assert_reset = feroceon_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm926ejs_soft_reset_halt,
-
+
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = arm7_9_read_memory,
.bulk_write_memory = feroceon_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
-
+
.run_algorithm = armv4_5_run_algorithm,
.add_breakpoint = arm7_9_add_breakpoint,
u8 out_buf[4];
u8 instr_buf[4];
u8 sysspeed_buf = 0x0;
-
+
/* prepare buffer */
buf_set_u32(out_buf, 0, 32, 0);
-
+
buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
-
- jtag_add_end_state(TAP_PD);
+
+ jtag_add_end_state(TAP_DRPAUSE);
arm_jtag_scann(jtag_info, 0x1);
-
+
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
+
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].in_handler_priv = NULL;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
-
+
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
-
+
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
jtag_add_dr_scan(3, fields, -1);
/* no jtag_add_runtest(0, -1) here */
-
+
return ERROR_OK;
}
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/*
- * save r0 before using it and put system in ARM state
+ * save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging
*/
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
void feroceon_branch_resume_thumb(target_t *target)
{
LOG_DEBUG("-");
-
+
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
- (void)(r0); // use R0...
+ (void)(r0); // use R0...
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
-
+
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
* We can't use the dcc flow control bits, so let's transfer data
* with 31 bits and flip the MSB each time a new data word is sent.
*/
- static u32 dcc_code[] =
+ static u32 dcc_code[] =
{
0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */
0xe3a0301e, /* 1: mov r3, #30 */
armv4_5->core_cache->reg_list[0].dirty = 1;
armv4_5->core_state = ARMV4_5_STATE_ARM;
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
/* send data over */
{
u32 y = target_buffer_get_u32(target, buffer);
u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
x = y << (32 - shift);
if (++shift >= 32 || i + 1 >= count)
{
z = (x >> 1) | (flip ^= 0x80000000);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
x = 0;
shift = 1;
}
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
-
+
arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant);
armv4_5 = target->arch_info;
arm7_9->set_special_dbgrq = feroceon_set_dbgrq;
/* only one working comparator */
- arm7_9->wp_available_max = 1;
- arm7_9->wp1_used_default = -1;
+ arm7_9->wp_available_max = 1;
+ arm7_9->wp1_used_default = -1;
return ERROR_OK;
}
retval = arm9tdmi_examine(target);
if (retval!=ERROR_OK)
return retval;
-
+
armv4_5 = target->arch_info;
arm7_9 = armv4_5->arch_info;
-
+
/* the COMMS_CTRL bits are all contiguous */
if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
LOG_ERROR("unexpected Feroceon EICE version signature");
-
- arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
- arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
+
+ arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
+ arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
-
+
/* vector catch reg is not initialized on reset */
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
-
+
/* clear monitor mode, enable comparators */
embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
- jtag_execute_queue();
+ jtag_execute_queue();
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
- buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
+ buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
-
+
return ERROR_OK;
}
{
scan_field_t field;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
{
scan_field_t field;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
{
u32 ejtag_ctrl;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
/* set debug break bit */
.assert_reset = mips_m4k_assert_reset,
.deassert_reset = mips_m4k_deassert_reset,
.soft_reset_halt = mips_m4k_soft_reset_halt,
-
+
.get_gdb_reg_list = mips32_get_gdb_reg_list,
.read_memory = mips_m4k_read_memory,
.bulk_write_memory = mips_m4k_bulk_write_memory,
.checksum_memory = NULL,
.blank_check_memory = NULL,
-
+
.run_algorithm = mips32_run_algorithm,
.add_breakpoint = mips_m4k_add_breakpoint,
};
int mips_m4k_examine_debug_reason(target_t *target)
-{
+{
int break_status;
int retval;
-
+
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
return retval;
target->debug_reason = DBG_REASON_BREAKPOINT;
}
-
+
/* get info about data breakpoint support */
if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
return retval;
target->debug_reason = DBG_REASON_WATCHPOINT;
}
}
-
+
return ERROR_OK;
}
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
u32 debug_reg;
-
+
/* read debug register */
mips_ejtag_read_debug(ejtag_info, &debug_reg);
-
+
/* make sure break uit configured */
mips32_configure_break_unit(target);
-
+
/* attempt to find halt reason */
mips_m4k_examine_debug_reason(target);
-
+
/* clear single step if active */
if (debug_reg & EJTAG_DEBUG_DSS)
{
/* stopped due to single step - clear step bit */
mips_ejtag_config_step(ejtag_info, 0);
}
-
+
mips32_save_context(target);
-
- LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
- *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
+
+ LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
+ *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
-
+
return ERROR_OK;
}
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
-
+
/* read ejtag control reg */
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-
+
/* clear this bit before handling polling
* as after reset registers will read zero */
if (ejtag_ctrl & EJTAG_CTRL_ROCC)
{
/* we have detected a reset, clear flag
* otherwise ejtag will not work */
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
-
+
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("Reset Detected");
}
-
+
/* check for processor halted */
if (ejtag_ctrl & EJTAG_CTRL_BRKST)
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
-
+
target->state = TARGET_HALTED;
-
+
if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
return retval;
-
+
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
else if (target->state == TARGET_DEBUG_RUNNING)
{
target->state = TARGET_HALTED;
-
+
if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
return retval;
-
+
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
}
{
target->state = TARGET_RUNNING;
}
-
+
// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
-
+
return ERROR_OK;
}
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
- LOG_DEBUG("target->state: %s",
+
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
-
+
if (target->state == TARGET_HALTED)
{
LOG_DEBUG("target was already halted");
return ERROR_OK;
}
-
+
if (target->state == TARGET_UNKNOWN)
{
LOG_WARNING("target was in unknown state when halt was requested");
}
-
- if (target->state == TARGET_RESET)
+
+ if (target->state == TARGET_RESET)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
{
* debug entry was already prepared in mips32_prepare_reset_halt()
*/
target->debug_reason = DBG_REASON_DBGRQ;
-
+
return ERROR_OK;
}
}
-
+
/* break processor */
mips_ejtag_enter_debug(ejtag_info);
-
+
target->debug_reason = DBG_REASON_DBGRQ;
-
+
return ERROR_OK;
}
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
mips_m4k_common_t *mips_m4k = mips32->arch_info;
-
- LOG_DEBUG("target->state: %s",
+
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
-
+
if (!(jtag_reset_config & RESET_HAS_SRST))
{
LOG_ERROR("Can't assert SRST");
return ERROR_FAIL;
}
-
+
if (target->reset_halt)
{
/* use hardware to catch reset */
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
}
else
{
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
}
-
+
if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
{
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
jtag_add_reset(0, 1);
}
}
-
+
target->state = TARGET_RESET;
jtag_add_sleep(50000);
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
-
+
return ERROR_OK;
}
int mips_m4k_deassert_reset(target_t *target)
{
- LOG_DEBUG("target->state: %s",
+ LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
-
+
/* deassert reset lines */
jtag_add_reset(0, 0);
-
+
return ERROR_OK;
}
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
+
/* configure single step mode */
mips_ejtag_config_step(ejtag_info, 1);
-
+
/* exit debug mode */
mips_ejtag_exit_debug(ejtag_info, 1);
-
+
mips_m4k_debug_entry(target);
-
+
return ERROR_OK;
}
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
breakpoint_t *breakpoint = NULL;
u32 resume_pc;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (!debug_execution)
{
target_free_all_working_areas(target);
mips_m4k_enable_breakpoints(target);
mips_m4k_enable_watchpoints(target);
}
-
+
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
{
mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
}
-
+
resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
-
+
mips32_restore_context(target);
-
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
{
mips_m4k_set_breakpoint(target, breakpoint);
}
}
-
+
/* exit debug mode - enable interrupts if required */
mips_ejtag_exit_debug(ejtag_info, !debug_execution);
target->debug_reason = DBG_REASON_NOTHALTED;
-
+
/* registers are now invalid */
mips32_invalidate_core_regs(target);
-
+
if (!debug_execution)
{
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
}
-
+
return ERROR_OK;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
-
+
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
mips_m4k_unset_breakpoint(target, breakpoint);
-
+
/* restore context */
mips32_restore_context(target);
-
+
/* configure single step mode */
mips_ejtag_config_step(ejtag_info, 1);
-
+
target->debug_reason = DBG_REASON_SINGLESTEP;
-
+
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-
+
/* exit debug mode */
mips_ejtag_exit_debug(ejtag_info, 1);
-
+
/* registers are now invalid */
mips32_invalidate_core_regs(target);
-
+
if (breakpoint)
mips_m4k_set_breakpoint(target, breakpoint);
LOG_DEBUG("target stepped ");
-
+
mips_m4k_debug_entry(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-
+
return ERROR_OK;
}
void mips_m4k_enable_breakpoints(struct target_s *target)
{
breakpoint_t *breakpoint = target->breakpoints;
-
+
/* set any pending breakpoints */
while (breakpoint)
{
{
mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->inst_break_list;
-
+
if (breakpoint->set)
{
LOG_WARNING("breakpoint already set");
return ERROR_OK;
}
-
+
if (breakpoint->type == BKPT_HARD)
{
int bp_num = 0;
-
+
while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
bp_num++;
if (bp_num >= mips32->num_inst_bpoints)
{
}
-
+
return ERROR_OK;
}
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
-
+
if (breakpoint->type == BKPT_HARD)
{
int bp_num = breakpoint->set - 1;
}
breakpoint->set = 0;
-
+
return ERROR_OK;
}
int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
mips32_common_t *mips32 = target->arch_info;
-
+
if (mips32->num_inst_bpoints_avail < 1)
{
LOG_INFO("no hardware breakpoint available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
/* default to hardware for now */
breakpoint->type = BKPT_HARD;
-
+
mips32->num_inst_bpoints_avail--;
mips_m4k_set_breakpoint(target, breakpoint);
-
+
return ERROR_OK;
}
{
/* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
if (breakpoint->set)
{
mips_m4k_unset_breakpoint(target, breakpoint);
}
-
+
if (breakpoint->type == BKPT_HARD)
mips32->num_inst_bpoints_avail++;
-
+
return ERROR_OK;
}
void mips_m4k_enable_watchpoints(struct target_s *target)
{
watchpoint_t *watchpoint = target->watchpoints;
-
+
/* set any pending watchpoints */
while (watchpoint)
{
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
+
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED)
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
-
+
switch (size)
{
case 4:
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
-
+
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED)
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
-
+
switch (size)
{
case 4:
exit(-1);
break;
}
-
+
return ERROR_OK;
}
int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
-
+
retval = mips32_register_commands(cmd_ctx);
return retval;
}
int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
mips32_build_reg_cache(target);
-
+
return ERROR_OK;
}
int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant)
{
mips32_common_t *mips32 = &mips_m4k->mips32_common;
-
+
if (variant)
{
mips_m4k->variant = strdup(variant);
{
mips_m4k->variant = strdup("");
}
-
+
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
-
+
/* initialize mips4k specific info */
mips32_init_arch_info(target, mips32, tap, variant);
mips32->arch_info = mips_m4k;
-
+
return ERROR_OK;
}
int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
{
mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
-
+
mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant);
-
+
return ERROR_OK;
}
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
u32 idcode = 0;
-
+
if (!target->type->examined)
{
mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
-
+
if (((idcode >> 1) & 0x7FF) == 0x29)
{
/* we are using a pic32mx so select ejtag port
LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
}
}
-
+
/* init rest of ejtag interface */
if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
return retval;
-
+
if ((retval = mips32_examine(target)) != ERROR_OK)
return retval;
-
+
return ERROR_OK;
}
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
- jtag_add_end_state(TAP_PD);
+ jtag_add_end_state(TAP_DRPAUSE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
jtag_add_dr_scan(3, fields, -1);
int i;
- path[0] = TAP_SDS;
- path[1] = TAP_CD;
- path[2] = TAP_SD;
+ path[0] = TAP_DRSELECT;
+ path[1] = TAP_DRCAPTURE;
+ path[2] = TAP_DRSHIFT;
fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
- jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
+ jtag_add_runtest(1, -1); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */
int attempts=0;
fields[1].in_handler_priv = (u8*)&field1[i];
jtag_add_pathmove(3, path);
- jtag_add_dr_scan(3, fields, TAP_RTI);
+ jtag_add_dr_scan(3, fields, TAP_IDLE);
words_scheduled++;
}
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
- path[0] = TAP_SDS;
- path[1] = TAP_CD;
- path[2] = TAP_SD;
+ path[0] = TAP_DRSELECT;
+ path[1] = TAP_DRCAPTURE;
+ path[2] = TAP_DRSHIFT;
- noconsume_path[0] = TAP_SDS;
- noconsume_path[1] = TAP_CD;
- noconsume_path[2] = TAP_E1D;
- noconsume_path[3] = TAP_PD;
- noconsume_path[4] = TAP_E2D;
- noconsume_path[5] = TAP_SD;
+ noconsume_path[0] = TAP_DRSELECT;
+ noconsume_path[1] = TAP_DRCAPTURE;
+ noconsume_path[2] = TAP_DREXIT1;
+ noconsume_path[3] = TAP_DRPAUSE;
+ noconsume_path[4] = TAP_DREXIT2;
+ noconsume_path[5] = TAP_DRSHIFT;
fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 3;
jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
}
- jtag_add_dr_scan(3, fields, TAP_RTI);
+ jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
u8 field2_check_value = 0x0;
u8 field2_check_mask = 0x1;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
LOG_DEBUG("polling RX");
for (;;)
{
- jtag_add_dr_scan(3, fields, TAP_RTI);
+ jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
/* set rx_valid */
field2 = 0x1;
- jtag_add_dr_scan(3, fields, TAP_RTI);
+ jtag_add_dr_scan(3, fields, TAP_IDLE);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
int done_count = 0;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
3,
bits,
t,
- TAP_RTI);
+ TAP_IDLE);
buffer += size;
}
if (ext_dbg_brk != -1)
xscale->external_debug_break = ext_dbg_brk;
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
LOG_DEBUG("loading miniIC at 0x%8.8x", va);
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD is b010 for Main IC and b011 for Mini IC */
scan_field_t fields[2];
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD for invalidate IC line b000, bits [6:4] b000 */
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
- jtag_add_end_state(TAP_RTI);
+ jtag_add_end_state(TAP_IDLE);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
/* set Hold reset, Halt mode and Trap Reset */
if (target->reset_halt)
{
- int retval;
+ int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
/* wait 300ms; 150 and 100ms were not enough */
jtag_add_sleep(300*1000);
- jtag_add_runtest(2030, TAP_RTI);
+ jtag_add_runtest(2030, TAP_IDLE);
jtag_execute_queue();
/* set Hold reset, Halt mode and Trap Reset */
xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
- jtag_add_runtest(30, TAP_RTI);
+ jtag_add_runtest(30, TAP_IDLE);
jtag_add_sleep(100000);
command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
if (dcache)
- command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
+ command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
return ERROR_OK;
}
enum tap_state xsvf_to_tap[] =
{
- TAP_TLR, TAP_RTI,
- TAP_SDS, TAP_CD, TAP_SD, TAP_E1D, TAP_PD, TAP_E2D, TAP_UD,
- TAP_SIS, TAP_CI, TAP_SI, TAP_E1I, TAP_PI, TAP_E2I, TAP_UI,
+ TAP_RESET, TAP_IDLE,
+ TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT, TAP_DREXIT1, TAP_DRPAUSE, TAP_DREXIT2, TAP_DRUPDATE,
+ TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT, TAP_IREXIT1, TAP_IRPAUSE, TAP_IREXIT2, TAP_IRUPDATE,
};
int tap_to_xsvf[] =
/* xsvf has it's own definition of a statemove. This needs
* to be handled according to the specs, which has nothing
* to do with the JTAG spec or OpenOCD as such.
- *
+ *
* Implemented via jtag_add_pathmove().
*/
void xsvf_add_statemove(enum tap_state state)
{
enum tap_state moves[7]; /* max # of transitions */
- int i;
+ int i;
enum tap_state curstate = cmd_queue_cur_state;
u8 move = TAP_MOVE(cmd_queue_cur_state, state);
-
- if ((state != TAP_TLR) && (state == cmd_queue_cur_state))
+
+ if ((state != TAP_RESET) && (state == cmd_queue_cur_state))
return;
- if(state==TAP_TLR)
+ if(state==TAP_RESET)
{
- jtag_add_tlr();
- return;
+ jtag_add_tlr();
+ return;
}
for (i=0; i<7; i++)
{
{
char c;
unsigned char uc;
-
+
while ((read(fd, &c, 1) > 0) && (c == 0x12))
{
if (*path_len > max_path)
}
path[(*path_len)++] = xsvf_to_tap[uc];
}
-
+
lseek(fd, -1, SEEK_CUR);
-
+
return ERROR_OK;
}
int do_abort = 0;
int unsupported = 0;
int tdo_mismatch = 0;
-
+
int runtest_requires_tck = 0;
-
+
jtag_tap_t *tap = NULL;
/* use NULL to indicate a "plain" xsvf file which accounts for
additional devices in the scan chain, otherwise the device
command_print(cmd_ctx, "file %s not found", args[0]);
return ERROR_OK;
}
-
+
if ((argc > 2) && (strcmp(args[2], "virt2") == 0))
{
runtest_requires_tck = 1;
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
- break;
+ break;
}
break;
case 0x01: /* XTDOMASK */
field.in_handler = NULL;
field.in_handler_priv = NULL;
if (tap == NULL)
- jtag_add_plain_ir_scan(1, &field, TAP_PI);
+ jtag_add_plain_ir_scan(1, &field, TAP_IRPAUSE);
else
- jtag_add_ir_scan(1, &field, TAP_PI);
+ jtag_add_ir_scan(1, &field, TAP_IRPAUSE);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
jtag_add_runtest(xruntest, xsvf_to_tap[xendir]);
else
{
- xsvf_add_statemove(TAP_RTI);
+ xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xendir]);
}
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
if (tap == NULL)
- jtag_add_plain_dr_scan(1, &field, TAP_PD);
+ jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE);
else
- jtag_add_dr_scan(1, &field, TAP_PD);
+ jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
- break;
+ break;
}
if (xruntest)
{
jtag_add_runtest(xruntest, xsvf_to_tap[xenddr]);
else
{
- xsvf_add_statemove(TAP_RTI);
+ xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xenddr]);
}
field.in_value = NULL;
jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL);
if (tap == NULL)
- jtag_add_plain_dr_scan(1, &field, TAP_PD);
+ jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE);
else
- jtag_add_dr_scan(1, &field, TAP_PD);
+ jtag_add_dr_scan(1, &field, TAP_DRPAUSE);
if (jtag_execute_queue() != ERROR_OK)
{
tdo_mismatch = 1;
- break;
+ break;
}
if (xruntest)
{
jtag_add_runtest(xruntest, xsvf_to_tap[xenddr]);
else
{
- xsvf_add_statemove(TAP_RTI);
+ xsvf_add_statemove(TAP_IDLE);
jtag_add_sleep(xruntest);
xsvf_add_statemove(xsvf_to_tap[xenddr]);
}
{
int i,lasti;
/* here the trick is that jtag_add_pathmove() must end in a stable
- state, so we must only invoke jtag_add_tlr() when we absolutely
+ state, so we must only invoke jtag_add_tlr() when we absolutely
have to
*/
- for(i=0,lasti=0;i<path_len;i++)
+ for(i=0,lasti=0;i<path_len;i++)
{
- if(path[i]==TAP_TLR)
+ if(path[i]==TAP_RESET)
{
- if(i>lasti)
+ if(i>lasti)
{
jtag_add_pathmove(i-lasti,path+lasti);
}
jtag_add_tlr();
}
}
- if(i>=lasti)
+ if(i>=lasti)
{
jtag_add_pathmove(i-lasti, path+lasti);
}
if (do_abort || unsupported || tdo_mismatch)
break;
}
-
+
if (tdo_mismatch)
{
command_print(cmd_ctx, "TDO mismatch, aborting");
command_print(cmd_ctx, "premature end detected, aborting");
return ERROR_OK;
}
-
+
if (dr_out_buf)
free(dr_out_buf);
-
+
if (dr_in_buf)
free(dr_in_buf);
-
+
if (dr_in_mask)
free(dr_in_mask);
close(xsvf_fd);
-
+
command_print(cmd_ctx, "XSVF file programmed successfully");
return ERROR_OK;
Code Review / openocd.git / commitdiff