static int mips32_read_core_reg(struct target *target, int num)
{
uint32_t reg_value;
- struct mips32_core_reg *mips_core_reg;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
if ((num < 0) || (num >= MIPS32NUMCOREREGS))
return ERROR_INVALID_ARGUMENTS;
- mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
reg_value = mips32->core_regs[num];
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32->core_cache->reg_list[num].valid = 1;
static int mips32_write_core_reg(struct target *target, int num)
{
uint32_t reg_value;
- struct mips32_core_reg *mips_core_reg;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
return ERROR_INVALID_ARGUMENTS;
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
- mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
mips32->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
mips32->core_cache->reg_list[num].valid = 1;
{
target->arch_info = mips32;
mips32->common_magic = MIPS32_COMMON_MAGIC;
+ mips32->fast_data_area = NULL;
/* has breakpoint/watchpint unit been scanned */
mips32->bp_scanned = 0;
}
pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
- if (pc != exit_point)
+ if (exit_point && (pc != exit_point))
{
- LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+ LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
return ERROR_TARGET_TIMEOUT;
}
}
/* refresh core register cache */
- for (unsigned i = 0; i < MIPS32NUMCOREREGS; i++)
+ for (i = 0; i < MIPS32NUMCOREREGS; i++)
{
if (!mips32->core_cache->reg_list[i].valid)
mips32->read_core_reg(target, i);
}
}
- for (int i = 0; i < num_reg_params; i++)
+ for (i = 0; i < num_reg_params; i++)
{
struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
return retval;
}
+ /* check if target endianness settings matches debug control register */
+ if ( ( (dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN) ) ||
+ ( !(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN) ) )
+ {
+ LOG_WARNING("DCR endianness settings does not match target settings");
+ }
+
LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
mips32->num_data_bpoints);
int retval;
uint32_t i;
+ /* see contib/loaders/checksum/mips32.s for src */
+
static const uint32_t mips_crc_code[] =
{
0x248C0000, /* addiu $t4, $a0, 0 */
init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
buf_set_u32(reg_params[1].value, 0, 32, count);
+ int timeout = 20000 * (1 + (count / (1024 * 1024)));
+
if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
- crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), 10000,
+ crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout,
&mips32_info)) != ERROR_OK)
{
destroy_reg_param(®_params[0]);