transport: move files over to transport folder

[openocd.git] / src / target / mips32.c

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 79215b5f3f0d91844c08786b3385bfacd16ba553..65ea6e859193058e863d979f9bc9ddc3366d5590 100644 (file)
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -143,7 +143,6 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
 static int mips32_read_core_reg(struct target *target, int num)
 {
        uint32_t reg_value;
-       struct mips32_core_reg *mips_core_reg;
 
        /* get pointers to arch-specific information */
        struct mips32_common *mips32 = target_to_mips32(target);
@@ -151,7 +150,6 @@ static int mips32_read_core_reg(struct target *target, int num)
        if ((num < 0) || (num >= MIPS32NUMCOREREGS))
                return ERROR_INVALID_ARGUMENTS;
 
-       mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
        reg_value = mips32->core_regs[num];
        buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
        mips32->core_cache->reg_list[num].valid = 1;
@@ -163,7 +161,6 @@ static int mips32_read_core_reg(struct target *target, int num)
 static int mips32_write_core_reg(struct target *target, int num)
 {
        uint32_t reg_value;
-       struct mips32_core_reg *mips_core_reg;
 
        /* get pointers to arch-specific information */
        struct mips32_common *mips32 = target_to_mips32(target);
@@ -172,7 +169,6 @@ static int mips32_write_core_reg(struct target *target, int num)
                return ERROR_INVALID_ARGUMENTS;
 
        reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
-       mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
        mips32->core_regs[num] = reg_value;
        LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
        mips32->core_cache->reg_list[num].valid = 1;
@@ -559,6 +555,13 @@ int mips32_configure_break_unit(struct target *target)
                        return retval;
        }
 
+       /* check if target endianness settings matches debug control register */
+       if ( (  (dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN) ) ||
+               ( !(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN)    ) )
+       {
+               LOG_WARNING("DCR endianness settings does not match target settings");
+       }
+
        LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
                        mips32->num_data_bpoints);