Support for Freescale LS102x SAP

[openocd.git] / src / target / feroceon.c

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index acaa1b3b4846cab63523783a1871cae2c75909c3..f12e4e450628e1c8e62f73bc11158e333594da5e 100644 (file)
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -16,9 +16,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 /*
@@ -64,6 +62,13 @@ static int feroceon_assert_reset(struct target *target)
        struct arm7_9_common *arm7_9 = arm->arch_info;
        int ud = arm7_9->use_dbgrq;
 
+       /* TODO: apply hw reset signal in not examined state */
+       if (!(target_was_examined(target))) {
+               LOG_WARNING("Reset is not asserted because the target is not examined.");
+               LOG_WARNING("Use a reset button or power cycle the target.");
+               return ERROR_TARGET_NOT_EXAMINED;
+       }
+
        arm7_9->use_dbgrq = 0;
        if (target->reset_halt)
                arm7_9_halt(target);
@@ -88,7 +93,7 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
        if (retval != ERROR_OK)
                return retval;
 
-       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+       retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
        if (retval != ERROR_OK)
                return retval;
 
@@ -510,8 +515,7 @@ static int feroceon_bulk_write_memory(struct target *target,
                }
 
                /* copy target instructions to target endianness */
-               for (i = 0; i < dcc_size/4; i++)
-                       target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
+               target_buffer_set_u32_array(target, dcc_code_buf, ARRAY_SIZE(dcc_code), dcc_code);
 
                /* write DCC code to working area, using the non-optimized
                 * memory write to avoid ending up here again */