#ifndef ETM_H
#define ETM_H
-#include "image.h"
#include "trace.h"
-#include "target.h"
-#include "register.h"
#include "arm_jtag.h"
-
#include "armv4_5.h"
-/* ETM registers (V1.3 protocol) */
+struct image_s;
+
+/* ETM registers (JTAG protocol) */
enum
{
ETM_CTRL = 0x00,
ETM_CONFIG = 0x01,
ETM_TRIG_EVENT = 0x02,
- ETM_MMD_CTRL = 0x03,
+ ETM_ASIC_CTRL = 0x03,
ETM_STATUS = 0x04,
ETM_SYS_CONFIG = 0x05,
ETM_TRACE_RESOURCE_CTRL = 0x06,
ETM_TRACE_EN_CTRL2 = 0x07,
ETM_TRACE_EN_EVENT = 0x08,
ETM_TRACE_EN_CTRL1 = 0x09,
+ /* optional FIFOFULL */
ETM_FIFOFULL_REGION = 0x0a,
ETM_FIFOFULL_LEVEL = 0x0b,
+ /* viewdata support */
ETM_VIEWDATA_EVENT = 0x0c,
ETM_VIEWDATA_CTRL1 = 0x0d,
- ETM_VIEWDATA_CTRL2 = 0x0e,
+ ETM_VIEWDATA_CTRL2 = 0x0e, /* optional */
ETM_VIEWDATA_CTRL3 = 0x0f,
+ /* N pairs of ADDR_{COMPARATOR,ACCESS} registers */
ETM_ADDR_COMPARATOR_VALUE = 0x10,
ETM_ADDR_ACCESS_TYPE = 0x20,
+ /* N pairs of DATA_COMPARATOR_{VALUE,MASK} registers */
ETM_DATA_COMPARATOR_VALUE = 0x30,
ETM_DATA_COMPARATOR_MASK = 0x40,
- ETM_COUNTER_INITAL_VALUE = 0x50,
+ /* N quads of COUNTER_{RELOAD_{VALUE,EVENT},ENABLE,VALUE} registers */
+ ETM_COUNTER_RELOAD_VALUE = 0x50,
ETM_COUNTER_ENABLE = 0x54,
- ETM_COUNTER_RELOAD_VALUE = 0x58,
+ ETM_COUNTER_RELOAD_EVENT = 0x58,
ETM_COUNTER_VALUE = 0x5c,
- ETM_SEQUENCER_CTRL = 0x60,
+ /* 6 sequencer event transitions */
+ ETM_SEQUENCER_EVENT = 0x60,
ETM_SEQUENCER_STATE = 0x67,
+ /* N triggered outputs */
ETM_EXTERNAL_OUTPUT = 0x68,
+ /* N task contexts */
ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
};
typedef struct etm_reg_s
{
- int addr;
+ uint32_t value;
+ const struct etm_reg_info *reg_info;
arm_jtag_t *jtag_info;
} etm_reg_t;
typedef struct etmv1_trace_data_s
{
- u8 pipestat; /* bits 0-2 pipeline status */
- u16 packet; /* packet data (4, 8 or 16 bit) */
+ uint8_t pipestat; /* bits 0-2 pipeline status */
+ uint16_t packet; /* packet data (4, 8 or 16 bit) */
int flags; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
} etmv1_trace_data_t;
*/
typedef struct etm_context_s
{
- target_t *target; /* target this ETM is connected to */
- reg_cache_t *reg_cache; /* ETM register cache */
+ target_t *target; /* target this ETM is connected to */
+ reg_cache_t *reg_cache; /* ETM register cache */
etm_capture_driver_t *capture_driver; /* driver used to access ETM data */
- void *capture_driver_priv; /* capture driver private data */
- u32 trigger_percent; /* percent of trace buffer to be filled after the trigger */
+ void *capture_driver_priv; /* capture driver private data */
+ uint32_t trigger_percent; /* how much trace buffer to fill after trigger */
trace_status_t capture_status; /* current state of capture run */
etmv1_trace_data_t *trace_data; /* trace data */
- u32 trace_depth; /* number of trace cycles to be analyzed, 0 if no trace data available */
- etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
- etmv1_tracemode_t tracemode; /* type of information the trace contains (data, addres, contextID, ...) */
- armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
- image_t *image; /* source for target opcodes */
- u32 pipe_index; /* current trace cycle */
- u32 data_index; /* cycle holding next data packet */
- int data_half; /* port half on a 16 bit port */
- u32 current_pc; /* current program counter */
- u32 pc_ok; /* full PC has been acquired */
- u32 last_branch; /* last branch address output */
- u32 last_branch_reason; /* branch reason code for the last branch encountered */
- u32 last_ptr; /* address of the last data access */
- u32 ptr_ok; /* whether last_ptr is valid */
- u32 context_id; /* context ID of the code being traced */
- u32 last_instruction; /* index of last instruction executed (to calculate cycle timings) */
+ uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
+ etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
+ etmv1_tracemode_t tracemode; /* type of info trace contains */
+ armv4_5_state_t core_state; /* current core state */
+ struct image_s *image; /* source for target opcodes */
+ uint32_t pipe_index; /* current trace cycle */
+ uint32_t data_index; /* cycle holding next data packet */
+ bool data_half; /* port half on a 16 bit port */
+ bool pc_ok; /* full PC has been acquired */
+ bool ptr_ok; /* whether last_ptr is valid */
+ uint8_t bcd_vers; /* e.g. 0x13 == ETMv1.3 */
+ uint32_t config; /* cache of ETM_CONFIG value */
+ uint32_t current_pc; /* current program counter */
+ uint32_t last_branch; /* last branch address output */
+ uint32_t last_branch_reason; /* type of last branch encountered */
+ uint32_t last_ptr; /* address of the last data access */
+ uint32_t last_instruction; /* index of last executed (to calc timings) */
} etm_context_t;
/* PIPESTAT values */
BR_ENABLE = 0x1, /* Trace has been enabled */
BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
BR_NODEBUG = 0x3, /* ARM has exited for debug state */
- BR_PERIOD = 0x4, /* Peridioc synchronization point (ETM>=v1.2)*/
+ BR_PERIOD = 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
BR_RSVD5 = 0x5, /* reserved */
BR_RSVD6 = 0x6, /* reserved */
BR_RSVD7 = 0x7, /* reserved */
} etmv1_branch_reason_t;
-extern char *etmv1v1_branch_reason_strings[];
-
extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
-extern int etm_read_reg(reg_t *reg);
-extern int etm_write_reg(reg_t *reg, u32 value);
-extern int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
-extern int etm_store_reg(reg_t *reg);
-extern int etm_set_reg(reg_t *reg, u32 value);
-extern int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
extern int etm_setup(target_t *target);
int etm_register_commands(struct command_context_s *cmd_ctx);
-int etm_register_user_commands(struct command_context_s *cmd_ctx);
-extern etm_context_t* etm_create_context(etm_portmode_t portmode, char *capture_driver_name);
#define ERROR_ETM_INVALID_DRIVER (-1300)
#define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
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