return retvalue;
}
+#if 0
/* Enable interrupts */
int cortex_m3_cpsie(target_t *target, u32 IF)
{
{
return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2);
}
+#endif
int cortex_m3_endreset_event(target_t *target)
{
target_write_u32(target, FP_CTRL, 3);
/* Restore FPB registers */
- for ( i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
+ for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
{
target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
}
/* Restore DWT registers */
- for ( i = 0; i < cortex_m3->dwt_num_comp; i++)
+ for (i = 0; i < cortex_m3->dwt_num_comp; i++)
{
target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp);
target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask);
return retval;
/* Examine target state and mode */
- /* First load register acessible through core debug port*/
+ /* First load register acessible through core debug port*/
for (i = 0; i < ARMV7M_PRIMASK; i++)
{
if (!armv7m->core_cache->reg_list[i].valid)
- armv7m->read_core_reg(target, i);
+ armv7m->read_core_reg(target, i);
}
xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
- /* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/
+ /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
if (xPSR & 0xf00)
{
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
}
-
/* Now we can load SP core registers */
for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++)
{
cortex_m3_examine_exception_reason(target);
}
- DEBUG("entered debug state at PC 0x%x, target->state: %s ", *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
+ DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \
+ *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
if (armv7m->post_debug_entry)
armv7m->post_debug_entry(target);
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
- return ERROR_TARGET_ALREADY_HALTED;
+ return ERROR_OK;
}
if (target->state == TARGET_UNKNOWN)
/* Check that we are using process_context, or change and print warning */
if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
{
- WARNING("Incorrect context in resume");
+ DEBUG("Incorrect context in resume");
armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
}
cortex_m3_enable_breakpoints(target);
cortex_m3_enable_watchpoints(target);
- /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */
+ /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */
}
dcb_dhcsr = DBGKEY | C_DEBUGEN;
/* Check that we are using debug_context, or change and print warning */
if (armv7m_get_context(target) != ARMV7M_DEBUG_CONTEXT)
{
- WARNING("Incorrect context in debug_exec resume");
+ DEBUG("Incorrect context in debug_exec resume");
armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
}
/* Disable interrupts */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ int retval;
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_INVALID_ARGUMENTS;
-
- if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
- return ERROR_TARGET_UNALIGNED_ACCESS;
- /* Is not optimal, autoincrement of tar should be used ( ahbap_block_read and CSW_ADDRINC_SINGLE ) */
+ /* cortex_m3 handles unaligned memory access */
+
switch (size)
{
case 4:
- /* TODOLATER Check error return value ! */
- {
- ahbap_read_buf(swjdp, buffer, 4 * count, address);
- }
+ retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
- {
- ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
- }
+ retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- {
- ahbap_read_buf(swjdp, buffer, count, address);
- }
+ retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
break;
default:
ERROR("BUG: we shouldn't get here");
exit(-1);
}
- return ERROR_OK;
+ return retval;
}
int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ int retval;
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
return ERROR_INVALID_ARGUMENTS;
-
- if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
- return ERROR_TARGET_UNALIGNED_ACCESS;
-
+
switch (size)
{
case 4:
- /* TODOLATER Check error return value ! */
- {
- ahbap_write_buf(swjdp, buffer, 4 * count, address);
- }
+ retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
- {
- ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
- }
+ retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- {
- ahbap_write_buf(swjdp, buffer, count, address);
- }
+ retval = ahbap_write_buf_u8(swjdp, buffer, count, address);
break;
default:
ERROR("BUG: we shouldn't get here");
exit(-1);
}
- return ERROR_OK;
+ return retval;
}
int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
- cortex_m3_write_memory(target, address, 4, count, buffer);
-
- return ERROR_OK;
+ return cortex_m3_write_memory(target, address, 4, count, buffer);
}
void cortex_m3_build_reg_cache(target_t *target)
armv7m->arch_info = cortex_m3;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
- /* armv7m->full_context = cortex_m3_full_context; */
target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);