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allow #include directives to use module name
[openocd.git] / src / target / cortex_a8.c
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index e312e547615842bd45259705a7064f3320530de5..9ca072e0d934a109e03b1e90c628d53eba2642be 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -41,7 +41,7 @@
 
 static int cortex_a8_poll(struct target *target);
 static int cortex_a8_debug_entry(struct target *target);
-static int cortex_a8_restore_context(struct target *target);
+static int cortex_a8_restore_context(struct target *target, bool bpwp);
 static int cortex_a8_set_breakpoint(struct target *target,
                struct breakpoint *breakpoint, uint8_t matchmode);
 static int cortex_a8_unset_breakpoint(struct target *target,
@@ -460,9 +460,70 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
        return cortex_a8_read_dcc(a8, data, &dscr);
 }
 
+static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+               uint32_t addr, uint32_t control)
+{
+       struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+       uint32_t vr = a8->armv7a_common.debug_base;
+       uint32_t cr = a8->armv7a_common.debug_base;
+       int retval;
+
+       switch (index) {
+       case 0 ... 15:          /* breakpoints */
+               vr += CPUDBG_BVR_BASE;
+               cr += CPUDBG_BCR_BASE;
+               break;
+       case 16 ... 31:         /* watchpoints */
+               vr += CPUDBG_WVR_BASE;
+               cr += CPUDBG_WCR_BASE;
+               index -= 16;
+               break;
+       default:
+               return ERROR_FAIL;
+       }
+       vr += 4 * index;
+       cr += 4 * index;
+
+       LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
+                       (unsigned) vr, (unsigned) cr);
+
+       retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+                       vr, addr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+                       cr, control);
+       return retval;
+}
+
+static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+{
+       struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+       uint32_t cr;
+
+       switch (index) {
+       case 0 ... 15:
+               cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
+               break;
+       case 16 ... 31:
+               cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
+               index -= 16;
+               break;
+       default:
+               return ERROR_FAIL;
+       }
+       cr += 4 * index;
+
+       LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
+
+       /* clear control register */
+       return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
+}
+
 static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
 {
        struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+       int retval;
 
        dpm->arm = &a8->armv7a_common.armv4_5_common;
        dpm->didr = didr;
@@ -477,7 +538,14 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
        dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
        dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
 
-       return arm_dpm_setup(dpm);
+       dpm->bpwp_enable = cortex_a8_bpwp_enable;
+       dpm->bpwp_disable = cortex_a8_bpwp_disable;
+
+       retval = arm_dpm_setup(dpm);
+       if (retval == ERROR_OK)
+               retval = arm_dpm_initialize(dpm);
+
+       return retval;
 }
 
 
@@ -602,11 +670,7 @@ static int cortex_a8_resume(struct target *target, int current,
        dap_ap_select(swjdp, swjdp_debugap);
 
        if (!debug_execution)
-       {
                target_free_all_working_areas(target);
-//             cortex_m3_enable_breakpoints(target);
-//             cortex_m3_enable_watchpoints(target);
-       }
 
 #if 0
        if (debug_execution)
@@ -661,7 +725,7 @@ static int cortex_a8_resume(struct target *target, int current,
        armv4_5->core_cache->reg_list[15].dirty = 1;
        armv4_5->core_cache->reg_list[15].valid = 1;
 
-       cortex_a8_restore_context(target);
+       cortex_a8_restore_context(target, handle_breakpoints);
 
 #if 0
        /* the front-end may request us not to handle breakpoints */
@@ -713,7 +777,7 @@ static int cortex_a8_resume(struct target *target, int current,
 static int cortex_a8_debug_entry(struct target *target)
 {
        int i;
-       uint32_t regfile[16], pc, cpsr, dscr;
+       uint32_t regfile[16], wfar, cpsr, dscr;
        int retval = ERROR_OK;
        struct working_area *regfile_working_area = NULL;
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
@@ -749,11 +813,15 @@ static int cortex_a8_debug_entry(struct target *target)
                case 5:         /* vector catch */
                        target->debug_reason = DBG_REASON_BREAKPOINT;
                        break;
+               case 2:         /* asynch watchpoint */
                case 10:        /* precise watchpoint */
                        target->debug_reason = DBG_REASON_WATCHPOINT;
-                       /* REVISIT could collect WFAR later, to see just
-                        * which instruction triggered the watchpoint.
-                        */
+
+                       /* save address of faulting instruction */
+                       retval = mem_ap_read_atomic_u32(swjdp,
+                                       armv7a->debug_base + CPUDBG_WFAR,
+                                       &wfar);
+                       arm_dpm_report_wfar(&armv7a->dpm, wfar);
                        break;
                default:
                        target->debug_reason = DBG_REASON_UNDEFINED;
@@ -781,7 +849,6 @@ static int cortex_a8_debug_entry(struct target *target)
 
                /* read Current PSR */
                cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
-               pc = regfile[15];
                dap_ap_select(swjdp, swjdp_debugap);
                LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
@@ -832,10 +899,7 @@ static int cortex_a8_debug_entry(struct target *target)
        if (armv7a->post_debug_entry)
                armv7a->post_debug_entry(target);
 
-
-
        return retval;
-
 }
 
 static void cortex_a8_post_debug_entry(struct target *target)
@@ -952,7 +1016,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
        return ERROR_OK;
 }
 
-static int cortex_a8_restore_context(struct target *target)
+static int cortex_a8_restore_context(struct target *target, bool bpwp)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
 
@@ -961,7 +1025,7 @@ static int cortex_a8_restore_context(struct target *target)
        if (armv7a->pre_restore_context)
                armv7a->pre_restore_context(target);
 
-       arm_dpm_write_dirty_registers(&armv7a->dpm);
+       arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
 
        if (armv7a->post_restore_context)
                armv7a->post_restore_context(target);
@@ -1280,6 +1344,8 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
                 *
                 * For both ICache and DCache, walk all cache lines in the
                 * address range. Cortex-A8 has fixed 64 byte line length.
+                *
+                * REVISIT per ARMv7, these may trigger watchpoints ...
                 */
 
                /* invalidate I-Cache */
@@ -1465,20 +1531,7 @@ static int cortex_a8_examine_first(struct target *target)
                cortex_a8->brp_list[i].BRPn = i;
        }
 
-       /* Setup Watchpoint Register Pairs */
-       cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
-       cortex_a8->wrp_num_available = cortex_a8->wrp_num;
-       cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp));
-       for (i = 0; i < cortex_a8->wrp_num; i++)
-       {
-               cortex_a8->wrp_list[i].used = 0;
-               cortex_a8->wrp_list[i].type = 0;
-               cortex_a8->wrp_list[i].value = 0;
-               cortex_a8->wrp_list[i].control = 0;
-               cortex_a8->wrp_list[i].WRPn = i;
-       }
-       LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
-                       cortex_a8->brp_num , cortex_a8->wrp_num);
+       LOG_DEBUG("Configured %i hw breakpoints", cortex_a8->brp_num);
 
        target_set_examined(target);
        return ERROR_OK;
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