- /* This algorithm comes from either :
- * Cortex-A8 TRM Example 12-24
- * Cortex-R4 TRM Example 11-25
- * (slight differences)
- */
-
- /* Set DTR access mode to stall mode b01 */
- dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_STALL_MODE;
- retval += mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DSCR, dscr);
-
- /* Write R0 with value 'address' using write procedure for stall mode */
- /* - Write the address for read access into DTRRX */
- retval += mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_DTRRX, address & ~0x3);
- /* - Copy value from DTRRX to R0 using instruction mrc p14, 0, r0, c5, c0 */
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
-
- /* Write the data transfer instruction (ldc p14, c5, [r0],4)
- * and the DTR mode setting to fast mode
- * in one combined write (since they are adjacent registers)
- */
- u8buf_ptr = buf;
- target_buffer_set_u32(target, u8buf_ptr, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
- dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_FAST_MODE;
- target_buffer_set_u32(target, u8buf_ptr + 4, dscr);
- /* group the 2 access CPUDBG_ITR 0x84 and CPUDBG_DSCR 0x88 */
- retval += mem_ap_sel_write_buf(swjdp, armv7a->debug_ap, u8buf_ptr, 4, 2,
- armv7a->debug_base + CPUDBG_ITR);
- if (retval != ERROR_OK)
- goto error_unset_dtr_r;
-
- /* Optimize the read as much as we can, either way we read in a single pass */
- if ((start_byte) || (end_byte)) {
- /* The algorithm only copies 32 bit words, so the buffer
- * should be expanded to include the words at either end.
- * The first and last words will be read into a temp buffer
- * to avoid corruption
- */
- tmp_buff = malloc(total_u32 * 4);
- if (!tmp_buff)
- goto error_unset_dtr_r;