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cortex_a: force cache and tlb bypass when cpu is in debug state
[openocd.git] / src / target / armv7a.h
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 3f2bdd34c71dea7400461522ffe2151daf12b521..8d7bece11724e2d135738756f3658f1ed62271fc 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -172,6 +172,7 @@ target_to_armv7a(struct target *target)
 
 /* See ARMv7a arch spec section C10.7 */
 #define CPUDBG_DSCCR           0x028
+#define CPUDBG_DSMCR           0x02C
 
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS      0xFB8
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