+static int dcc_count;
+static u8 *dcc_buffer;
+
+
+static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
+{
+ int retval = ERROR_OK;
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+
+ if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+ return retval;
+
+ int little=target->endianness==TARGET_LITTLE_ENDIAN;
+ int count=dcc_count;
+ u8 *buffer=dcc_buffer;
+ if (count>2)
+ {
+ /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
+ core function repeated.
+ */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ buffer+=4;
+
+ embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+ u8 reg_addr = ice_reg->addr & 0x1f;
+ int chain_pos = ice_reg->jtag_info->chain_pos;
+
+ embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
+ buffer += (count-2)*4;
+
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ } else
+ {
+ int i;
+ for (i = 0; i < count; i++)
+ {
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
+ }
+
+ if((retval = target_halt(target))!= ERROR_OK)
+ {
+ return retval;
+ }
+ return target_wait_state(target, TARGET_HALTED, 500);
+}
+
+