X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=a9f06df0bae5e2f962463677d9cde19b9409bdb1;hp=d014e4b9589e150166f3421afbbdc68b40361843;hb=09614074b7eafe413935059d19dcc8df020131ab;hpb=fb27b7f8406949cac996529cbd4815f9cf21f23b;ds=sidebyside diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index d014e4b958..a9f06df0ba 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2,9 +2,12 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyvind.harboe@zylin.com * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -35,6 +38,7 @@ #include "log.h" #include "arm7_9_common.h" #include "breakpoints.h" +#include "time_support.h" #include #include @@ -84,7 +88,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } arm7_9->wp_available--; - + /* pick a breakpoint unit */ if (!arm7_9->wp0_used) { @@ -204,20 +208,29 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK) return retval; - + /* did we already set this breakpoint? */ if (breakpoint->set) return ERROR_OK; - + if (breakpoint->length == 4) { u32 verify = 0xffffffff; /* keep the original instruction in target endianness */ - target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); + if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt); + if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK) + { + return retval; + } - target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify); + if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK) + { + return retval; + } if (verify != arm7_9->arm_bkpt) { LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address); @@ -228,11 +241,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { u16 verify = 0xffff; /* keep the original instruction in target endianness */ - target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); + if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */ - target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt); + if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK) + { + return retval; + } - target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify); + if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK) + { + return retval; + } if (verify != arm7_9->thumb_bkpt) { LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address); @@ -248,6 +270,8 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval = ERROR_OK; + armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -269,7 +293,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); arm7_9->wp1_used = 0; } - jtag_execute_queue(); + retval = jtag_execute_queue(); breakpoint->set = 0; } else @@ -279,22 +303,34 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { u32 current_instr; /* check that user program as not modified breakpoint instruction */ - target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr); + if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK) + { + return retval; + } if (current_instr==arm7_9->arm_bkpt) - target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); + if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } else { u16 current_instr; /* check that user program as not modified breakpoint instruction */ - target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr); + if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK) + { + return retval; + } if (current_instr==arm7_9->thumb_bkpt) - target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); + if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } breakpoint->set = 0; } - return ERROR_OK; + return retval; } int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) @@ -307,13 +343,13 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - + if (arm7_9->breakpoint_count==0) { - /* make sure we don't have any dangling breakpoints. This is vital upon - * GDB connect/disconnect + /* make sure we don't have any dangling breakpoints. This is vital upon + * GDB connect/disconnect */ - arm7_9_clear_watchpoints(arm7_9); + arm7_9_clear_watchpoints(arm7_9); } if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1)) @@ -331,7 +367,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { arm7_9->wp_available--; - + if (!arm7_9->wp0_used) { arm7_9->wp0_used = 1; @@ -347,28 +383,35 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_ERROR("BUG: no hardware comparator available"); } } - + arm7_9->breakpoint_count++; - + return arm7_9_set_breakpoint(target, breakpoint); } int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7_9_unset_breakpoint(target, breakpoint); + if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } if (breakpoint->type == BKPT_HARD) arm7_9->wp_available++; - + arm7_9->breakpoint_count--; if (arm7_9->breakpoint_count==0) { /* make sure we don't have any dangling breakpoints */ - arm7_9_clear_watchpoints(arm7_9); + if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK) + { + return retval; + } } return ERROR_OK; @@ -376,6 +419,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; int rw_mask = 1; @@ -404,7 +448,10 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } watchpoint->set = 1; arm7_9->wp0_used = 2; } @@ -418,7 +465,10 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } watchpoint->set = 2; arm7_9->wp1_used = 2; } @@ -433,6 +483,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -451,13 +502,19 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (watchpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } arm7_9->wp0_used = 0; } else if (watchpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } arm7_9->wp1_used = 0; } watchpoint->set = 0; @@ -493,12 +550,16 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; if (watchpoint->set) { - arm7_9_unset_watchpoint(target, watchpoint); + if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK) + { + return retval; + } } arm7_9->wp_available++; @@ -511,7 +572,6 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_execute_sys_speed(struct target_s *target) { - int timeout; int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -527,7 +587,9 @@ int arm7_9_execute_sys_speed(struct target_s *target) } arm_jtag_set_instr(jtag_info, 0x4, NULL); - for (timeout=0; timeout<50; timeout++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -536,9 +598,15 @@ int arm7_9_execute_sys_speed(struct target_s *target) if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1))) break; - usleep(100000); + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } } - if (timeout == 50) + if (timeout) { LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size)); return ERROR_TARGET_TIMEOUT; @@ -590,11 +658,11 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; u32 *data; - int i; + int i, retval = ERROR_OK; data = malloc(size * (sizeof(u32))); - embeddedice_receive(jtag_info, data, size); + retval = embeddedice_receive(jtag_info, data, size); for (i = 0; i < size; i++) { @@ -603,11 +671,12 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) free(data); - return ERROR_OK; + return retval; } int arm7_9_handle_target_request(void *priv) { + int retval = ERROR_OK; target_t *target = priv; if (!target->type->examined) return ERROR_OK; @@ -624,15 +693,24 @@ int arm7_9_handle_target_request(void *priv) { /* read DCC control register */ embeddedice_read_reg(dcc_control); - jtag_execute_queue(); + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } /* check W bit */ if (buf_get_u32(dcc_control->value, 1, 1) == 1) { u32 request; - embeddedice_receive(jtag_info, &request, 1); - target_request(target, request); + if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK) + { + return retval; + } + if ((retval = target_request(target, request)) != ERROR_OK) + { + return retval; + } } } @@ -690,7 +768,10 @@ int arm7_9_poll(target_t *target) } } - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } } if (target->state == TARGET_DEBUG_RUNNING) { @@ -698,7 +779,10 @@ int arm7_9_poll(target_t *target) if ((retval = arm7_9_debug_entry(target)) != ERROR_OK) return retval; - target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK) + { + return retval; + } } if (target->state != TARGET_HALTED) { @@ -726,7 +810,8 @@ int arm7_9_assert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); if (!(jtag_reset_config & RESET_HAS_SRST)) { @@ -779,7 +864,7 @@ int arm7_9_assert_reset(target_t *target) /* debug entry was already prepared in arm7_9_assert_reset() */ target->debug_reason = DBG_REASON_DBGRQ; } - + return ERROR_OK; } @@ -787,7 +872,9 @@ int arm7_9_assert_reset(target_t *target) int arm7_9_deassert_reset(target_t *target) { int retval=ERROR_OK; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + /* deassert reset lines */ jtag_add_reset(0, 0); @@ -803,12 +890,12 @@ int arm7_9_deassert_reset(target_t *target) { return retval; } - + if ((retval=target_halt(target))!=ERROR_OK) { return retval; } - + } return retval; } @@ -873,18 +960,24 @@ int arm7_9_soft_reset_halt(struct target_s *target) if ((retval=target_halt(target))!=ERROR_OK) return retval; - for (i=0; i<10; i++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0) break; embeddedice_read_reg(dbg_stat); if ((retval=jtag_execute_queue())!=ERROR_OK) return retval; - /* do not eat all CPU, time out after 1 se*/ - usleep(100*1000); - + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } } - if (i==10) + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; @@ -899,7 +992,10 @@ int arm7_9_soft_reset_halt(struct target_s *target) buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1); embeddedice_store_reg(dbg_ctrl); - arm7_9_clear_halt(target); + if ((retval = arm7_9_clear_halt(target)) != ERROR_OK) + { + return retval; + } /* if the target is in Thumb state, change to ARM state */ if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) @@ -912,7 +1008,10 @@ int arm7_9_soft_reset_halt(struct target_s *target) } /* all register content is now invalid */ - armv4_5_invalidate_core_regs(target); + if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) + { + return retval; + } /* SVC, ARM state, IRQ and FIQ disabled */ buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); @@ -938,7 +1037,10 @@ int arm7_9_soft_reset_halt(struct target_s *target) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1; } - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } return ERROR_OK; } @@ -955,7 +1057,8 @@ int arm7_9_halt(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); if (target->state == TARGET_HALTED) { @@ -1023,7 +1126,10 @@ int arm7_9_debug_entry(target_t *target) buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1); embeddedice_store_reg(dbg_ctrl); - arm7_9_clear_halt(target); + if ((retval = arm7_9_clear_halt(target)) != ERROR_OK) + { + return retval; + } if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -1130,7 +1236,10 @@ int arm7_9_debug_entry(target_t *target) { u32 spsr; arm7_9->read_xpsr(target, &spsr, 1); - jtag_execute_queue(); + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr); ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1; @@ -1421,7 +1530,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ arm7_9_common_t *arm7_9 = armv4_5->arch_info; breakpoint_t *breakpoint = target->breakpoints; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - int err; + int err, retval = ERROR_OK; LOG_DEBUG("-"); @@ -1446,14 +1555,20 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); - arm7_9_unset_breakpoint(target, breakpoint); + if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } LOG_DEBUG("enable single-step"); arm7_9->enable_single_step(target); target->debug_reason = DBG_REASON_SINGLESTEP; - arm7_9_restore_context(target); + if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + { + return retval; + } if (armv4_5->core_state == ARMV4_5_STATE_ARM) arm7_9->branch_resume(target); @@ -1476,7 +1591,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ if (err != ERROR_OK) { - arm7_9_set_breakpoint(target, breakpoint); + if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } target->state = TARGET_UNKNOWN; return err; } @@ -1485,7 +1603,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); - arm7_9_set_breakpoint(target, breakpoint); + if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } } } @@ -1493,7 +1614,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ arm7_9_enable_breakpoints(target); arm7_9_enable_watchpoints(target); - arm7_9_restore_context(target); + if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + { + return retval; + } if (armv4_5->core_state == ARMV4_5_STATE_ARM) { @@ -1516,7 +1640,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0); embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size)); - arm7_9_restart_core(target); + if ((retval = arm7_9_restart_core(target)) != ERROR_OK) + { + return retval; + } target->debug_reason = DBG_REASON_NOTHALTED; @@ -1525,12 +1652,18 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ /* registers are now invalid */ armv4_5_invalidate_core_regs(target); target->state = TARGET_RUNNING; - target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK) + { + return retval; + } } else { target->state = TARGET_DEBUG_RUNNING; - target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK) + { + return retval; + } } LOG_DEBUG("target resumed"); @@ -1579,7 +1712,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; breakpoint_t *breakpoint = NULL; - int err; + int err, retval; if (target->state != TARGET_HALTED) { @@ -1594,11 +1727,17 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) - arm7_9_unset_breakpoint(target, breakpoint); + if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } target->debug_reason = DBG_REASON_SINGLESTEP; - arm7_9_restore_context(target); + if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + { + return retval; + } arm7_9->enable_single_step(target); @@ -1616,7 +1755,10 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br return ERROR_FAIL; } - target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK) + { + return retval; + } err = arm7_9_execute_sys_speed(target); arm7_9->disable_single_step(target); @@ -1629,12 +1771,18 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br target->state = TARGET_UNKNOWN; } else { arm7_9_debug_entry(target); - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } LOG_DEBUG("target stepped"); } if (breakpoint) - arm7_9_set_breakpoint(target, breakpoint); + if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) + { + return retval; + } return err; @@ -1800,6 +1948,8 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count reg[0] = address; arm7_9->write_core_regs(target, 0x1, reg); + int j=0; + switch (size) { case 4: @@ -1827,6 +1977,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count /* advance buffer, count number of accesses */ buffer += thisrun_accesses * 4; num_accesses += thisrun_accesses; + + if ((j++%1024)==0) + { + keep_alive(); + } } break; case 2: @@ -1845,9 +2000,14 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } + } arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2); @@ -1855,6 +2015,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count /* advance buffer, count number of accesses */ buffer += thisrun_accesses * 2; num_accesses += thisrun_accesses; + + if ((j++%1024)==0) + { + keep_alive(); + } } break; case 1: @@ -1873,9 +2038,13 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } } arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1); @@ -1883,6 +2052,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count /* advance buffer, count number of accesses */ buffer += thisrun_accesses * 1; num_accesses += thisrun_accesses; + + if ((j++%1024)==0) + { + keep_alive(); + } } break; default: @@ -1980,9 +2154,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } num_accesses += thisrun_accesses; } @@ -2012,9 +2190,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } } num_accesses += thisrun_accesses; @@ -2043,9 +2225,14 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) - arm7_9_execute_fast_sys_speed(target); + retval = arm7_9_execute_fast_sys_speed(target); else - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if(retval != ERROR_OK) + { + return retval; + } + } num_accesses += thisrun_accesses; @@ -2086,20 +2273,70 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun return ERROR_OK; } +static int dcc_count; +static u8 *dcc_buffer; + + +static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info) +{ + int retval = ERROR_OK; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + + if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK) + return retval; + + int little=target->endianness==TARGET_LITTLE_ENDIAN; + int count=dcc_count; + u8 *buffer=dcc_buffer; + if (count>2) + { + /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the + core function repeated. + */ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + buffer+=4; + + embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; + u8 reg_addr = ice_reg->addr & 0x1f; + int chain_pos = ice_reg->jtag_info->chain_pos; + + embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2); + buffer += (count-2)*4; + + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + } else + { + int i; + for (i = 0; i < count; i++) + { + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + buffer += 4; + } + } + + if((retval = target_halt(target))!= ERROR_OK) + { + return retval; + } + return target_wait_state(target, TARGET_HALTED, 500); +} + + static const u32 dcc_code[] = { /* MRC TST BNE MRC STR B */ 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9 }; +int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)); + + int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) { + int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - enum armv4_5_state core_state = armv4_5->core_state; - u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); - u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32); - u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); int i; if (!arm7_9->dcc_downloads) @@ -2124,70 +2361,43 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe } /* write DCC code to working area */ - target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf); + if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK) + { + return retval; + } } - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address); - armv4_5->core_cache->reg_list[0].valid = 1; - armv4_5->core_cache->reg_list[0].dirty = 1; - armv4_5->core_state = ARMV4_5_STATE_ARM; + armv4_5_algorithm_t armv4_5_info; + reg_param_t reg_params[1]; - arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); + armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; + armv4_5_info.core_mode = ARMV4_5_MODE_SVC; + armv4_5_info.core_state = ARMV4_5_STATE_ARM; - int little=target->endianness==TARGET_LITTLE_ENDIAN; - if (count>2) - { - /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the - core function repeated. - */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - buffer+=4; + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); - embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; - u8 reg_addr = ice_reg->addr & 0x1f; - int chain_pos = ice_reg->jtag_info->chain_pos; + buf_set_u32(reg_params[0].value, 0, 32, address); - embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2); - buffer += (count-2)*4; + //armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, + // int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)) + dcc_count=count; + dcc_buffer=buffer; + retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, + arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - } else + if (retval==ERROR_OK) { - for (i = 0; i < count; i++) + u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32); + if (endaddress!=(address+count*4)) { - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - buffer += 4; + LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress); + retval=ERROR_FAIL; } } - target_halt(target); - - for (i=0; i<100; i++) - { - target_poll(target); - if (target->state == TARGET_HALTED) - break; - usleep(1000); /* sleep 1ms */ - } - if (i == 100) - { - LOG_ERROR("bulk write timed out, target not halted"); - return ERROR_TARGET_TIMEOUT; - } - - /* restore target state */ - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0); - armv4_5->core_cache->reg_list[0].valid = 1; - armv4_5->core_cache->reg_list[0].dirty = 1; - buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1); - armv4_5->core_cache->reg_list[1].valid = 1; - armv4_5->core_cache->reg_list[1].dirty = 1; - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc); - armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_state = core_state; + destroy_reg_param(®_params[0]); - return ERROR_OK; + return retval; } int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) @@ -2234,7 +2444,12 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++) - target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]); + { + if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK) + { + return retval; + } + } armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; armv4_5_info.core_mode = ARMV4_5_MODE_SVC; @@ -2293,7 +2508,10 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++) - target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]); + if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK) + { + return retval; + } armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; armv4_5_info.core_mode = ARMV4_5_MODE_SVC; @@ -2473,9 +2691,8 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char mode = strtoul(args[1], NULL, 0); value = strtoul(args[2], NULL, 0); - arm7_9_write_core_reg(target, num, mode, value); + return arm7_9_write_core_reg(target, num, mode, value); - return ERROR_OK; } @@ -2580,11 +2797,16 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common; arm7_9->common_magic = ARM7_9_COMMON_MAGIC; - arm_jtag_setup_connection(&arm7_9->jtag_info); + if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK) + { + return retval; + } + arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */ arm7_9->wp_available_max = 2; arm7_9->sw_breakpoints_added = 0; @@ -2613,9 +2835,15 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) armv4_5->write_core_reg = arm7_9_write_core_reg; armv4_5->full_context = arm7_9_full_context; - armv4_5_init_arch_info(target, armv4_5); + if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK) + { + return retval; + } - target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target); + if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK) + { + return retval; + } return ERROR_OK; }