#endif
#include "arm11.h"
-#include "jtag.h"
-#include "log.h"
-#include <stdlib.h>
-#include <string.h>
#if 0
#define JTAG_DEBUG(expr ...) DEBUG(expr)
#define JTAG_DEBUG(expr ...) do {} while(0)
#endif
+/*
+This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
+behavior of the FTDI driver IIRC was to go via RTI.
+
+Conversely there may be other places in this code where the ARM11 code relies
+on the driver to hit through RTI when coming from Update-?R.
+*/
tap_state_t arm11_move_pi_to_si_via_ci[] =
{
TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
{
field->tap = arm11->jtag_info.tap;
field->num_bits = num_bits;
- field->out_mask = NULL;
- field->in_check_mask = NULL;
- field->in_check_value = NULL;
- field->in_handler = NULL;
- field->in_handler_priv = NULL;
-
field->out_value = out_data;
field->in_value = in_data;
}
* arm11_add_debug_SCAN_N().
*
*/
-static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field)
+static void arm11_in_handler_SCAN_N(u8 *in_value)
{
/** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
u8 v = *in_value & 0x1F;
if (v != 0x10)
{
LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
- return ERROR_FAIL;
+ jtag_set_error(ERROR_FAIL);
}
JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
- return ERROR_OK;
}
/** Select and write to Scan Chain Register (SCREG)
scan_field_t field;
- arm11_setup_field(arm11, 5, &chain, NULL, &field);
-
- field.in_handler = arm11_in_handler_SCAN_N;
+ u8 tmp[1];
+ arm11_setup_field(arm11, 5, &chain, &tmp, &field);
arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
+
+ jtag_execute_queue_noclear();
+
+ arm11_in_handler_SCAN_N(tmp);
}
/** Write an instruction into the ITR register
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
*value=dscr;
- return retval;
+ return ERROR_OK;
}
/** Write the Debug Status and Control Register (DSCR)
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
+int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- jtag_execute_queue();
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
+
+ return ERROR_OK;
}
* \param count Number of opcodes to execute
*
*/
-void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
+int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
- jtag_execute_queue();
+ CHECK_RETVAL(jtag_execute_queue());
if (flag)
break;
}
}
+
+ return ERROR_OK;
}
/** Execute one instruction via ITR
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
- jtag_execute_queue();
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
+
+ return ERROR_OK;
}
/** JTAG path for arm11_run_instr_data_to_core_noack
* layer (FT2232) that is long enough to finish execution on
* the core but still shorter than any manually inducible delays.
*
+ * To disable this code, try "memwrite burst false"
+ *
*/
tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
{
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+ CHECK_RETVAL(jtag_execute_queue());
size_t error_count = 0;
- {size_t i;
- for (i = 0; i < asizeof(Readies); i++)
+ for (size_t i = 0; i < asizeof(Readies); i++)
{
if (Readies[i] != 1)
{
error_count++;
}
- }}
+ }
if (error_count)
LOG_ERROR("Transfer errors " ZU, error_count);
+
+ return ERROR_OK;
}
* \param data Data word to be passed to the core via DTR
*
*/
-void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
+int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
{
- arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
+ return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
}
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
- jtag_execute_queue();
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
*data++ = Data;
}
+
+ return ERROR_OK;
}
/** Execute one instruction via ITR
* \param count Number of instructions in the list.
*
*/
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
- {size_t i;
- for (i = 0; i < count + 1; i++)
+ for (size_t i = 0; i < count + 1; i++)
{
if (i < count)
{
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
}
}
}
- }}
+ }
- {size_t i;
- for (i = 0; i < count; i++)
+ for (size_t i = 0; i < count; i++)
{
JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
- }}
+ }
+
+ return ERROR_OK;
}
/** Clear VCR and all breakpoints and watchpoints via scan chain 7
arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
arm11_sc7_action_t * pos = clear_bw;
- {size_t i;
- for (i = 0; i < asizeof(clear_bw); i++)
+ for (size_t i = 0; i < asizeof(clear_bw); i++)
{
clear_bw[i].write = true;
clear_bw[i].value = 0;
- }}
+ }
- {size_t i;
- for (i = 0; i < arm11->brp; i++)
+ for (size_t i = 0; i < arm11->brp; i++)
(pos++)->address = ARM11_SC7_BCR0 + i;
- }
- {size_t i;
- for (i = 0; i < arm11->wrp; i++)
+
+ for (size_t i = 0; i < arm11->wrp; i++)
(pos++)->address = ARM11_SC7_WCR0 + i;
- }
+
(pos++)->address = ARM11_SC7_VCR;
* \param result Pointer where to store result
*
*/
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
+int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
{
arm11_run_instr_data_prepare(arm11);
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
+ CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
- arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
arm11_run_instr_data_finish(arm11);
+
+ return ERROR_OK;
}
Code Review / openocd.git / blobdiff