alive_sleep(1);
}
/* Clear but report errors */
- if (status & (FLASH_WRPRTERR|FLASH_PGERR))
+ if (status & (FLASH_WRPRTERR | FLASH_PGERR))
{
- target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR|FLASH_PGERR);
+ target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
}
return status;
}
/* read current option bytes */
target_read_u32(target, STM32_FLASH_OBR, &optiondata);
- stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8|((optiondata >> 2) & 0x07);
+ stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
if (optiondata & (1 << OPT_READOUT))
target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
/* erase option bytes */
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
status = stm32x_wait_status_busy(bank, 10);
target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
/* program option bytes */
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
/* write user option byte */
target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
{
target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
- target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
status = stm32x_wait_status_busy(bank, 10);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
- if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
+ if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
return retval;
/* memory buffer */
if (argc < 4)
{
- command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
+ command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
return ERROR_OK;
}
if (strcmp(args[1], "SWWDG") == 0)
{
- optionbyte |= (1<<0);
+ optionbyte |= (1 << 0);
}
else
{
- optionbyte &= ~(1<<0);
+ optionbyte &= ~(1 << 0);
}
if (strcmp(args[2], "NORSTSTNDBY") == 0)
{
- optionbyte |= (1<<1);
+ optionbyte |= (1 << 1);
}
else
{
- optionbyte &= ~(1<<1);
+ optionbyte &= ~(1 << 1);
}
if (strcmp(args[3], "NORSTSTOP") == 0)
{
- optionbyte |= (1<<2);
+ optionbyte |= (1 << 2);
}
else
{
- optionbyte &= ~(1<<2);
+ optionbyte &= ~(1 << 2);
}
if (stm32x_erase_options(bank) != ERROR_OK)
/* mass erase flash memory */
target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
- target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
status = stm32x_wait_status_busy(bank, 10);