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flash/nor: use command_print() in command "flash banks"
[openocd.git] / src / flash / nor / pic32mx.c
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index 842fd76bba7fc5193fca83ad3c6b3eaeb8a74820..81ffdc400c2640b61498df24124f4fc031991466 100644 (file)
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -19,9 +19,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -52,7 +50,7 @@
 
 /* pic32mx configuration register locations */
 
-#define PIC32MX_DEVCFG0_1_2    0xBFC00BFC
+#define PIC32MX_DEVCFG0_1xx_2xx        0xBFC00BFC
 #define PIC32MX_DEVCFG0                0xBFC02FFC
 #define PIC32MX_DEVCFG1                0xBFC02FF8
 #define PIC32MX_DEVCFG2                0xBFC02FF4
@@ -93,7 +91,8 @@
 #define NVMKEY1                        0xAA996655
 #define NVMKEY2                        0x556699AA
 
-#define MX_1_2                 1       /* PIC32mx1xx/2xx */
+#define MX_1xx_2xx                     1       /* PIC32mx1xx/2xx */
+#define MX_17x_27x                     2       /* PIC32mx17x/27x */
 
 struct pic32mx_flash_bank {
        int probed;
@@ -101,7 +100,7 @@ struct pic32mx_flash_bank {
 };
 
 /*
- * DEVID values as per PIC32MX Flash Programming Specification Rev J
+ * DEVID values as per PIC32MX Flash Programming Specification Rev N
  */
 
 static const struct pic32mx_devs_s {
@@ -120,6 +119,8 @@ static const struct pic32mx_devs_s {
        {0x04D06053, "150F128B"},
        {0x04D08053, "150F128C"},
        {0x04D0A053, "150F128D"},
+       {0x06610053, "170F256B"},
+       {0x0661A053, "170F256D"},
        {0x04A01053, "210F016B"},
        {0x04A03053, "210F016C"},
        {0x04A05053, "210F016D"},
@@ -132,6 +133,24 @@ static const struct pic32mx_devs_s {
        {0x04D00053, "250F128B"},
        {0x04D02053, "250F128C"},
        {0x04D04053, "250F128D"},
+       {0x06600053, "270F256B"},
+       {0x0660A053, "270F256D"},
+       {0x05600053, "330F064H"},
+       {0x05601053, "330F064L"},
+       {0x05602053, "430F064H"},
+       {0x05603053, "430F064L"},
+       {0x0570C053, "350F128H"},
+       {0x0570D053, "350F128L"},
+       {0x0570E053, "450F128H"},
+       {0x0570F053, "450F128L"},
+       {0x05704053, "350F256H"},
+       {0x05705053, "350F256L"},
+       {0x05706053, "450F256H"},
+       {0x05707053, "450F256L"},
+       {0x05808053, "370F512H"},
+       {0x05809053, "370F512L"},
+       {0x0580A053, "470F512H"},
+       {0x0580B053, "470F512L"},
        {0x00938053, "360F512L"},
        {0x00934053, "360F256L"},
        {0x0092D053, "340F128L"},
@@ -260,10 +279,15 @@ static int pic32mx_protect_check(struct flash_bank *bank)
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (pic32mx_info->dev_type == MX_1_2)
-               config0_address = PIC32MX_DEVCFG0_1_2;
-       else
+       switch (pic32mx_info->dev_type) {
+       case    MX_1xx_2xx:
+       case    MX_17x_27x:
+               config0_address = PIC32MX_DEVCFG0_1xx_2xx;
+               break;
+       default:
                config0_address = PIC32MX_DEVCFG0;
+               break;
+       }
 
        target_read_u32(target, config0_address, &devcfg0);
 
@@ -276,10 +300,17 @@ static int pic32mx_protect_check(struct flash_bank *bank)
                        num_pages = 0xffff;             /* All pages protected */
        } else {
                /* pgm flash */
-               if (pic32mx_info->dev_type == MX_1_2)
-                       num_pages = (~devcfg0 >> 10) & 0x3f;
-               else
+               switch (pic32mx_info->dev_type) {
+               case    MX_1xx_2xx:
+                       num_pages = (~devcfg0 >> 10) & 0x7f;
+                       break;
+               case    MX_17x_27x:
+                       num_pages = (~devcfg0 >> 10) & 0x1ff;
+                       break;
+               default:
                        num_pages = (~devcfg0 >> 12) & 0xff;
+                       break;
+               }
        }
 
        for (s = 0; s < bank->num_sectors && s < num_pages; s++)
@@ -410,7 +441,7 @@ static uint32_t pic32mx_flash_write_code[] = {
        0x00000000              /* nop */
 };
 
-static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int pic32mx_write_block(struct flash_bank *bank, const uint8_t *buffer,
                uint32_t offset, uint32_t count)
 {
        struct target *target = bank->target;
@@ -430,27 +461,33 @@ static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer,
                        &write_algorithm) != ERROR_OK) {
                LOG_WARNING("no working area available, can't do block memory writes");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-       };
+       }
 
        /* Change values for counters and row size, depending on variant */
-       if (pic32mx_info->dev_type == MX_1_2) {
+       switch (pic32mx_info->dev_type) {
+       case    MX_1xx_2xx:
+       case    MX_17x_27x:
                /* 128 byte row */
                pic32mx_flash_write_code[8] = 0x2CD30020;
                pic32mx_flash_write_code[14] = 0x24840080;
                pic32mx_flash_write_code[15] = 0x24A50080;
                pic32mx_flash_write_code[17] = 0x24C6FFE0;
                row_size = 128;
-       } else {
+               break;
+       default:
                /* 512 byte row */
                pic32mx_flash_write_code[8] = 0x2CD30080;
                pic32mx_flash_write_code[14] = 0x24840200;
                pic32mx_flash_write_code[15] = 0x24A50200;
                pic32mx_flash_write_code[17] = 0x24C6FF80;
                row_size = 512;
+               break;
        }
 
-       retval = target_write_buffer(target, write_algorithm->address,
-                       sizeof(pic32mx_flash_write_code), (uint8_t *)pic32mx_flash_write_code);
+       uint8_t code[sizeof(pic32mx_flash_write_code)];
+       target_buffer_set_u32_array(target, code, ARRAY_SIZE(pic32mx_flash_write_code),
+                       pic32mx_flash_write_code);
+       retval = target_write_buffer(target, write_algorithm->address, sizeof(code), code);
        if (retval != ERROR_OK)
                return retval;
 
@@ -470,9 +507,9 @@ static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer,
        mips32_info.common_magic = MIPS32_COMMON_MAGIC;
        mips32_info.isa_mode = MIPS32_ISA_MIPS32;
 
-       init_reg_param(&reg_params[0], "a0", 32, PARAM_IN_OUT);
-       init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
-       init_reg_param(&reg_params[2], "a2", 32, PARAM_OUT);
+       init_reg_param(&reg_params[0], "r4", 32, PARAM_IN_OUT);
+       init_reg_param(&reg_params[1], "r5", 32, PARAM_OUT);
+       init_reg_param(&reg_params[2], "r6", 32, PARAM_OUT);
 
        int row_offset = offset % row_size;
        uint8_t *new_buffer = NULL;
@@ -569,7 +606,7 @@ static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_
        return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
 }
 
-static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int pic32mx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
 {
        uint32_t words_remaining = (count / 4);
        uint32_t bytes_remaining = (count & 0x00000003);
@@ -583,7 +620,7 @@ static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offs
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       LOG_DEBUG("writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32
+       LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
                        " count: 0x%8.8" PRIx32 "", bank->base, offset, count);
 
        if (offset & 0x3) {
@@ -680,17 +717,21 @@ static int pic32mx_probe(struct flash_bank *bank)
        /* Check for PIC32mx1xx/2xx */
        for (i = 0; pic32mx_devs[i].name != NULL; i++) {
                if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
-                       if ((*(pic32mx_devs[i].name) == '1') || (*(pic32mx_devs[i].name) == '2'))
-                               pic32mx_info->dev_type = MX_1_2;
+                       if ((pic32mx_devs[i].name[0] == '1') || (pic32mx_devs[i].name[0] == '2'))
+                               pic32mx_info->dev_type = (pic32mx_devs[i].name[1] == '7') ? MX_17x_27x : MX_1xx_2xx;
                        break;
                }
        }
 
-       if (pic32mx_info->dev_type == MX_1_2)
+       switch (pic32mx_info->dev_type) {
+       case    MX_1xx_2xx:
+       case    MX_17x_27x:
                page_size = 1024;
-       else
+               break;
+       default:
                page_size = 4096;
-
+               break;
+       }
 
        if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
                /* 0x1FC00000: Boot flash size */
@@ -704,20 +745,29 @@ static int pic32mx_probe(struct flash_bank *bank)
                }
 #else
                /* fixed 12k boot bank - see comments above */
-               if (pic32mx_info->dev_type == MX_1_2)
+               switch (pic32mx_info->dev_type) {
+               case    MX_1xx_2xx:
+               case    MX_17x_27x:
                        num_pages = (3 * 1024);
-               else
+                       break;
+               default:
                        num_pages = (12 * 1024);
+                       break;
+               }
 #endif
        } else {
                /* read the flash size from the device */
                if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
-                       if (pic32mx_info->dev_type == MX_1_2) {
+                       switch (pic32mx_info->dev_type) {
+                       case    MX_1xx_2xx:
+                       case    MX_17x_27x:
                                LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
                                num_pages = (32 * 1024);
-                       } else {
+                               break;
+                       default:
                                LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 512k flash");
                                num_pages = (512 * 1024);
+                               break;
                        }
                }
        }
@@ -808,7 +858,7 @@ COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
                return retval;
 
        if (address < bank->base || address >= (bank->base + bank->size)) {
-               command_print(CMD_CTX, "flash address '%s' is out of bounds", CMD_ARGV[0]);
+               command_print(CMD, "flash address '%s' is out of bounds", CMD_ARGV[0]);
                return ERROR_OK;
        }
 
@@ -820,23 +870,22 @@ COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
                res = ERROR_FLASH_OPERATION_FAILED;
 
        if (res == ERROR_OK)
-               command_print(CMD_CTX, "pic32mx pgm word complete");
+               command_print(CMD, "pic32mx pgm word complete");
        else
-               command_print(CMD_CTX, "pic32mx pgm word failed (status = 0x%x)", status);
+               command_print(CMD, "pic32mx pgm word failed (status = 0x%x)", status);
 
        return ERROR_OK;
 }
 
 COMMAND_HANDLER(pic32mx_handle_unlock_command)
 {
-       uint32_t mchip_cmd;
        struct target *target = NULL;
        struct mips_m4k_common *mips_m4k;
        struct mips_ejtag *ejtag_info;
        int timeout = 10;
 
        if (CMD_ARGC < 1) {
-               command_print(CMD_CTX, "pic32mx unlock <bank>");
+               command_print(CMD, "pic32mx unlock <bank>");
                return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
@@ -854,11 +903,11 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
        mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 
        /* first check status of device */
-       mchip_cmd = MCHP_STATUS;
+       uint8_t mchip_cmd = MCHP_STATUS;
        mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
        if (mchip_cmd & (1 << 7)) {
                /* device is not locked */
-               command_print(CMD_CTX, "pic32mx is already unlocked, erasing anyway");
+               command_print(CMD, "pic32mx is already unlocked, erasing anyway");
        }
 
        /* unlock/erase device */
@@ -882,7 +931,7 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
        /* select ejtag tap */
        mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 
-       command_print(CMD_CTX, "pic32mx unlocked.\n"
+       command_print(CMD, "pic32mx unlocked.\n"
                        "INFO: a reset or power cycle is required "
                        "for the new settings to take effect.");
 
@@ -918,7 +967,7 @@ static const struct command_registration pic32mx_command_handlers[] = {
        COMMAND_REGISTRATION_DONE
 };
 
-struct flash_driver pic32mx_flash = {
+const struct flash_driver pic32mx_flash = {
        .name = "pic32mx",
        .commands = pic32mx_command_handlers,
        .flash_bank_command = pic32mx_flash_bank_command,
@@ -931,4 +980,5 @@ struct flash_driver pic32mx_flash = {
        .erase_check = default_flash_blank_check,
        .protect_check = pic32mx_protect_check,
        .info = pic32mx_info,
+       .free_driver_priv = default_flash_free_driver_priv,
 };
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