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flash/nor: implement flash bank deallocation in drivers with simple alloc
[openocd.git] / src / flash / nor / lpcspifi.c
diff --git a/src/flash/nor/lpcspifi.c b/src/flash/nor/lpcspifi.c
index 7566c275f863e3a32209a126fa4cfbf1782f0a31..828c60ca6e0e0bd9ecd8337d7773f625d6e19792 100644 (file)
--- a/src/flash/nor/lpcspifi.c
+++ b/src/flash/nor/lpcspifi.c
@@ -13,9 +13,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -44,6 +42,10 @@
 #define SSP_PROBE_TIMEOUT (100)
 #define SSP_MAX_TIMEOUT  (3000)
 
+/* Size of the stack to alloc in the working area for the execution of
+ * the ROM spifi_init() function */
+#define SPIFI_INIT_STACK_SIZE  512
+
 struct lpcspifi_flash_bank {
        int probed;
        uint32_t ssp_base;
@@ -54,21 +56,6 @@ struct lpcspifi_flash_bank {
        const struct flash_device *dev;
 };
 
-struct lpcspifi_target {
-       char *name;
-       uint32_t tap_idcode;
-       uint32_t spifi_base;
-       uint32_t ssp_base;
-       uint32_t io_base;
-       uint32_t ioconfig_base; /* base address for the port word pin registers */
-};
-
-static const struct lpcspifi_target target_devices[] = {
-       /* name,          tap_idcode, spifi_base, ssp_base,   io_base,    ioconfig_base */
-       { "LPC43xx/18xx", 0x4ba00477, 0x14000000, 0x40083000, 0x400F4000, 0x40086000 },
-       { NULL,           0,          0,          0,          0,          0 }
-};
-
 /* flash_bank lpcspifi <base> <size> <chip_width> <bus_width> <target>
  */
 FLASH_BANK_COMMAND_HANDLER(lpcspifi_flash_bank_command)
@@ -119,7 +106,7 @@ static int ssp_setcs(struct target *target, uint32_t io_base, unsigned int value
  * and the controller is idle. */
 static int poll_ssp_busy(struct target *target, uint32_t ssp_base, int timeout)
 {
-       long long endtime;
+       int64_t endtime;
        uint32_t value;
        int retval;
 
@@ -151,7 +138,7 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
        uint32_t ssp_base = lpcspifi_info->ssp_base;
        struct armv7m_algorithm armv7m_info;
        struct working_area *spifi_init_algorithm;
-       struct reg_param reg_params[1];
+       struct reg_param reg_params[2];
        int retval = ERROR_OK;
 
        LOG_DEBUG("Uninitializing LPC43xx SSP");
@@ -187,19 +174,19 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
 
        LOG_DEBUG("Allocating working area for SPIFI init algorithm");
        /* Get memory for spifi initialization algorithm */
-       retval = target_alloc_working_area(target, sizeof(spifi_init_code),
-               &spifi_init_algorithm);
+       retval = target_alloc_working_area(target, sizeof(spifi_init_code)
+               + SPIFI_INIT_STACK_SIZE, &spifi_init_algorithm);
        if (retval != ERROR_OK) {
                LOG_ERROR("Insufficient working area to initialize SPIFI "\
                        "module. You must allocate at least %zdB of working "\
                        "area in order to use this driver.",
-                       sizeof(spifi_init_code)
+                       sizeof(spifi_init_code) + SPIFI_INIT_STACK_SIZE
                );
 
                return retval;
        }
 
-       LOG_DEBUG("Writing algorithm to working area at 0x%08" PRIx32,
+       LOG_DEBUG("Writing algorithm to working area at 0x%08" TARGET_PRIxADDR,
                spifi_init_algorithm->address);
        /* Write algorithm to working area */
        retval = target_write_buffer(target,
@@ -214,6 +201,8 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
        }
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);            /* spifi clk speed */
+       /* the spifi_init() rom API makes use of the stack */
+       init_reg_param(&reg_params[1], "sp", 32, PARAM_OUT);
 
        /* For now, the algorithm will set up the SPIFI module
         * @ the IRC clock speed. In the future, it could be made
@@ -221,10 +210,13 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
         * already configured them in order to speed up memory-
         * mapped reads. */
        buf_set_u32(reg_params[0].value, 0, 32, 12);
+       /* valid stack pointer */
+       buf_set_u32(reg_params[1].value, 0, 32, (spifi_init_algorithm->address +
+               sizeof(spifi_init_code) + SPIFI_INIT_STACK_SIZE) & ~7UL);
 
        /* Run the algorithm */
        LOG_DEBUG("Running SPIFI init algorithm");
-       retval = target_run_algorithm(target, 0 , NULL, 1, reg_params,
+       retval = target_run_algorithm(target, 0 , NULL, 2, reg_params,
                spifi_init_algorithm->address,
                spifi_init_algorithm->address + sizeof(spifi_init_code) - 2,
                1000, &armv7m_info);
@@ -235,6 +227,7 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
        target_free_working_area(target, spifi_init_algorithm);
 
        destroy_reg_param(&reg_params[0]);
+       destroy_reg_param(&reg_params[1]);
 
        return retval;
 }
@@ -332,7 +325,7 @@ static int wait_till_ready(struct flash_bank *bank, int timeout)
 {
        uint32_t status;
        int retval;
-       long long endtime;
+       int64_t endtime;
 
        endtime = timeval_ms() + timeout;
        do {
@@ -581,7 +574,7 @@ static int lpcspifi_protect(struct flash_bank *bank, int set,
        return ERROR_OK;
 }
 
-static int lpcspifi_write(struct flash_bank *bank, uint8_t *buffer,
+static int lpcspifi_write(struct flash_bank *bank, const uint8_t *buffer,
        uint32_t offset, uint32_t count)
 {
        struct target *target = bank->target;
@@ -678,7 +671,8 @@ static int lpcspifi_write(struct flash_bank *bank, uint8_t *buffer,
                0x00, 0xf0, 0x02, 0xb8, 0x4f, 0xf0, 0x00, 0x08,
                0x4f, 0xf4, 0x80, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
                0xca, 0xf8, 0xab, 0x80, 0x70, 0x47, 0x00, 0x20,
-               0x50, 0x60, 0x30, 0x46, 0x00, 0xbe, 0xff, 0xff
+               0x50, 0x60, 0xff, 0xf7, 0xef, 0xff, 0x30, 0x46,
+               0x00, 0xbe, 0xff, 0xff
        };
 
        if (target_alloc_working_area(target, sizeof(lpcspifi_flash_write_code),
@@ -687,7 +681,7 @@ static int lpcspifi_write(struct flash_bank *bank, uint8_t *buffer,
                        " a working area > %zdB in order to write to SPIFI flash.",
                        sizeof(lpcspifi_flash_write_code));
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-       };
+       }
 
        retval = target_write_buffer(target, write_algorithm->address,
                        sizeof(lpcspifi_flash_write_code),
@@ -723,7 +717,7 @@ static int lpcspifi_write(struct flash_bank *bank, uint8_t *buffer,
        if (target_alloc_working_area(target, fifo_size, &fifo) != ERROR_OK) {
                target_free_working_area(target, write_algorithm);
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-       };
+       }
 
        armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
        armv7m_info.core_mode = ARM_MODE_THREAD;
@@ -841,14 +835,9 @@ static int lpcspifi_read_flash_id(struct flash_bank *bank, uint32_t *id)
 
 static int lpcspifi_probe(struct flash_bank *bank)
 {
-       struct target *target = bank->target;
        struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
-       uint32_t ssp_base;
-       uint32_t io_base;
-       uint32_t ioconfig_base;
        struct flash_sector *sectors;
        uint32_t id = 0; /* silence uninitialized warning */
-       const struct lpcspifi_target *target_device;
        int retval;
 
        /* If we've already probed, we should be fine to skip this time. */
@@ -856,26 +845,11 @@ static int lpcspifi_probe(struct flash_bank *bank)
                return ERROR_OK;
        lpcspifi_info->probed = 0;
 
-       for (target_device = target_devices ; target_device->name ; ++target_device)
-               if (target_device->tap_idcode == target->tap->idcode)
-                       break;
-       if (!target_device->name) {
-               LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SPIFI capable",
-                               target->tap->idcode);
-               return ERROR_FAIL;
-       }
-
-       ssp_base = target_device->ssp_base;
-       io_base = target_device->io_base;
-       ioconfig_base = target_device->ioconfig_base;
-       lpcspifi_info->ssp_base = ssp_base;
-       lpcspifi_info->io_base = io_base;
-       lpcspifi_info->ioconfig_base = ioconfig_base;
+       lpcspifi_info->ssp_base = 0x40083000;
+       lpcspifi_info->io_base = 0x400F4000;
+       lpcspifi_info->ioconfig_base = 0x40086000;
        lpcspifi_info->bank_num = bank->bank_number;
 
-       LOG_DEBUG("Valid SPIFI on device %s at address 0x%" PRIx32,
-               target_device->name, bank->base);
-
        /* read and decode flash ID; returns in SW mode */
        retval = lpcspifi_read_flash_id(bank, &id);
        if (retval != ERROR_OK)
@@ -968,4 +942,5 @@ struct flash_driver lpcspifi_flash = {
        .erase_check = default_flash_blank_check,
        .protect_check = lpcspifi_protect_check,
        .info = get_lpcspifi_info,
+       .free_driver_priv = default_flash_free_driver_priv,
 };
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