tcl/target/ti_dm365.cfg

   1 #
   2 # Texas Instruments DaVinci family:  TMS320DM365
   3 #
   4 if { [info exists CHIPNAME] } {
   5    set  _CHIPNAME $CHIPNAME
   6 } else {
   7    set  _CHIPNAME dm365
   8 }
   9
  10 #
  11 # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
  12 # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
  13 #
  14 # Also note:  when running without RTCK before the PLLs are set up, you
  15 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
  16 #
  17 source [find target/icepick.cfg]
  18 set EMU01 "-enable"
  19 #set EMU01 "-disable"
  20
  21 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  22 if { [info exists ETB_TAPID ] } {
  23    set _ETB_TAPID $ETB_TAPID
  24 } else {
  25    set _ETB_TAPID 0x2b900f0f
  26 }
  27 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
  28 jtag configure $_CHIPNAME.etb -event tap-enable \
  29         "icepick_c_tapenable $_CHIPNAME.jrc 1"
  30
  31 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  32 if { [info exists CPU_TAPID ] } {
  33    set _CPU_TAPID $CPU_TAPID
  34 } else {
  35    set _CPU_TAPID 0x0792602f
  36 }
  37 jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
  38 jtag configure $_CHIPNAME.arm -event tap-enable \
  39         "icepick_c_tapenable $_CHIPNAME.jrc 0"
  40
  41 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
  42 if { [info exists JRC_TAPID ] } {
  43    set _JRC_TAPID $JRC_TAPID
  44 } else {
  45    set _JRC_TAPID 0x0b83e02f
  46 }
  47 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
  48
  49 ################
  50
  51 # various symbol definitions, to avoid hard-wiring addresses
  52 # and enable some sharing of DaVinci-family utility code
  53 global dm365
  54 set dm365 [ dict create ]
  55
  56 # Physical addresses for controllers and memory
  57 # (Some of these are valid for many DaVinci family chips)
  58 dict set dm365 sram0            0x00010000
  59 dict set dm365 sram1            0x00014000
  60 dict set dm365 sysbase          0x01c40000
  61 dict set dm365 pllc1            0x01c40800
  62 dict set dm365 pllc2            0x01c40c00
  63 dict set dm365 psc              0x01c41000
  64 dict set dm365 gpio             0x01c67000
  65 dict set dm365 a_emif           0x01d10000
  66 dict set dm365 a_emif_cs0       0x02000000
  67 dict set dm365 a_emif_cs1       0x04000000
  68 dict set dm365 ddr_emif         0x20000000
  69 dict set dm365 ddr              0x80000000
  70
  71 source [find target/davinci.cfg]
  72
  73 ################
  74 # GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
  75 # and the ETB memory (4K) are other options, while trace is unused.
  76 set _TARGETNAME $_CHIPNAME.arm
  77
  78 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  79
  80 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
  81 # and that the work area is used only with a kernel mmu context ...
  82 $_TARGETNAME configure \
  83         -work-area-virt [expr 0xfffe0000 + 0x4000] \
  84         -work-area-phys [dict get $dm365 sram1] \
  85         -work-area-size 0x4000 \
  86         -work-area-backup 0
  87
  88 # be absolutely certain the JTAG clock will work with the worst-case
  89 # CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
  90 # on the PLL and starts using it.  OK to speed up after clock setup.
  91 jtag_rclk 1500
  92 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
  93
  94 arm7_9 fast_memory_access enable
  95 arm7_9 dcc_downloads enable
  96
  97 # trace setup
  98 etm config $_TARGETNAME 16 normal full etb
  99 etb config $_TARGETNAME $_CHIPNAME.etb