1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # script for stm32g4x family
6 # stm32g4 devices support both JTAG and SWD transports.
8 source [find target/swj-dp.tcl]
9 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME stm32g4x
19 # Work-area is a space in RAM used for flash programming
20 # Smallest current target has 32kB ram, use 16kB by default to avoid surprises
21 if { [info exists WORKAREASIZE] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x4000
28 if { [info exists CPUTAPID] } {
29 set _CPUTAPID $CPUTAPID
32 # See STM Document RM0440
33 # Section 46.6.3 - corresponds to Cortex-M4 r0p1
34 set _CPUTAPID 0x4ba00477
36 set _CPUTAPID 0x2ba01477
40 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
41 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
44 jtag newtap $_CHIPNAME bs -irlen 5
47 set _TARGETNAME $_CHIPNAME.cpu
48 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
50 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
52 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
53 flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
55 if { [info exists QUADSPI] && $QUADSPI } {
56 set a [llength [flash list]]
57 set _QSPINAME $_CHIPNAME.qspi
58 flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
64 adapter srst delay 100
69 reset_config srst_nogate
72 # if srst is not fitted use SYSRESETREQ to
73 # perform a soft reset
74 cortex_m reset_config sysresetreq
77 $_TARGETNAME configure -event reset-init {
78 # CPU comes out of reset with HSION | HSIRDY.
79 # Use HSI 16 MHz clock, compliant even with VOS == 2.
80 # 1 WS compliant with VOS == 2 and 16 MHz.
81 mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1
82 mmw 0x40021000 0x00000100 0x00000000 ;# RCC_CR |= HSION
83 mmw 0x40021008 0x00000001 0x00000002 ;# RCC_CFGR: SW=HSI16
86 $_TARGETNAME configure -event reset-start {
87 # Reset clock is HSI (16 MHz)
91 $_TARGETNAME configure -event examine-end {
92 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
93 mmw 0xE0042004 0x00000007 0
95 # Stop watchdog counters during halt
96 # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
97 mmw 0xE0042008 0x00001800 0
100 $_TARGETNAME configure -event trace-config {
101 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
102 # change this value accordingly to configure trace pins
104 mmw 0xE0042004 0x00000020 0
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