47d22e0ac0cc1a838072bd34ff71ddf5fd3e34ec
[openocd.git] / tcl / chip / atmel / at91 / at91sam9_init.cfg
1 uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
2 uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
3 uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
4 uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]
5 uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]
6
7 proc at91sam9_reset_start { } {
8
9 arm7_9 fast_memory_access disable
10
11 jtag_rclk 8
12 halt
13 wait_halt 10000
14 set rstc_mr_val [expr $::AT91_RSTC_KEY]
15 set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))]
16 set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
17 mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
18 }
19
20 proc at91sam9_reset_init { config } {
21
22 mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog
23
24 set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))]
25
26 mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
27 while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
28
29 set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
30 set pllar_val [expr ($pllar_val | $::AT91_PMC_OUT)]
31 set pllar_val [expr ($pllar_val | $::AT91_PMC_PLLCOUNT)]
32 set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
33 set pllar_val [expr ($pllar_val | $config(master_pll_div))]
34
35 mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
36 while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
37
38 ;# PCK/2 = MCK Master Clock from PLLA
39 set mckr_val [expr $::AT91_PMC_CSS_PLLA]
40 set mckr_val [expr ($mckr_val | $::AT91_PMC_PRES_1)]
41 set mckr_val [expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)]
42 set mckr_val [expr ($mckr_val | $::AT91_PMC_PDIV_1)]
43
44 mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
45 while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
46
47 ## switch JTAG clock to highseepd clock
48 jtag_rclk 0
49
50 arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
51 arm7_9 fast_memory_access enable
52
53 set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
54 set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
55 mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable
56
57 set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
58 mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
59 set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
60 mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
61
62 mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
63 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRAMC_MR Mode register
64 mww $::AT91_SDRAMC_TR $config(sdram_tr_val) ;# SDRAMC_TR - Refresh Timer register
65 mww $::AT91_SDRAMC_CR $config(sdram_cr_val) ;# SDRAMC_CR - Configuration register
66 mww $::AT91_SDRAMC_MDR $::AT91_SDRAMC_MD_SDRAM ;# Memory Device Register -> SDRAM
67 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_PRECHARGE ;# SDRAMC_MR
68 mww $config(sdram_base) 0 ;# SDRAM_BASE
69 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_REFRESH ;# SDRC_MR
70 mww $config(sdram_base) 0 ;# SDRAM_BASE
71 mww $config(sdram_base) 0 ;# SDRAM_BASE
72 mww $config(sdram_base) 0 ;# SDRAM_BASE
73 mww $config(sdram_base) 0 ;# SDRAM_BASE
74 mww $config(sdram_base) 0 ;# SDRAM_BASE
75 mww $config(sdram_base) 0 ;# SDRAM_BASE
76 mww $config(sdram_base) 0 ;# SDRAM_BASE
77 mww $config(sdram_base) 0 ;# SDRAM_BASE
78 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_LMR ;# SDRC_MR
79 mww $config(sdram_base) 0 ;# SDRAM_BASE
80 mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRC_MR
81 mww $config(sdram_base) 0 ;# SDRAM_BASE
82 mww $::AT91_SDRAMC_TR 1200 ;# SDRAM_TR
83 mww $config(sdram_base) 0 ;# SDRAM_BASE
84
85 mww $::AT91_MATRIX 0xf ;# MATRIX_MCFG - REMAP all masters
86 }

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