tcl/board/imx27ads.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # The IMX27 ADS eval board has a single IMX27 chip
   4 # Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
   5 source [find target/imx27.cfg]
   6 $_TARGETNAME configure -event gdb-attach { reset init }
   7 $_TARGETNAME configure -event reset-init { imx27ads_init }
   8
   9 # The IMX27 ADS board has a NOR flash on CS0
  10 set _FLASHNAME $_CHIPNAME.flash
  11 flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
  12
  13 proc imx27ads_init { } {
  14         # This setup puts RAM at 0xA0000000
  15
  16         # reset the board correctly
  17         reset run
  18         reset halt
  19
  20         mww 0x10000000 0x20040304
  21         mww 0x10020000 0x00000000
  22         mww 0x10000004 0xDFFBFCFB
  23         mww 0x10020004 0xFFFFFFFF
  24
  25         sleep 100
  26
  27         # ========================================
  28         #  Configure DDR on CSD0 -- initial reset
  29         # ========================================
  30         mww 0xD8001010 0x00000008
  31
  32         # ========================================
  33         #  Configure PSRAM on CS5
  34         # ========================================
  35         mww 0xd8002050 0x0000dcf6
  36         mww 0xd8002054 0x444a4541
  37         mww 0xd8002058 0x44443302
  38
  39         #  ========================================
  40         #         Configure16 bit NorFlash on CS0
  41         #  ========================================
  42         mww 0xd8002000 0x0000CC03
  43         mww 0xd8002004 0xa0330D01
  44         mww 0xd8002008 0x00220800
  45
  46         # ========================================
  47         #  Configure CPLD on CS4
  48         # ========================================
  49         mww 0xd8002040 0x0000DCF6
  50         mww 0xd8002044 0x444A4541
  51         mww 0xd8002048 0x44443302
  52
  53         # ========================================
  54         #  Configure DDR on CSD0 -- wait 5000 cycle
  55         # ========================================
  56         mww 0x10027828 0x55555555
  57         mww 0x10027830 0x55555555
  58         mww 0x10027834 0x55555555
  59         mww 0x10027838 0x00005005
  60         mww 0x1002783C 0x15555555
  61
  62         mww 0xD8001010 0x00000004
  63
  64         mww 0xD8001004 0x00795729
  65
  66         mww 0xD8001000 0x92200000
  67         mww 0xA0000F00 0x0
  68
  69         mww 0xD8001000 0xA2200000
  70         mww 0xA0000F00 0x0
  71         mww 0xA0000F00 0x0
  72
  73         mww 0xD8001000 0xB2200000
  74         mwb 0xA0000033 0xFF
  75         mwb 0xA1000000 0xAA
  76
  77         mww 0xD8001000 0x82228085
  78 }