tcl/board/digi_connectcore_wi-9c.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 ######################################
   4 # Target: DIGI ConnectCore Wi-9C
   5 ######################################
   6
   7 reset_config trst_and_srst
   8
   9 # FIXME use some standard target config, maybe create one from this
  10 #
  11 #       source [find target/...cfg]
  12
  13 if { [info exists CHIPNAME] } {
  14    set  _CHIPNAME $CHIPNAME
  15 } else {
  16    set  _CHIPNAME ns9360
  17 }
  18
  19 if { [info exists ENDIAN] } {
  20    set  _ENDIAN $ENDIAN
  21 } else {
  22   # This config file was defaulting to big endian..
  23    set  _ENDIAN big
  24 }
  25
  26
  27 # What's a good fallback frequency for this board if RCLK is
  28 # not available??
  29 jtag_rclk 1000
  30
  31
  32 if { [info exists CPUTAPID] } {
  33    set _CPUTAPID $CPUTAPID
  34 } else {
  35    set _CPUTAPID 0x07926031
  36 }
  37
  38 set _TARGETNAME $_CHIPNAME.cpu
  39 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  40
  41 adapter srst delay 200
  42 jtag_ntrst_delay 0
  43
  44
  45 ######################
  46 # Target configuration
  47 ######################
  48
  49 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
  50
  51 $_TARGETNAME configure -event reset-init {
  52         mww 0x90600104 0x33313333
  53         mww 0xA0700000 0x00000001  ;# Enable the memory controller.
  54         mww 0xA0700024 0x00000006  ;# Set the refresh counter 6
  55         mww 0xA0700028 0x00000001  ;#
  56         mww 0xA0700030 0x00000001  ;# Set the precharge period
  57         mww 0xA0700034 0x00000004  ;# Active to precharge command period is 16 clock cycles
  58         mww 0xA070003C 0x00000001  ;# tAPR
  59         mww 0xA0700040 0x00000005  ;# tDAL
  60         mww 0xA0700044 0x00000001  ;# tWR
  61         mww 0xA0700048 0x00000006  ;# tRC 32 clock cycles
  62         mww 0xA070004C 0x00000006  ;# tRFC 32 clock cycles
  63         mww 0xA0700054 0x00000001  ;# tRRD
  64         mww 0xA0700058 0x00000001  ;# tMRD
  65         mww 0xA0700100 0x00004280  ;# Dynamic Config 0 (cs4)
  66         mww 0xA0700120 0x00004280  ;# Dynamic Config 1 (cs5)
  67         mww 0xA0700140 0x00004280  ;# Dynamic Config 2 (cs6)
  68         mww 0xA0700160 0x00004280  ;# Dynamic Config 3 (cs7)
  69         #
  70         mww 0xA0700104 0x00000203  ;# CAS latency is 2 at 100 MHz
  71         mww 0xA0700124 0x00000203  ;# CAS latency is 2 at 100 MHz
  72         mww 0xA0700144 0x00000203  ;# CAS latency is 2 at 100 MHz
  73         mww 0xA0700164 0x00000203  ;# CAS latency is 2 at 100 MHz
  74         #
  75         mww 0xA0700020 0x00000103  ;# issue SDRAM PALL command
  76         #
  77         mww 0xA0700024 0x00000001  ;# Set the refresh counter to be as small as possible
  78         #
  79         # Add some dummy writes to give the SDRAM time to settle, it needs two
  80         # AHB clock cycles, here we poke in the debugger flag, this lets
  81         # the software know that we are in the debugger
  82         mww 0xA0900000 0x00000002
  83         mww 0xA0900000 0x00000002
  84         mww 0xA0900000 0x00000002
  85         mww 0xA0900000 0x00000002
  86         mww 0xA0900000 0x00000002
  87         #
  88         mdw 0xA0900000
  89         mdw 0xA0900000
  90         mdw 0xA0900000
  91         mdw 0xA0900000
  92         mdw 0xA0900000
  93         #
  94         mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
  95         mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
  96         #
  97         # Next we perform a read of RAM.
  98         # mw = move word.
  99         mdw 0x00022000
 100         # mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
 101         #
 102         mww 0xA0700020 0x00000003   ;# issue SDRAM NORMAL command
 103         mww 0xA0700100 0x00084280   ;# Enable buffer access
 104         mww 0xA0700120 0x00084280   ;# Enable buffer access
 105         mww 0xA0700140 0x00084280   ;# Enable buffer access
 106         mww 0xA0700160 0x00084280   ;# Enable buffer access
 107
 108         #Set byte lane state (static mem 1)"
 109         mww 0xA0700220 0x00000082
 110         #Flash Start
 111         mww 0xA09001F8 0x50000000
 112         #Flash Mask Reg
 113         mww 0xA09001FC 0xFF000001
 114         mww 0xA0700028 0x00000001
 115
 116         #  RAMAddr = 0x00020000
 117         #  RAMSize = 0x00004000
 118
 119         # Set the processor mode
 120         reg cpsr 0xd3
 121 }
 122
 123 $_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
 124
 125 #####################
 126 # Flash configuration
 127 #####################
 128
 129 #M29DW323DB - not working
 130 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 131 set _FLASHNAME $_CHIPNAME.flash
 132 flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME