1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "replacements.h"
31 #include "arm7_9_common.h"
35 #include "arm_simulator.h"
36 #include "arm_disassembler.h"
39 #include "binarybuffer.h"
40 #include "time_support.h"
41 #include "breakpoints.h"
47 #include <sys/types.h>
53 int xscale_register_commands(struct command_context_s
*cmd_ctx
);
55 /* forward declarations */
56 int xscale_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
57 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
58 int xscale_quit(void);
60 int xscale_arch_state(struct target_s
*target
);
61 int xscale_poll(target_t
*target
);
62 int xscale_halt(target_t
*target
);
63 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
64 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
65 int xscale_debug_entry(target_t
*target
);
66 int xscale_restore_context(target_t
*target
);
68 int xscale_assert_reset(target_t
*target
);
69 int xscale_deassert_reset(target_t
*target
);
70 int xscale_soft_reset_halt(struct target_s
*target
);
72 int xscale_set_reg_u32(reg_t
*reg
, u32 value
);
74 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
);
75 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
);
77 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
78 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
79 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
);
81 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
82 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
83 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
84 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
);
85 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
86 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
);
87 void xscale_enable_watchpoints(struct target_s
*target
);
88 void xscale_enable_breakpoints(struct target_s
*target
);
89 static int xscale_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
);
90 static int xscale_mmu(struct target_s
*target
, int *enabled
);
92 int xscale_read_trace(target_t
*target
);
94 target_type_t xscale_target
=
99 .arch_state
= xscale_arch_state
,
101 .target_request_data
= NULL
,
104 .resume
= xscale_resume
,
107 .assert_reset
= xscale_assert_reset
,
108 .deassert_reset
= xscale_deassert_reset
,
109 .soft_reset_halt
= xscale_soft_reset_halt
,
111 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
113 .read_memory
= xscale_read_memory
,
114 .write_memory
= xscale_write_memory
,
115 .bulk_write_memory
= xscale_bulk_write_memory
,
116 .checksum_memory
= arm7_9_checksum_memory
,
117 .blank_check_memory
= arm7_9_blank_check_memory
,
119 .run_algorithm
= armv4_5_run_algorithm
,
121 .add_breakpoint
= xscale_add_breakpoint
,
122 .remove_breakpoint
= xscale_remove_breakpoint
,
123 .add_watchpoint
= xscale_add_watchpoint
,
124 .remove_watchpoint
= xscale_remove_watchpoint
,
126 .register_commands
= xscale_register_commands
,
127 .target_command
= xscale_target_command
,
128 .init_target
= xscale_init_target
,
131 .virt2phys
= xscale_virt2phys
,
135 char* xscale_reg_list
[] =
137 "XSCALE_MAINID", /* 0 */
147 "XSCALE_IBCR0", /* 10 */
157 "XSCALE_RX", /* 20 */
161 xscale_reg_t xscale_reg_arch_info
[] =
163 {XSCALE_MAINID
, NULL
},
164 {XSCALE_CACHETYPE
, NULL
},
166 {XSCALE_AUXCTRL
, NULL
},
172 {XSCALE_CPACCESS
, NULL
},
173 {XSCALE_IBCR0
, NULL
},
174 {XSCALE_IBCR1
, NULL
},
177 {XSCALE_DBCON
, NULL
},
178 {XSCALE_TBREG
, NULL
},
179 {XSCALE_CHKPT0
, NULL
},
180 {XSCALE_CHKPT1
, NULL
},
181 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
182 {-1, NULL
}, /* TX accessed via JTAG */
183 {-1, NULL
}, /* RX accessed via JTAG */
184 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
187 int xscale_reg_arch_type
= -1;
189 int xscale_get_reg(reg_t
*reg
);
190 int xscale_set_reg(reg_t
*reg
, u8
*buf
);
192 int xscale_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, xscale_common_t
**xscale_p
)
194 armv4_5_common_t
*armv4_5
= target
->arch_info
;
195 xscale_common_t
*xscale
= armv4_5
->arch_info
;
197 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
199 LOG_ERROR("target isn't an XScale target");
203 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
)
205 LOG_ERROR("target isn't an XScale target");
209 *armv4_5_p
= armv4_5
;
215 int xscale_jtag_set_instr(int chain_pos
, u32 new_instr
)
217 jtag_device_t
*device
= jtag_get_device(chain_pos
);
219 if (buf_get_u32(device
->cur_instr
, 0, device
->ir_length
) != new_instr
)
223 field
.device
= chain_pos
;
224 field
.num_bits
= device
->ir_length
;
225 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
226 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
227 field
.out_mask
= NULL
;
228 field
.in_value
= NULL
;
229 jtag_set_check_value(&field
, device
->expected
, device
->expected_mask
, NULL
);
231 jtag_add_ir_scan(1, &field
, -1);
233 free(field
.out_value
);
239 int xscale_read_dcsr(target_t
*target
)
241 armv4_5_common_t
*armv4_5
= target
->arch_info
;
242 xscale_common_t
*xscale
= armv4_5
->arch_info
;
246 scan_field_t fields
[3];
248 u8 field0_check_value
= 0x2;
249 u8 field0_check_mask
= 0x7;
251 u8 field2_check_value
= 0x0;
252 u8 field2_check_mask
= 0x1;
254 jtag_add_end_state(TAP_PD
);
255 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
257 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
258 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
260 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
261 fields
[0].num_bits
= 3;
262 fields
[0].out_value
= &field0
;
263 fields
[0].out_mask
= NULL
;
264 fields
[0].in_value
= NULL
;
265 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
267 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
268 fields
[1].num_bits
= 32;
269 fields
[1].out_value
= NULL
;
270 fields
[1].out_mask
= NULL
;
271 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
272 fields
[1].in_handler
= NULL
;
273 fields
[1].in_handler_priv
= NULL
;
274 fields
[1].in_check_value
= NULL
;
275 fields
[1].in_check_mask
= NULL
;
277 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
278 fields
[2].num_bits
= 1;
279 fields
[2].out_value
= &field2
;
280 fields
[2].out_mask
= NULL
;
281 fields
[2].in_value
= NULL
;
282 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
284 jtag_add_dr_scan(3, fields
, -1);
286 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
288 LOG_ERROR("JTAG error while reading DCSR");
292 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
293 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
295 /* write the register with the value we just read
296 * on this second pass, only the first bit of field0 is guaranteed to be 0)
298 field0_check_mask
= 0x1;
299 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
300 fields
[1].in_value
= NULL
;
302 jtag_add_end_state(TAP_RTI
);
304 jtag_add_dr_scan(3, fields
, -1);
306 /* DANGER!!! this must be here. It will make sure that the arguments
307 * to jtag_set_check_value() does not go out of scope! */
308 return jtag_execute_queue();
311 int xscale_receive(target_t
*target
, u32
*buffer
, int num_words
)
314 return ERROR_INVALID_ARGUMENTS
;
317 armv4_5_common_t
*armv4_5
= target
->arch_info
;
318 xscale_common_t
*xscale
= armv4_5
->arch_info
;
320 enum tap_state path
[3];
321 scan_field_t fields
[3];
323 u8
*field0
= malloc(num_words
* 1);
324 u8 field0_check_value
= 0x2;
325 u8 field0_check_mask
= 0x6;
326 u32
*field1
= malloc(num_words
* 4);
327 u8 field2_check_value
= 0x0;
328 u8 field2_check_mask
= 0x1;
330 int words_scheduled
= 0;
338 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
339 fields
[0].num_bits
= 3;
340 fields
[0].out_value
= NULL
;
341 fields
[0].out_mask
= NULL
;
342 fields
[0].in_value
= NULL
;
343 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
345 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
346 fields
[1].num_bits
= 32;
347 fields
[1].out_value
= NULL
;
348 fields
[1].out_mask
= NULL
;
349 fields
[1].in_value
= NULL
;
350 fields
[1].in_handler
= NULL
;
351 fields
[1].in_handler_priv
= NULL
;
352 fields
[1].in_check_value
= NULL
;
353 fields
[1].in_check_mask
= NULL
;
357 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
358 fields
[2].num_bits
= 1;
359 fields
[2].out_value
= NULL
;
360 fields
[2].out_mask
= NULL
;
361 fields
[2].in_value
= NULL
;
362 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
364 jtag_add_end_state(TAP_RTI
);
365 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgtx
);
366 jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
368 /* repeat until all words have been collected */
370 while (words_done
< num_words
)
374 for (i
= words_done
; i
< num_words
; i
++)
376 fields
[0].in_value
= &field0
[i
];
377 fields
[1].in_handler
= buf_to_u32_handler
;
378 fields
[1].in_handler_priv
= (u8
*)&field1
[i
];
380 jtag_add_pathmove(3, path
);
381 jtag_add_dr_scan(3, fields
, TAP_RTI
);
385 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
387 LOG_ERROR("JTAG error while receiving data from debug handler");
391 /* examine results */
392 for (i
= words_done
; i
< num_words
; i
++)
394 if (!(field0
[0] & 1))
396 /* move backwards if necessary */
398 for (j
= i
; j
< num_words
- 1; j
++)
400 field0
[j
] = field0
[j
+1];
401 field1
[j
] = field1
[j
+1];
406 if (words_scheduled
==0)
408 if (attempts
++==1000)
410 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
411 retval
=ERROR_TARGET_TIMEOUT
;
416 words_done
+= words_scheduled
;
419 for (i
= 0; i
< num_words
; i
++)
420 *(buffer
++) = buf_get_u32((u8
*)&field1
[i
], 0, 32);
427 int xscale_read_tx(target_t
*target
, int consume
)
429 armv4_5_common_t
*armv4_5
= target
->arch_info
;
430 xscale_common_t
*xscale
= armv4_5
->arch_info
;
431 enum tap_state path
[3];
432 enum tap_state noconsume_path
[6];
435 struct timeval timeout
, now
;
437 scan_field_t fields
[3];
439 u8 field0_check_value
= 0x2;
440 u8 field0_check_mask
= 0x6;
441 u8 field2_check_value
= 0x0;
442 u8 field2_check_mask
= 0x1;
444 jtag_add_end_state(TAP_RTI
);
446 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgtx
);
452 noconsume_path
[0] = TAP_SDS
;
453 noconsume_path
[1] = TAP_CD
;
454 noconsume_path
[2] = TAP_E1D
;
455 noconsume_path
[3] = TAP_PD
;
456 noconsume_path
[4] = TAP_E2D
;
457 noconsume_path
[5] = TAP_SD
;
459 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
460 fields
[0].num_bits
= 3;
461 fields
[0].out_value
= NULL
;
462 fields
[0].out_mask
= NULL
;
463 fields
[0].in_value
= &field0_in
;
464 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
466 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
467 fields
[1].num_bits
= 32;
468 fields
[1].out_value
= NULL
;
469 fields
[1].out_mask
= NULL
;
470 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
471 fields
[1].in_handler
= NULL
;
472 fields
[1].in_handler_priv
= NULL
;
473 fields
[1].in_check_value
= NULL
;
474 fields
[1].in_check_mask
= NULL
;
478 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
479 fields
[2].num_bits
= 1;
480 fields
[2].out_value
= NULL
;
481 fields
[2].out_mask
= NULL
;
482 fields
[2].in_value
= NULL
;
483 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
485 gettimeofday(&timeout
, NULL
);
486 timeval_add_time(&timeout
, 1, 0);
491 for (i
=0; i
<100; i
++)
493 /* if we want to consume the register content (i.e. clear TX_READY),
494 * we have to go straight from Capture-DR to Shift-DR
495 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
498 jtag_add_pathmove(3, path
);
501 jtag_add_pathmove(sizeof(noconsume_path
)/sizeof(*noconsume_path
), noconsume_path
);
504 jtag_add_dr_scan(3, fields
, TAP_RTI
);
506 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
508 LOG_ERROR("JTAG error while reading TX");
509 return ERROR_TARGET_TIMEOUT
;
512 gettimeofday(&now
, NULL
);
513 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
515 LOG_ERROR("time out reading TX register");
516 return ERROR_TARGET_TIMEOUT
;
518 if (!((!(field0_in
& 1)) && consume
))
523 LOG_DEBUG("waiting 10ms");
524 usleep(10*1000); /* avoid flooding the logs */
528 if (!(field0_in
& 1))
529 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
534 int xscale_write_rx(target_t
*target
)
536 armv4_5_common_t
*armv4_5
= target
->arch_info
;
537 xscale_common_t
*xscale
= armv4_5
->arch_info
;
540 struct timeval timeout
, now
;
542 scan_field_t fields
[3];
545 u8 field0_check_value
= 0x2;
546 u8 field0_check_mask
= 0x6;
548 u8 field2_check_value
= 0x0;
549 u8 field2_check_mask
= 0x1;
551 jtag_add_end_state(TAP_RTI
);
553 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgrx
);
555 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
556 fields
[0].num_bits
= 3;
557 fields
[0].out_value
= &field0_out
;
558 fields
[0].out_mask
= NULL
;
559 fields
[0].in_value
= &field0_in
;
560 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
562 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
563 fields
[1].num_bits
= 32;
564 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
565 fields
[1].out_mask
= NULL
;
566 fields
[1].in_value
= NULL
;
567 fields
[1].in_handler
= NULL
;
568 fields
[1].in_handler_priv
= NULL
;
569 fields
[1].in_check_value
= NULL
;
570 fields
[1].in_check_mask
= NULL
;
574 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
575 fields
[2].num_bits
= 1;
576 fields
[2].out_value
= &field2
;
577 fields
[2].out_mask
= NULL
;
578 fields
[2].in_value
= NULL
;
579 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
581 gettimeofday(&timeout
, NULL
);
582 timeval_add_time(&timeout
, 1, 0);
584 /* poll until rx_read is low */
585 LOG_DEBUG("polling RX");
589 for (i
=0; i
<100; i
++)
591 jtag_add_dr_scan(3, fields
, TAP_RTI
);
593 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
595 LOG_ERROR("JTAG error while writing RX");
599 gettimeofday(&now
, NULL
);
600 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
602 LOG_ERROR("time out writing RX register");
603 return ERROR_TARGET_TIMEOUT
;
605 if (!(field0_in
& 1))
608 LOG_DEBUG("waiting 10ms");
609 usleep(10*1000); /* wait 10ms to avoid flooding the logs */
615 jtag_add_dr_scan(3, fields
, TAP_RTI
);
617 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
619 LOG_ERROR("JTAG error while writing RX");
626 /* send count elements of size byte to the debug handler */
627 int xscale_send(target_t
*target
, u8
*buffer
, int count
, int size
)
629 armv4_5_common_t
*armv4_5
= target
->arch_info
;
630 xscale_common_t
*xscale
= armv4_5
->arch_info
;
638 jtag_add_end_state(TAP_RTI
);
640 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dbgrx
);
647 int endianness
= target
->endianness
;
648 while (done_count
++ < count
)
653 if (endianness
== TARGET_LITTLE_ENDIAN
)
655 t
[1]=le_to_h_u32(buffer
);
658 t
[1]=be_to_h_u32(buffer
);
662 if (endianness
== TARGET_LITTLE_ENDIAN
)
664 t
[1]=le_to_h_u16(buffer
);
667 t
[1]=be_to_h_u16(buffer
);
674 LOG_ERROR("BUG: size neither 4, 2 nor 1");
677 jtag_add_dr_out(xscale
->jtag_info
.chain_pos
,
685 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
687 LOG_ERROR("JTAG error while sending data to debug handler");
694 int xscale_send_u32(target_t
*target
, u32 value
)
696 armv4_5_common_t
*armv4_5
= target
->arch_info
;
697 xscale_common_t
*xscale
= armv4_5
->arch_info
;
699 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
700 return xscale_write_rx(target
);
703 int xscale_write_dcsr(target_t
*target
, int hold_rst
, int ext_dbg_brk
)
705 armv4_5_common_t
*armv4_5
= target
->arch_info
;
706 xscale_common_t
*xscale
= armv4_5
->arch_info
;
710 scan_field_t fields
[3];
712 u8 field0_check_value
= 0x2;
713 u8 field0_check_mask
= 0x7;
715 u8 field2_check_value
= 0x0;
716 u8 field2_check_mask
= 0x1;
719 xscale
->hold_rst
= hold_rst
;
721 if (ext_dbg_brk
!= -1)
722 xscale
->external_debug_break
= ext_dbg_brk
;
724 jtag_add_end_state(TAP_RTI
);
725 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
727 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
728 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
730 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
731 fields
[0].num_bits
= 3;
732 fields
[0].out_value
= &field0
;
733 fields
[0].out_mask
= NULL
;
734 fields
[0].in_value
= NULL
;
735 jtag_set_check_value(fields
+0, &field0_check_value
, &field0_check_mask
, NULL
);
737 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
738 fields
[1].num_bits
= 32;
739 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
740 fields
[1].out_mask
= NULL
;
741 fields
[1].in_value
= NULL
;
742 fields
[1].in_handler
= NULL
;
743 fields
[1].in_handler_priv
= NULL
;
744 fields
[1].in_check_value
= NULL
;
745 fields
[1].in_check_mask
= NULL
;
749 fields
[2].device
= xscale
->jtag_info
.chain_pos
;
750 fields
[2].num_bits
= 1;
751 fields
[2].out_value
= &field2
;
752 fields
[2].out_mask
= NULL
;
753 fields
[2].in_value
= NULL
;
754 jtag_set_check_value(fields
+2, &field2_check_value
, &field2_check_mask
, NULL
);
756 jtag_add_dr_scan(3, fields
, -1);
758 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
760 LOG_ERROR("JTAG error while writing DCSR");
764 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
765 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
770 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
771 unsigned int parity (unsigned int v
)
778 LOG_DEBUG("parity of 0x%x is %i", ov
, (0x6996 >> v
) & 1);
779 return (0x6996 >> v
) & 1;
782 int xscale_load_ic(target_t
*target
, int mini
, u32 va
, u32 buffer
[8])
784 armv4_5_common_t
*armv4_5
= target
->arch_info
;
785 xscale_common_t
*xscale
= armv4_5
->arch_info
;
790 scan_field_t fields
[2];
792 LOG_DEBUG("loading miniIC at 0x%8.8x", va
);
794 jtag_add_end_state(TAP_RTI
);
795 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.ldic
); /* LDIC */
797 /* CMD is b010 for Main IC and b011 for Mini IC */
799 buf_set_u32(&cmd
, 0, 3, 0x3);
801 buf_set_u32(&cmd
, 0, 3, 0x2);
803 buf_set_u32(&cmd
, 3, 3, 0x0);
805 /* virtual address of desired cache line */
806 buf_set_u32(packet
, 0, 27, va
>> 5);
808 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
809 fields
[0].num_bits
= 6;
810 fields
[0].out_value
= &cmd
;
811 fields
[0].out_mask
= NULL
;
812 fields
[0].in_value
= NULL
;
813 fields
[0].in_check_value
= NULL
;
814 fields
[0].in_check_mask
= NULL
;
815 fields
[0].in_handler
= NULL
;
816 fields
[0].in_handler_priv
= NULL
;
818 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
819 fields
[1].num_bits
= 27;
820 fields
[1].out_value
= packet
;
821 fields
[1].out_mask
= NULL
;
822 fields
[1].in_value
= NULL
;
823 fields
[1].in_check_value
= NULL
;
824 fields
[1].in_check_mask
= NULL
;
825 fields
[1].in_handler
= NULL
;
826 fields
[1].in_handler_priv
= NULL
;
828 jtag_add_dr_scan(2, fields
, -1);
830 fields
[0].num_bits
= 32;
831 fields
[0].out_value
= packet
;
833 fields
[1].num_bits
= 1;
834 fields
[1].out_value
= &cmd
;
836 for (word
= 0; word
< 8; word
++)
838 buf_set_u32(packet
, 0, 32, buffer
[word
]);
839 cmd
= parity(*((u32
*)packet
));
840 jtag_add_dr_scan(2, fields
, -1);
843 jtag_execute_queue();
848 int xscale_invalidate_ic_line(target_t
*target
, u32 va
)
850 armv4_5_common_t
*armv4_5
= target
->arch_info
;
851 xscale_common_t
*xscale
= armv4_5
->arch_info
;
855 scan_field_t fields
[2];
857 jtag_add_end_state(TAP_RTI
);
858 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.ldic
); /* LDIC */
860 /* CMD for invalidate IC line b000, bits [6:4] b000 */
861 buf_set_u32(&cmd
, 0, 6, 0x0);
863 /* virtual address of desired cache line */
864 buf_set_u32(packet
, 0, 27, va
>> 5);
866 fields
[0].device
= xscale
->jtag_info
.chain_pos
;
867 fields
[0].num_bits
= 6;
868 fields
[0].out_value
= &cmd
;
869 fields
[0].out_mask
= NULL
;
870 fields
[0].in_value
= NULL
;
871 fields
[0].in_check_value
= NULL
;
872 fields
[0].in_check_mask
= NULL
;
873 fields
[0].in_handler
= NULL
;
874 fields
[0].in_handler_priv
= NULL
;
876 fields
[1].device
= xscale
->jtag_info
.chain_pos
;
877 fields
[1].num_bits
= 27;
878 fields
[1].out_value
= packet
;
879 fields
[1].out_mask
= NULL
;
880 fields
[1].in_value
= NULL
;
881 fields
[1].in_check_value
= NULL
;
882 fields
[1].in_check_mask
= NULL
;
883 fields
[1].in_handler
= NULL
;
884 fields
[1].in_handler_priv
= NULL
;
886 jtag_add_dr_scan(2, fields
, -1);
891 int xscale_update_vectors(target_t
*target
)
893 armv4_5_common_t
*armv4_5
= target
->arch_info
;
894 xscale_common_t
*xscale
= armv4_5
->arch_info
;
898 u32 low_reset_branch
, high_reset_branch
;
900 for (i
= 1; i
< 8; i
++)
902 /* if there's a static vector specified for this exception, override */
903 if (xscale
->static_high_vectors_set
& (1 << i
))
905 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
909 retval
=target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
910 if (retval
== ERROR_TARGET_TIMEOUT
)
912 if (retval
!=ERROR_OK
)
914 /* Some of these reads will fail as part of normal execution */
915 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
920 for (i
= 1; i
< 8; i
++)
922 if (xscale
->static_low_vectors_set
& (1 << i
))
924 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
928 retval
=target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
929 if (retval
== ERROR_TARGET_TIMEOUT
)
931 if (retval
!=ERROR_OK
)
933 /* Some of these reads will fail as part of normal execution */
934 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
939 /* calculate branches to debug handler */
940 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
941 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
943 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
944 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
946 /* invalidate and load exception vectors in mini i-cache */
947 xscale_invalidate_ic_line(target
, 0x0);
948 xscale_invalidate_ic_line(target
, 0xffff0000);
950 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
951 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
956 int xscale_arch_state(struct target_s
*target
)
958 armv4_5_common_t
*armv4_5
= target
->arch_info
;
959 xscale_common_t
*xscale
= armv4_5
->arch_info
;
963 "disabled", "enabled"
966 char *arch_dbg_reason
[] =
968 "", "\n(processor reset)", "\n(trace buffer full)"
971 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
973 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
977 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
978 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
979 "MMU: %s, D-Cache: %s, I-Cache: %s"
981 armv4_5_state_strings
[armv4_5
->core_state
],
982 target_debug_reason_strings
[target
->debug_reason
],
983 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
984 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
985 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
986 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
987 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
988 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
989 arch_dbg_reason
[xscale
->arch_debug_reason
]);
994 int xscale_poll(target_t
*target
)
997 armv4_5_common_t
*armv4_5
= target
->arch_info
;
998 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1000 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
1002 enum target_state previous_state
= target
->state
;
1003 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
1006 /* there's data to read from the tx register, we entered debug state */
1007 xscale
->handler_running
= 1;
1009 target
->state
= TARGET_HALTED
;
1011 /* process debug entry, fetching current mode regs */
1012 retval
= xscale_debug_entry(target
);
1014 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1016 LOG_USER("error while polling TX register, reset CPU");
1017 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
1018 target
->state
= TARGET_HALTED
;
1021 /* debug_entry could have overwritten target state (i.e. immediate resume)
1022 * don't signal event handlers in that case
1024 if (target
->state
!= TARGET_HALTED
)
1027 /* if target was running, signal that we halted
1028 * otherwise we reentered from debug execution */
1029 if (previous_state
== TARGET_RUNNING
)
1030 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1032 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
1038 int xscale_debug_entry(target_t
*target
)
1040 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1041 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1049 /* clear external dbg break (will be written on next DCSR read) */
1050 xscale
->external_debug_break
= 0;
1051 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
1054 /* get r0, pc, r1 to r7 and cpsr */
1055 if ((retval
=xscale_receive(target
, buffer
, 10))!=ERROR_OK
)
1058 /* move r0 from buffer to register cache */
1059 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
1060 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1061 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1062 LOG_DEBUG("r0: 0x%8.8x", buffer
[0]);
1064 /* move pc from buffer to register cache */
1065 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
1066 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1067 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1068 LOG_DEBUG("pc: 0x%8.8x", buffer
[1]);
1070 /* move data from buffer to register cache */
1071 for (i
= 1; i
<= 7; i
++)
1073 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
1074 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
1075 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
1076 LOG_DEBUG("r%i: 0x%8.8x", i
, buffer
[i
+ 1]);
1079 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, buffer
[9]);
1080 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1081 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1082 LOG_DEBUG("cpsr: 0x%8.8x", buffer
[9]);
1084 armv4_5
->core_mode
= buffer
[9] & 0x1f;
1085 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1087 target
->state
= TARGET_UNKNOWN
;
1088 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1089 return ERROR_TARGET_FAILURE
;
1091 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1093 if (buffer
[9] & 0x20)
1094 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1096 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1099 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1102 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1103 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1105 xscale_receive(target
, buffer
, 8);
1106 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1107 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1108 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1112 /* r8 to r14, but no spsr */
1113 xscale_receive(target
, buffer
, 7);
1116 /* move data from buffer to register cache */
1117 for (i
= 8; i
<= 14; i
++)
1119 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, buffer
[i
- 8]);
1120 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1121 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1124 /* examine debug reason */
1125 xscale_read_dcsr(target
);
1126 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1128 /* stored PC (for calculating fixup) */
1129 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1133 case 0x0: /* Processor reset */
1134 target
->debug_reason
= DBG_REASON_DBGRQ
;
1135 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1138 case 0x1: /* Instruction breakpoint hit */
1139 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1140 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1143 case 0x2: /* Data breakpoint hit */
1144 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1145 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1148 case 0x3: /* BKPT instruction executed */
1149 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1150 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1153 case 0x4: /* Ext. debug event */
1154 target
->debug_reason
= DBG_REASON_DBGRQ
;
1155 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1158 case 0x5: /* Vector trap occured */
1159 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1160 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1163 case 0x6: /* Trace buffer full break */
1164 target
->debug_reason
= DBG_REASON_DBGRQ
;
1165 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1168 case 0x7: /* Reserved */
1170 LOG_ERROR("Method of Entry is 'Reserved'");
1175 /* apply PC fixup */
1176 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1178 /* on the first debug entry, identify cache type */
1179 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1183 /* read cp15 cache type register */
1184 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1185 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1187 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1190 /* examine MMU and Cache settings */
1191 /* read cp15 control register */
1192 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1193 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1194 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1195 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1196 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1198 /* tracing enabled, read collected trace data */
1199 if (xscale
->trace
.buffer_enabled
)
1201 xscale_read_trace(target
);
1202 xscale
->trace
.buffer_fill
--;
1204 /* resume if we're still collecting trace data */
1205 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1206 && (xscale
->trace
.buffer_fill
> 0))
1208 xscale_resume(target
, 1, 0x0, 1, 0);
1212 xscale
->trace
.buffer_enabled
= 0;
1219 int xscale_halt(target_t
*target
)
1221 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1222 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1224 LOG_DEBUG("target->state: %s", target_state_strings
[target
->state
]);
1226 if (target
->state
== TARGET_HALTED
)
1228 LOG_DEBUG("target was already halted");
1231 else if (target
->state
== TARGET_UNKNOWN
)
1233 /* this must not happen for a xscale target */
1234 LOG_ERROR("target was in unknown state when halt was requested");
1235 return ERROR_TARGET_INVALID
;
1237 else if (target
->state
== TARGET_RESET
)
1239 LOG_DEBUG("target->state == TARGET_RESET");
1243 /* assert external dbg break */
1244 xscale
->external_debug_break
= 1;
1245 xscale_read_dcsr(target
);
1247 target
->debug_reason
= DBG_REASON_DBGRQ
;
1253 int xscale_enable_single_step(struct target_s
*target
, u32 next_pc
)
1255 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1256 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1257 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1259 if (xscale
->ibcr0_used
)
1261 breakpoint_t
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1265 xscale_unset_breakpoint(target
, ibcr0_bp
);
1269 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1274 xscale_set_reg_u32(ibcr0
, next_pc
| 0x1);
1279 int xscale_disable_single_step(struct target_s
*target
)
1281 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1282 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1283 reg_t
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1285 xscale_set_reg_u32(ibcr0
, 0x0);
1290 int xscale_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
1292 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1293 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1294 breakpoint_t
*breakpoint
= target
->breakpoints
;
1303 if (target
->state
!= TARGET_HALTED
)
1305 LOG_WARNING("target not halted");
1306 return ERROR_TARGET_NOT_HALTED
;
1309 if (!debug_execution
)
1311 target_free_all_working_areas(target
);
1314 /* update vector tables */
1315 if ((retval
=xscale_update_vectors(target
))!=ERROR_OK
)
1318 /* current = 1: continue on current pc, otherwise continue at <address> */
1320 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1322 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1324 /* if we're at the reset vector, we have to simulate the branch */
1325 if (current_pc
== 0x0)
1327 arm_simulate_step(target
, NULL
);
1328 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1331 /* the front-end may request us not to handle breakpoints */
1332 if (handle_breakpoints
)
1334 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1338 /* there's a breakpoint at the current PC, we have to step over it */
1339 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1340 xscale_unset_breakpoint(target
, breakpoint
);
1342 /* calculate PC of next instruction */
1343 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1346 target_read_u32(target
, current_pc
, ¤t_opcode
);
1347 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1350 LOG_DEBUG("enable single-step");
1351 xscale_enable_single_step(target
, next_pc
);
1353 /* restore banked registers */
1354 xscale_restore_context(target
);
1356 /* send resume request (command 0x30 or 0x31)
1357 * clean the trace buffer if it is to be enabled (0x62) */
1358 if (xscale
->trace
.buffer_enabled
)
1360 xscale_send_u32(target
, 0x62);
1361 xscale_send_u32(target
, 0x31);
1364 xscale_send_u32(target
, 0x30);
1367 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1368 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1370 for (i
= 7; i
>= 0; i
--)
1373 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1374 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1378 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1379 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1381 /* wait for and process debug entry */
1382 xscale_debug_entry(target
);
1384 LOG_DEBUG("disable single-step");
1385 xscale_disable_single_step(target
);
1387 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint
->address
);
1388 xscale_set_breakpoint(target
, breakpoint
);
1392 /* enable any pending breakpoints and watchpoints */
1393 xscale_enable_breakpoints(target
);
1394 xscale_enable_watchpoints(target
);
1396 /* restore banked registers */
1397 xscale_restore_context(target
);
1399 /* send resume request (command 0x30 or 0x31)
1400 * clean the trace buffer if it is to be enabled (0x62) */
1401 if (xscale
->trace
.buffer_enabled
)
1403 xscale_send_u32(target
, 0x62);
1404 xscale_send_u32(target
, 0x31);
1407 xscale_send_u32(target
, 0x30);
1410 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1411 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1413 for (i
= 7; i
>= 0; i
--)
1416 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1417 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1421 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1422 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1424 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1426 if (!debug_execution
)
1428 /* registers are now invalid */
1429 armv4_5_invalidate_core_regs(target
);
1430 target
->state
= TARGET_RUNNING
;
1431 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1435 target
->state
= TARGET_DEBUG_RUNNING
;
1436 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1439 LOG_DEBUG("target resumed");
1441 xscale
->handler_running
= 1;
1446 int xscale_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
1448 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1449 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1450 breakpoint_t
*breakpoint
= target
->breakpoints
;
1452 u32 current_pc
, next_pc
;
1456 if (target
->state
!= TARGET_HALTED
)
1458 LOG_WARNING("target not halted");
1459 return ERROR_TARGET_NOT_HALTED
;
1462 /* current = 1: continue on current pc, otherwise continue at <address> */
1464 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1466 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1468 /* if we're at the reset vector, we have to simulate the step */
1469 if (current_pc
== 0x0)
1471 arm_simulate_step(target
, NULL
);
1472 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1474 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1475 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1480 /* the front-end may request us not to handle breakpoints */
1481 if (handle_breakpoints
)
1482 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1484 xscale_unset_breakpoint(target
, breakpoint
);
1487 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1489 /* calculate PC of next instruction */
1490 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1493 target_read_u32(target
, current_pc
, ¤t_opcode
);
1494 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode
);
1497 LOG_DEBUG("enable single-step");
1498 xscale_enable_single_step(target
, next_pc
);
1500 /* restore banked registers */
1501 xscale_restore_context(target
);
1503 /* send resume request (command 0x30 or 0x31)
1504 * clean the trace buffer if it is to be enabled (0x62) */
1505 if (xscale
->trace
.buffer_enabled
)
1507 xscale_send_u32(target
, 0x62);
1508 xscale_send_u32(target
, 0x31);
1511 xscale_send_u32(target
, 0x30);
1514 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1515 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1517 for (i
= 7; i
>= 0; i
--)
1520 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1521 LOG_DEBUG("writing r%i with value 0x%8.8x", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1525 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1526 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1528 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1530 /* registers are now invalid */
1531 armv4_5_invalidate_core_regs(target
);
1533 /* wait for and process debug entry */
1534 xscale_debug_entry(target
);
1536 LOG_DEBUG("disable single-step");
1537 xscale_disable_single_step(target
);
1539 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1543 xscale_set_breakpoint(target
, breakpoint
);
1546 LOG_DEBUG("target stepped");
1552 int xscale_assert_reset(target_t
*target
)
1554 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1555 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1557 LOG_DEBUG("target->state: %s", target_state_strings
[target
->state
]);
1559 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1560 * end up in T-L-R, which would reset JTAG
1562 jtag_add_end_state(TAP_RTI
);
1563 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, xscale
->jtag_info
.dcsr
);
1565 /* set Hold reset, Halt mode and Trap Reset */
1566 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1567 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1568 xscale_write_dcsr(target
, 1, 0);
1570 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1571 xscale_jtag_set_instr(xscale
->jtag_info
.chain_pos
, 0x7f);
1572 jtag_execute_queue();
1575 jtag_add_reset(0, 1);
1577 /* sleep 1ms, to be sure we fulfill any requirements */
1578 jtag_add_sleep(1000);
1579 jtag_execute_queue();
1581 target
->state
= TARGET_RESET
;
1583 if (target
->reset_halt
)
1586 if ((retval
= target_halt(target
))!=ERROR_OK
)
1593 int xscale_deassert_reset(target_t
*target
)
1595 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1596 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1598 fileio_t debug_handler
;
1606 breakpoint_t
*breakpoint
= target
->breakpoints
;
1610 xscale
->ibcr_available
= 2;
1611 xscale
->ibcr0_used
= 0;
1612 xscale
->ibcr1_used
= 0;
1614 xscale
->dbr_available
= 2;
1615 xscale
->dbr0_used
= 0;
1616 xscale
->dbr1_used
= 0;
1618 /* mark all hardware breakpoints as unset */
1621 if (breakpoint
->type
== BKPT_HARD
)
1623 breakpoint
->set
= 0;
1625 breakpoint
= breakpoint
->next
;
1628 if (!xscale
->handler_installed
)
1631 jtag_add_reset(0, 0);
1633 /* wait 300ms; 150 and 100ms were not enough */
1634 jtag_add_sleep(300*1000);
1636 jtag_add_runtest(2030, TAP_RTI
);
1637 jtag_execute_queue();
1639 /* set Hold reset, Halt mode and Trap Reset */
1640 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1641 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1642 xscale_write_dcsr(target
, 1, 0);
1644 /* Load debug handler */
1645 if (fileio_open(&debug_handler
, "xscale/debug_handler.bin", FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1650 if ((binary_size
= debug_handler
.size
) % 4)
1652 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1656 if (binary_size
> 0x800)
1658 LOG_ERROR("debug_handler.bin: larger than 2kb");
1662 binary_size
= CEIL(binary_size
, 32) * 32;
1664 address
= xscale
->handler_address
;
1665 while (binary_size
> 0)
1670 if ((retval
= fileio_read(&debug_handler
, 32, buffer
, &buf_cnt
)) != ERROR_OK
)
1675 for (i
= 0; i
< buf_cnt
; i
+= 4)
1677 /* convert LE buffer to host-endian u32 */
1678 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1681 for (; buf_cnt
< 32; buf_cnt
+= 4)
1683 cache_line
[buf_cnt
/ 4] = 0xe1a08008;
1686 /* only load addresses other than the reset vectors */
1687 if ((address
% 0x400) != 0x0)
1689 xscale_load_ic(target
, 1, address
, cache_line
);
1693 binary_size
-= buf_cnt
;
1696 xscale_load_ic(target
, 1, 0x0, xscale
->low_vectors
);
1697 xscale_load_ic(target
, 1, 0xffff0000, xscale
->high_vectors
);
1699 jtag_add_runtest(30, TAP_RTI
);
1701 jtag_add_sleep(100000);
1703 /* set Hold reset, Halt mode and Trap Reset */
1704 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1705 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1706 xscale_write_dcsr(target
, 1, 0);
1708 /* clear Hold reset to let the target run (should enter debug handler) */
1709 xscale_write_dcsr(target
, 0, 1);
1710 target
->state
= TARGET_RUNNING
;
1712 if (!target
->reset_halt
)
1714 jtag_add_sleep(10000);
1716 /* we should have entered debug now */
1717 xscale_debug_entry(target
);
1718 target
->state
= TARGET_HALTED
;
1720 /* resume the target */
1721 xscale_resume(target
, 1, 0x0, 1, 0);
1724 fileio_close(&debug_handler
);
1728 jtag_add_reset(0, 0);
1735 int xscale_soft_reset_halt(struct target_s
*target
)
1741 int xscale_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
1747 int xscale_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, u32 value
)
1753 int xscale_full_context(target_t
*target
)
1755 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1763 if (target
->state
!= TARGET_HALTED
)
1765 LOG_WARNING("target not halted");
1766 return ERROR_TARGET_NOT_HALTED
;
1769 buffer
= malloc(4 * 8);
1771 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1772 * we can't enter User mode on an XScale (unpredictable),
1773 * but User shares registers with SYS
1775 for(i
= 1; i
< 7; i
++)
1779 /* check if there are invalid registers in the current mode
1781 for (j
= 0; j
<= 16; j
++)
1783 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1791 /* request banked registers */
1792 xscale_send_u32(target
, 0x0);
1795 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1796 tmp_cpsr
|= 0xc0; /* I/F bits */
1798 /* send CPSR for desired mode */
1799 xscale_send_u32(target
, tmp_cpsr
);
1801 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1802 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1804 xscale_receive(target
, buffer
, 8);
1805 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, buffer
[7]);
1806 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1807 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1811 xscale_receive(target
, buffer
, 7);
1814 /* move data from buffer to register cache */
1815 for (j
= 8; j
<= 14; j
++)
1817 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
, 0, 32, buffer
[j
- 8]);
1818 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1819 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1829 int xscale_restore_context(target_t
*target
)
1831 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1837 if (target
->state
!= TARGET_HALTED
)
1839 LOG_WARNING("target not halted");
1840 return ERROR_TARGET_NOT_HALTED
;
1843 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1844 * we can't enter User mode on an XScale (unpredictable),
1845 * but User shares registers with SYS
1847 for(i
= 1; i
< 7; i
++)
1851 /* check if there are invalid registers in the current mode
1853 for (j
= 8; j
<= 14; j
++)
1855 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1859 /* if not USR/SYS, check if the SPSR needs to be written */
1860 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1862 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1870 /* send banked registers */
1871 xscale_send_u32(target
, 0x1);
1874 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1875 tmp_cpsr
|= 0xc0; /* I/F bits */
1877 /* send CPSR for desired mode */
1878 xscale_send_u32(target
, tmp_cpsr
);
1880 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1881 for (j
= 8; j
<= 14; j
++)
1883 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1884 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1887 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1889 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1890 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1898 int xscale_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1900 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1901 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1906 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1908 if (target
->state
!= TARGET_HALTED
)
1910 LOG_WARNING("target not halted");
1911 return ERROR_TARGET_NOT_HALTED
;
1914 /* sanitize arguments */
1915 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1916 return ERROR_INVALID_ARGUMENTS
;
1918 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1919 return ERROR_TARGET_UNALIGNED_ACCESS
;
1921 /* send memory read request (command 0x1n, n: access size) */
1922 if ((retval
=xscale_send_u32(target
, 0x10 | size
))!=ERROR_OK
)
1925 /* send base address for read request */
1926 if ((retval
=xscale_send_u32(target
, address
))!=ERROR_OK
)
1929 /* send number of requested data words */
1930 if ((retval
=xscale_send_u32(target
, count
))!=ERROR_OK
)
1933 /* receive data from target (count times 32-bit words in host endianness) */
1934 buf32
= malloc(4 * count
);
1935 if ((retval
=xscale_receive(target
, buf32
, count
))!=ERROR_OK
)
1938 /* extract data from host-endian buffer into byte stream */
1939 for (i
= 0; i
< count
; i
++)
1944 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1948 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1952 *buffer
++ = buf32
[i
] & 0xff;
1955 LOG_ERROR("should never get here");
1962 /* examine DCSR, to see if Sticky Abort (SA) got set */
1963 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
1965 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1968 if ((retval
=xscale_send_u32(target
, 0x60))!=ERROR_OK
)
1971 return ERROR_TARGET_DATA_ABORT
;
1977 int xscale_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
1979 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1980 xscale_common_t
*xscale
= armv4_5
->arch_info
;
1983 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
1985 if (target
->state
!= TARGET_HALTED
)
1987 LOG_WARNING("target not halted");
1988 return ERROR_TARGET_NOT_HALTED
;
1991 /* sanitize arguments */
1992 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1993 return ERROR_INVALID_ARGUMENTS
;
1995 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1996 return ERROR_TARGET_UNALIGNED_ACCESS
;
1998 /* send memory write request (command 0x2n, n: access size) */
1999 if ((retval
=xscale_send_u32(target
, 0x20 | size
))!=ERROR_OK
)
2002 /* send base address for read request */
2003 if ((retval
=xscale_send_u32(target
, address
))!=ERROR_OK
)
2006 /* send number of requested data words to be written*/
2007 if ((retval
=xscale_send_u32(target
, count
))!=ERROR_OK
)
2010 /* extract data from host-endian buffer into byte stream */
2012 for (i
= 0; i
< count
; i
++)
2017 value
= target_buffer_get_u32(target
, buffer
);
2018 xscale_send_u32(target
, value
);
2022 value
= target_buffer_get_u16(target
, buffer
);
2023 xscale_send_u32(target
, value
);
2028 xscale_send_u32(target
, value
);
2032 LOG_ERROR("should never get here");
2037 if ((retval
=xscale_send(target
, buffer
, count
, size
))!=ERROR_OK
)
2040 /* examine DCSR, to see if Sticky Abort (SA) got set */
2041 if ((retval
=xscale_read_dcsr(target
))!=ERROR_OK
)
2043 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
2046 if ((retval
=xscale_send_u32(target
, 0x60))!=ERROR_OK
)
2049 return ERROR_TARGET_DATA_ABORT
;
2055 int xscale_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
2057 return xscale_write_memory(target
, address
, 4, count
, buffer
);
2060 u32
xscale_get_ttb(target_t
*target
)
2062 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2063 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2066 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2067 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2072 void xscale_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2074 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2075 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2078 /* read cp15 control register */
2079 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2080 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2083 cp15_control
&= ~0x1U
;
2088 xscale_send_u32(target
, 0x50);
2089 xscale_send_u32(target
, xscale
->cache_clean_address
);
2091 /* invalidate DCache */
2092 xscale_send_u32(target
, 0x51);
2094 cp15_control
&= ~0x4U
;
2099 /* invalidate ICache */
2100 xscale_send_u32(target
, 0x52);
2101 cp15_control
&= ~0x1000U
;
2104 /* write new cp15 control register */
2105 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2107 /* execute cpwait to ensure outstanding operations complete */
2108 xscale_send_u32(target
, 0x53);
2111 void xscale_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
2113 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2114 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2117 /* read cp15 control register */
2118 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2119 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2122 cp15_control
|= 0x1U
;
2125 cp15_control
|= 0x4U
;
2128 cp15_control
|= 0x1000U
;
2130 /* write new cp15 control register */
2131 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2133 /* execute cpwait to ensure outstanding operations complete */
2134 xscale_send_u32(target
, 0x53);
2137 int xscale_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2139 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2140 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2142 if (target
->state
!= TARGET_HALTED
)
2144 LOG_WARNING("target not halted");
2145 return ERROR_TARGET_NOT_HALTED
;
2148 if (xscale
->force_hw_bkpts
)
2149 breakpoint
->type
= BKPT_HARD
;
2151 if (breakpoint
->set
)
2153 LOG_WARNING("breakpoint already set");
2157 if (breakpoint
->type
== BKPT_HARD
)
2159 u32 value
= breakpoint
->address
| 1;
2160 if (!xscale
->ibcr0_used
)
2162 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2163 xscale
->ibcr0_used
= 1;
2164 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2166 else if (!xscale
->ibcr1_used
)
2168 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2169 xscale
->ibcr1_used
= 1;
2170 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2174 LOG_ERROR("BUG: no hardware comparator available");
2178 else if (breakpoint
->type
== BKPT_SOFT
)
2180 if (breakpoint
->length
== 4)
2182 /* keep the original instruction in target endianness */
2183 target
->type
->read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
2184 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2185 target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
);
2189 /* keep the original instruction in target endianness */
2190 target
->type
->read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
2191 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2192 target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
);
2194 breakpoint
->set
= 1;
2201 int xscale_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2203 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2204 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2206 if (target
->state
!= TARGET_HALTED
)
2208 LOG_WARNING("target not halted");
2209 return ERROR_TARGET_NOT_HALTED
;
2212 if (xscale
->force_hw_bkpts
)
2214 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint
->address
);
2215 breakpoint
->type
= BKPT_HARD
;
2218 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2220 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2221 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2225 xscale
->ibcr_available
--;
2228 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2230 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2231 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2237 int xscale_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2239 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2240 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2242 if (target
->state
!= TARGET_HALTED
)
2244 LOG_WARNING("target not halted");
2245 return ERROR_TARGET_NOT_HALTED
;
2248 if (!breakpoint
->set
)
2250 LOG_WARNING("breakpoint not set");
2254 if (breakpoint
->type
== BKPT_HARD
)
2256 if (breakpoint
->set
== 1)
2258 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2259 xscale
->ibcr0_used
= 0;
2261 else if (breakpoint
->set
== 2)
2263 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2264 xscale
->ibcr1_used
= 0;
2266 breakpoint
->set
= 0;
2270 /* restore original instruction (kept in target endianness) */
2271 if (breakpoint
->length
== 4)
2273 target
->type
->write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
);
2277 target
->type
->write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
);
2279 breakpoint
->set
= 0;
2285 int xscale_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
2287 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2288 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2290 if (target
->state
!= TARGET_HALTED
)
2292 LOG_WARNING("target not halted");
2293 return ERROR_TARGET_NOT_HALTED
;
2296 if (breakpoint
->set
)
2298 xscale_unset_breakpoint(target
, breakpoint
);
2301 if (breakpoint
->type
== BKPT_HARD
)
2302 xscale
->ibcr_available
++;
2307 int xscale_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2309 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2310 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2312 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2313 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2315 if (target
->state
!= TARGET_HALTED
)
2317 LOG_WARNING("target not halted");
2318 return ERROR_TARGET_NOT_HALTED
;
2321 xscale_get_reg(dbcon
);
2323 switch (watchpoint
->rw
)
2335 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2338 if (!xscale
->dbr0_used
)
2340 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2341 dbcon_value
|= enable
;
2342 xscale_set_reg_u32(dbcon
, dbcon_value
);
2343 watchpoint
->set
= 1;
2344 xscale
->dbr0_used
= 1;
2346 else if (!xscale
->dbr1_used
)
2348 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2349 dbcon_value
|= enable
<< 2;
2350 xscale_set_reg_u32(dbcon
, dbcon_value
);
2351 watchpoint
->set
= 2;
2352 xscale
->dbr1_used
= 1;
2356 LOG_ERROR("BUG: no hardware comparator available");
2363 int xscale_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2365 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2366 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2368 if (target
->state
!= TARGET_HALTED
)
2370 LOG_WARNING("target not halted");
2371 return ERROR_TARGET_NOT_HALTED
;
2374 if (xscale
->dbr_available
< 1)
2376 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2379 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2381 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2384 xscale
->dbr_available
--;
2389 int xscale_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2391 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2392 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2393 reg_t
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2394 u32 dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2396 if (target
->state
!= TARGET_HALTED
)
2398 LOG_WARNING("target not halted");
2399 return ERROR_TARGET_NOT_HALTED
;
2402 if (!watchpoint
->set
)
2404 LOG_WARNING("breakpoint not set");
2408 if (watchpoint
->set
== 1)
2410 dbcon_value
&= ~0x3;
2411 xscale_set_reg_u32(dbcon
, dbcon_value
);
2412 xscale
->dbr0_used
= 0;
2414 else if (watchpoint
->set
== 2)
2416 dbcon_value
&= ~0xc;
2417 xscale_set_reg_u32(dbcon
, dbcon_value
);
2418 xscale
->dbr1_used
= 0;
2420 watchpoint
->set
= 0;
2425 int xscale_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
2427 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2428 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2430 if (target
->state
!= TARGET_HALTED
)
2432 LOG_WARNING("target not halted");
2433 return ERROR_TARGET_NOT_HALTED
;
2436 if (watchpoint
->set
)
2438 xscale_unset_watchpoint(target
, watchpoint
);
2441 xscale
->dbr_available
++;
2446 void xscale_enable_watchpoints(struct target_s
*target
)
2448 watchpoint_t
*watchpoint
= target
->watchpoints
;
2452 if (watchpoint
->set
== 0)
2453 xscale_set_watchpoint(target
, watchpoint
);
2454 watchpoint
= watchpoint
->next
;
2458 void xscale_enable_breakpoints(struct target_s
*target
)
2460 breakpoint_t
*breakpoint
= target
->breakpoints
;
2462 /* set any pending breakpoints */
2465 if (breakpoint
->set
== 0)
2466 xscale_set_breakpoint(target
, breakpoint
);
2467 breakpoint
= breakpoint
->next
;
2471 int xscale_get_reg(reg_t
*reg
)
2473 xscale_reg_t
*arch_info
= reg
->arch_info
;
2474 target_t
*target
= arch_info
->target
;
2475 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2476 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2478 /* DCSR, TX and RX are accessible via JTAG */
2479 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2481 return xscale_read_dcsr(arch_info
->target
);
2483 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2485 /* 1 = consume register content */
2486 return xscale_read_tx(arch_info
->target
, 1);
2488 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2490 /* can't read from RX register (host -> debug handler) */
2493 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2495 /* can't (explicitly) read from TXRXCTRL register */
2498 else /* Other DBG registers have to be transfered by the debug handler */
2500 /* send CP read request (command 0x40) */
2501 xscale_send_u32(target
, 0x40);
2503 /* send CP register number */
2504 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2506 /* read register value */
2507 xscale_read_tx(target
, 1);
2508 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2517 int xscale_set_reg(reg_t
*reg
, u8
* buf
)
2519 xscale_reg_t
*arch_info
= reg
->arch_info
;
2520 target_t
*target
= arch_info
->target
;
2521 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2522 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2523 u32 value
= buf_get_u32(buf
, 0, 32);
2525 /* DCSR, TX and RX are accessible via JTAG */
2526 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2528 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2529 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2531 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2533 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2534 return xscale_write_rx(arch_info
->target
);
2536 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2538 /* can't write to TX register (debug-handler -> host) */
2541 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2543 /* can't (explicitly) write to TXRXCTRL register */
2546 else /* Other DBG registers have to be transfered by the debug handler */
2548 /* send CP write request (command 0x41) */
2549 xscale_send_u32(target
, 0x41);
2551 /* send CP register number */
2552 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2554 /* send CP register value */
2555 xscale_send_u32(target
, value
);
2556 buf_set_u32(reg
->value
, 0, 32, value
);
2562 /* convenience wrapper to access XScale specific registers */
2563 int xscale_set_reg_u32(reg_t
*reg
, u32 value
)
2567 buf_set_u32(buf
, 0, 32, value
);
2569 return xscale_set_reg(reg
, buf
);
2572 int xscale_write_dcsr_sw(target_t
*target
, u32 value
)
2574 /* get pointers to arch-specific information */
2575 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2576 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2577 reg_t
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2578 xscale_reg_t
*dcsr_arch_info
= dcsr
->arch_info
;
2580 /* send CP write request (command 0x41) */
2581 xscale_send_u32(target
, 0x41);
2583 /* send CP register number */
2584 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2586 /* send CP register value */
2587 xscale_send_u32(target
, value
);
2588 buf_set_u32(dcsr
->value
, 0, 32, value
);
2593 int xscale_read_trace(target_t
*target
)
2595 /* get pointers to arch-specific information */
2596 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2597 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2598 xscale_trace_data_t
**trace_data_p
;
2600 /* 258 words from debug handler
2601 * 256 trace buffer entries
2602 * 2 checkpoint addresses
2604 u32 trace_buffer
[258];
2605 int is_address
[256];
2608 if (target
->state
!= TARGET_HALTED
)
2610 LOG_WARNING("target must be stopped to read trace data");
2611 return ERROR_TARGET_NOT_HALTED
;
2614 /* send read trace buffer command (command 0x61) */
2615 xscale_send_u32(target
, 0x61);
2617 /* receive trace buffer content */
2618 xscale_receive(target
, trace_buffer
, 258);
2620 /* parse buffer backwards to identify address entries */
2621 for (i
= 255; i
>= 0; i
--)
2624 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2625 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2628 is_address
[--i
] = 1;
2630 is_address
[--i
] = 1;
2632 is_address
[--i
] = 1;
2634 is_address
[--i
] = 1;
2639 /* search first non-zero entry */
2640 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2645 LOG_DEBUG("no trace data collected");
2646 return ERROR_XSCALE_NO_TRACE_DATA
;
2649 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2652 *trace_data_p
= malloc(sizeof(xscale_trace_data_t
));
2653 (*trace_data_p
)->next
= NULL
;
2654 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2655 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2656 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2657 (*trace_data_p
)->entries
= malloc(sizeof(xscale_trace_entry_t
) * (256 - j
));
2658 (*trace_data_p
)->depth
= 256 - j
;
2660 for (i
= j
; i
< 256; i
++)
2662 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2664 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2666 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2672 int xscale_read_instruction(target_t
*target
, arm_instruction_t
*instruction
)
2674 /* get pointers to arch-specific information */
2675 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2676 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2683 if (!xscale
->trace
.image
)
2684 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2686 /* search for the section the current instruction belongs to */
2687 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2689 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2690 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2699 /* current instruction couldn't be found in the image */
2700 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2703 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2706 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2707 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2708 4, buf
, &size_read
)) != ERROR_OK
)
2710 LOG_ERROR("error while reading instruction: %i", retval
);
2711 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2713 opcode
= target_buffer_get_u32(target
, buf
);
2714 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2716 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2719 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2720 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2721 2, buf
, &size_read
)) != ERROR_OK
)
2723 LOG_ERROR("error while reading instruction: %i", retval
);
2724 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2726 opcode
= target_buffer_get_u16(target
, buf
);
2727 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2731 LOG_ERROR("BUG: unknown core state encountered");
2738 int xscale_branch_address(xscale_trace_data_t
*trace_data
, int i
, u32
*target
)
2740 /* if there are less than four entries prior to the indirect branch message
2741 * we can't extract the address */
2747 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2748 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2753 int xscale_analyze_trace(target_t
*target
, command_context_t
*cmd_ctx
)
2755 /* get pointers to arch-specific information */
2756 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2757 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2760 xscale_trace_data_t
*trace_data
= xscale
->trace
.data
;
2769 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2774 for (i
= 0; i
< trace_data
->depth
; i
++)
2780 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2783 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2785 case 0: /* Exceptions */
2793 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2795 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2796 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2798 case 8: /* Direct Branch */
2801 case 9: /* Indirect Branch */
2803 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2808 case 13: /* Checkpointed Indirect Branch */
2809 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2812 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2813 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2814 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2816 /* explicit fall-through */
2817 case 12: /* Checkpointed Direct Branch */
2822 next_pc
= trace_data
->chkpt0
;
2825 else if (chkpt
== 1)
2828 next_pc
= trace_data
->chkpt0
;
2833 LOG_WARNING("more than two checkpointed branches encountered");
2836 case 15: /* Roll-over */
2839 default: /* Reserved */
2840 command_print(cmd_ctx
, "--- reserved trace message ---");
2841 LOG_ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2845 if (xscale
->trace
.pc_ok
)
2847 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2848 arm_instruction_t instruction
;
2850 if ((exception
== 6) || (exception
== 7))
2852 /* IRQ or FIQ exception, no instruction executed */
2856 while (executed
-- >= 0)
2858 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2860 /* can't continue tracing with no image available */
2861 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2865 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2867 /* TODO: handle incomplete images */
2871 /* a precise abort on a load to the PC is included in the incremental
2872 * word count, other instructions causing data aborts are not included
2874 if ((executed
== 0) && (exception
== 4)
2875 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2877 if ((instruction
.type
== ARM_LDM
)
2878 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2882 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2883 && (instruction
.info
.load_store
.Rd
!= 15))
2889 /* only the last instruction executed
2890 * (the one that caused the control flow change)
2891 * could be a taken branch
2893 if (((executed
== -1) && (branch
== 1)) &&
2894 (((instruction
.type
== ARM_B
) ||
2895 (instruction
.type
== ARM_BL
) ||
2896 (instruction
.type
== ARM_BLX
)) &&
2897 (instruction
.info
.b_bl_bx_blx
.target_address
!= -1)))
2899 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2903 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2905 command_print(cmd_ctx
, "%s", instruction
.text
);
2913 xscale
->trace
.current_pc
= next_pc
;
2914 xscale
->trace
.pc_ok
= 1;
2918 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2920 arm_instruction_t instruction
;
2921 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2923 /* can't continue tracing with no image available */
2924 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2928 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2930 /* TODO: handle incomplete images */
2933 command_print(cmd_ctx
, "%s", instruction
.text
);
2936 trace_data
= trace_data
->next
;
2942 void xscale_build_reg_cache(target_t
*target
)
2944 /* get pointers to arch-specific information */
2945 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2946 xscale_common_t
*xscale
= armv4_5
->arch_info
;
2948 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2949 xscale_reg_t
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2951 int num_regs
= sizeof(xscale_reg_arch_info
) / sizeof(xscale_reg_t
);
2953 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2954 armv4_5
->core_cache
= (*cache_p
);
2956 /* register a register arch-type for XScale dbg registers only once */
2957 if (xscale_reg_arch_type
== -1)
2958 xscale_reg_arch_type
= register_reg_arch_type(xscale_get_reg
, xscale_set_reg
);
2960 (*cache_p
)->next
= malloc(sizeof(reg_cache_t
));
2961 cache_p
= &(*cache_p
)->next
;
2963 /* fill in values for the xscale reg cache */
2964 (*cache_p
)->name
= "XScale registers";
2965 (*cache_p
)->next
= NULL
;
2966 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(reg_t
));
2967 (*cache_p
)->num_regs
= num_regs
;
2969 for (i
= 0; i
< num_regs
; i
++)
2971 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2972 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2973 (*cache_p
)->reg_list
[i
].dirty
= 0;
2974 (*cache_p
)->reg_list
[i
].valid
= 0;
2975 (*cache_p
)->reg_list
[i
].size
= 32;
2976 (*cache_p
)->reg_list
[i
].bitfield_desc
= NULL
;
2977 (*cache_p
)->reg_list
[i
].num_bitfields
= 0;
2978 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
2979 (*cache_p
)->reg_list
[i
].arch_type
= xscale_reg_arch_type
;
2980 arch_info
[i
] = xscale_reg_arch_info
[i
];
2981 arch_info
[i
].target
= target
;
2984 xscale
->reg_cache
= (*cache_p
);
2987 int xscale_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
2992 int xscale_quit(void)
2998 int xscale_init_arch_info(target_t
*target
, xscale_common_t
*xscale
, int chain_pos
, char *variant
)
3000 armv4_5_common_t
*armv4_5
;
3001 u32 high_reset_branch
, low_reset_branch
;
3004 armv4_5
= &xscale
->armv4_5_common
;
3006 /* store architecture specfic data (none so far) */
3007 xscale
->arch_info
= NULL
;
3008 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
3010 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3011 xscale
->variant
= strdup(variant
);
3013 /* prepare JTAG information for the new target */
3014 xscale
->jtag_info
.chain_pos
= chain_pos
;
3016 xscale
->jtag_info
.dbgrx
= 0x02;
3017 xscale
->jtag_info
.dbgtx
= 0x10;
3018 xscale
->jtag_info
.dcsr
= 0x09;
3019 xscale
->jtag_info
.ldic
= 0x07;
3021 if ((strcmp(xscale
->variant
, "pxa250") == 0) ||
3022 (strcmp(xscale
->variant
, "pxa255") == 0) ||
3023 (strcmp(xscale
->variant
, "pxa26x") == 0))
3025 xscale
->jtag_info
.ir_length
= 5;
3027 else if ((strcmp(xscale
->variant
, "pxa27x") == 0) ||
3028 (strcmp(xscale
->variant
, "ixp42x") == 0) ||
3029 (strcmp(xscale
->variant
, "ixp45x") == 0) ||
3030 (strcmp(xscale
->variant
, "ixp46x") == 0))
3032 xscale
->jtag_info
.ir_length
= 7;
3035 /* the debug handler isn't installed (and thus not running) at this time */
3036 xscale
->handler_installed
= 0;
3037 xscale
->handler_running
= 0;
3038 xscale
->handler_address
= 0xfe000800;
3040 /* clear the vectors we keep locally for reference */
3041 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
3042 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
3044 /* no user-specified vectors have been configured yet */
3045 xscale
->static_low_vectors_set
= 0x0;
3046 xscale
->static_high_vectors_set
= 0x0;
3048 /* calculate branches to debug handler */
3049 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
3050 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
3052 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
3053 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
3055 for (i
= 1; i
<= 7; i
++)
3057 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3058 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
3061 /* 64kB aligned region used for DCache cleaning */
3062 xscale
->cache_clean_address
= 0xfffe0000;
3064 xscale
->hold_rst
= 0;
3065 xscale
->external_debug_break
= 0;
3067 xscale
->force_hw_bkpts
= 1;
3069 xscale
->ibcr_available
= 2;
3070 xscale
->ibcr0_used
= 0;
3071 xscale
->ibcr1_used
= 0;
3073 xscale
->dbr_available
= 2;
3074 xscale
->dbr0_used
= 0;
3075 xscale
->dbr1_used
= 0;
3077 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
3078 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
3080 xscale
->vector_catch
= 0x1;
3082 xscale
->trace
.capture_status
= TRACE_IDLE
;
3083 xscale
->trace
.data
= NULL
;
3084 xscale
->trace
.image
= NULL
;
3085 xscale
->trace
.buffer_enabled
= 0;
3086 xscale
->trace
.buffer_fill
= 0;
3088 /* prepare ARMv4/5 specific information */
3089 armv4_5
->arch_info
= xscale
;
3090 armv4_5
->read_core_reg
= xscale_read_core_reg
;
3091 armv4_5
->write_core_reg
= xscale_write_core_reg
;
3092 armv4_5
->full_context
= xscale_full_context
;
3094 armv4_5_init_arch_info(target
, armv4_5
);
3096 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
3097 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
3098 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
3099 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
3100 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
3101 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
3102 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
3103 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3108 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3109 int xscale_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
3112 char *variant
= NULL
;
3113 xscale_common_t
*xscale
= malloc(sizeof(xscale_common_t
));
3114 memset(xscale
, 0, sizeof(*xscale
));
3118 LOG_ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
3122 chain_pos
= strtoul(args
[3], NULL
, 0);
3126 xscale_init_arch_info(target
, xscale
, chain_pos
, variant
);
3127 xscale_build_reg_cache(target
);
3132 int xscale_handle_debug_handler_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3134 target_t
*target
= NULL
;
3135 armv4_5_common_t
*armv4_5
;
3136 xscale_common_t
*xscale
;
3138 u32 handler_address
;
3142 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3146 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3148 LOG_ERROR("no target '%s' configured", args
[0]);
3152 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3157 handler_address
= strtoul(args
[1], NULL
, 0);
3159 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3160 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3162 xscale
->handler_address
= handler_address
;
3166 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3172 int xscale_handle_cache_clean_address_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3174 target_t
*target
= NULL
;
3175 armv4_5_common_t
*armv4_5
;
3176 xscale_common_t
*xscale
;
3178 u32 cache_clean_address
;
3182 LOG_ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
3186 if ((target
= get_target_by_num(strtoul(args
[0], NULL
, 0))) == NULL
)
3188 LOG_ERROR("no target '%s' configured", args
[0]);
3192 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3197 cache_clean_address
= strtoul(args
[1], NULL
, 0);
3199 if (cache_clean_address
& 0xffff)
3201 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3205 xscale
->cache_clean_address
= cache_clean_address
;
3211 int xscale_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3213 target_t
*target
= get_current_target(cmd_ctx
);
3214 armv4_5_common_t
*armv4_5
;
3215 xscale_common_t
*xscale
;
3217 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3222 return armv4_5_handle_cache_info_command(cmd_ctx
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3225 static int xscale_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
)
3227 armv4_5_common_t
*armv4_5
;
3228 xscale_common_t
*xscale
;
3236 if ((retval
= xscale_get_arch_pointers(target
, &armv4_5
, &xscale
)) != ERROR_OK
)
3240 u32 ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3249 static int xscale_mmu(struct target_s
*target
, int *enabled
)
3251 armv4_5_common_t
*armv4_5
= target
->arch_info
;
3252 xscale_common_t
*xscale
= armv4_5
->arch_info
;
3254 if (target
->state
!= TARGET_HALTED
)
3256 LOG_ERROR("Target not halted");
3257 return ERROR_TARGET_INVALID
;
3259 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3264 int xscale_handle_mmu_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3266 target_t
*target
= get_current_target(cmd_ctx
);
3267 armv4_5_common_t
*armv4_5
;
3268 xscale_common_t
*xscale
;
3270 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3275 if (target
->state
!= TARGET_HALTED
)
3277 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3283 if (strcmp("enable", args
[0]) == 0)
3285 xscale_enable_mmu_caches(target
, 1, 0, 0);
3286 xscale
->armv4_5_mmu
.mmu_enabled
= 1;
3288 else if (strcmp("disable", args
[0]) == 0)
3290 xscale_disable_mmu_caches(target
, 1, 0, 0);
3291 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3295 command_print(cmd_ctx
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3300 int xscale_handle_idcache_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3302 target_t
*target
= get_current_target(cmd_ctx
);
3303 armv4_5_common_t
*armv4_5
;
3304 xscale_common_t
*xscale
;
3305 int icache
= 0, dcache
= 0;
3307 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3312 if (target
->state
!= TARGET_HALTED
)
3314 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3318 if (strcmp(cmd
, "icache") == 0)
3320 else if (strcmp(cmd
, "dcache") == 0)
3325 if (strcmp("enable", args
[0]) == 0)
3327 xscale_enable_mmu_caches(target
, 0, dcache
, icache
);
3330 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 1;
3332 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 1;
3334 else if (strcmp("disable", args
[0]) == 0)
3336 xscale_disable_mmu_caches(target
, 0, dcache
, icache
);
3339 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
3341 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
3346 command_print(cmd_ctx
, "icache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
) ? "enabled" : "disabled");
3349 command_print(cmd_ctx
, "dcache %s", (xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
) ? "enabled" : "disabled");
3354 int xscale_handle_vector_catch_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3356 target_t
*target
= get_current_target(cmd_ctx
);
3357 armv4_5_common_t
*armv4_5
;
3358 xscale_common_t
*xscale
;
3360 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3367 command_print(cmd_ctx
, "usage: xscale vector_catch [mask]");
3371 xscale
->vector_catch
= strtoul(args
[0], NULL
, 0);
3372 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3373 xscale_write_dcsr(target
, -1, -1);
3376 command_print(cmd_ctx
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3381 int xscale_handle_force_hw_bkpts_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3383 target_t
*target
= get_current_target(cmd_ctx
);
3384 armv4_5_common_t
*armv4_5
;
3385 xscale_common_t
*xscale
;
3387 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3392 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3394 xscale
->force_hw_bkpts
= 1;
3396 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3398 xscale
->force_hw_bkpts
= 0;
3402 command_print(cmd_ctx
, "usage: xscale force_hw_bkpts <enable|disable>");
3405 command_print(cmd_ctx
, "force hardware breakpoints %s", (xscale
->force_hw_bkpts
) ? "enabled" : "disabled");
3410 int xscale_handle_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3412 target_t
*target
= get_current_target(cmd_ctx
);
3413 armv4_5_common_t
*armv4_5
;
3414 xscale_common_t
*xscale
;
3417 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3422 if (target
->state
!= TARGET_HALTED
)
3424 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3428 if ((argc
>= 1) && (strcmp("enable", args
[0]) == 0))
3430 xscale_trace_data_t
*td
, *next_td
;
3431 xscale
->trace
.buffer_enabled
= 1;
3433 /* free old trace data */
3434 td
= xscale
->trace
.data
;
3444 xscale
->trace
.data
= NULL
;
3446 else if ((argc
>= 1) && (strcmp("disable", args
[0]) == 0))
3448 xscale
->trace
.buffer_enabled
= 0;
3451 if ((argc
>= 2) && (strcmp("fill", args
[1]) == 0))
3454 xscale
->trace
.buffer_fill
= strtoul(args
[2], NULL
, 0);
3456 xscale
->trace
.buffer_fill
= 1;
3458 else if ((argc
>= 2) && (strcmp("wrap", args
[1]) == 0))
3460 xscale
->trace
.buffer_fill
= -1;
3463 if (xscale
->trace
.buffer_enabled
)
3465 /* if we enable the trace buffer in fill-once
3466 * mode we know the address of the first instruction */
3467 xscale
->trace
.pc_ok
= 1;
3468 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3472 /* otherwise the address is unknown, and we have no known good PC */
3473 xscale
->trace
.pc_ok
= 0;
3476 command_print(cmd_ctx
, "trace buffer %s (%s)",
3477 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3478 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3480 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3481 if (xscale
->trace
.buffer_fill
>= 0)
3482 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3484 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3489 int xscale_handle_trace_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3492 armv4_5_common_t
*armv4_5
;
3493 xscale_common_t
*xscale
;
3497 command_print(cmd_ctx
, "usage: xscale trace_image <file> [base address] [type]");
3501 target
= get_current_target(cmd_ctx
);
3503 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3508 if (xscale
->trace
.image
)
3510 image_close(xscale
->trace
.image
);
3511 free(xscale
->trace
.image
);
3512 command_print(cmd_ctx
, "previously loaded image found and closed");
3515 xscale
->trace
.image
= malloc(sizeof(image_t
));
3516 xscale
->trace
.image
->base_address_set
= 0;
3517 xscale
->trace
.image
->start_address_set
= 0;
3519 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3522 xscale
->trace
.image
->base_address_set
= 1;
3523 xscale
->trace
.image
->base_address
= strtoul(args
[1], NULL
, 0);
3527 xscale
->trace
.image
->base_address_set
= 0;
3530 if (image_open(xscale
->trace
.image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
3532 free(xscale
->trace
.image
);
3533 xscale
->trace
.image
= NULL
;
3540 int xscale_handle_dump_trace_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3542 target_t
*target
= get_current_target(cmd_ctx
);
3543 armv4_5_common_t
*armv4_5
;
3544 xscale_common_t
*xscale
;
3545 xscale_trace_data_t
*trace_data
;
3548 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3553 if (target
->state
!= TARGET_HALTED
)
3555 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3561 command_print(cmd_ctx
, "usage: xscale dump_trace <file>");
3565 trace_data
= xscale
->trace
.data
;
3569 command_print(cmd_ctx
, "no trace data collected");
3573 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3582 fileio_write_u32(&file
, trace_data
->chkpt0
);
3583 fileio_write_u32(&file
, trace_data
->chkpt1
);
3584 fileio_write_u32(&file
, trace_data
->last_instruction
);
3585 fileio_write_u32(&file
, trace_data
->depth
);
3587 for (i
= 0; i
< trace_data
->depth
; i
++)
3588 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3590 trace_data
= trace_data
->next
;
3593 fileio_close(&file
);
3598 int xscale_handle_analyze_trace_buffer_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3600 target_t
*target
= get_current_target(cmd_ctx
);
3601 armv4_5_common_t
*armv4_5
;
3602 xscale_common_t
*xscale
;
3604 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3609 xscale_analyze_trace(target
, cmd_ctx
);
3614 int xscale_handle_cp15(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3616 target_t
*target
= get_current_target(cmd_ctx
);
3617 armv4_5_common_t
*armv4_5
;
3618 xscale_common_t
*xscale
;
3620 if (xscale_get_arch_pointers(target
, &armv4_5
, &xscale
) != ERROR_OK
)
3625 if (target
->state
!= TARGET_HALTED
)
3627 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
3634 reg_no
= strtoul(args
[0], NULL
, 0);
3635 /*translate from xscale cp15 register no to openocd register*/
3639 reg_no
= XSCALE_MAINID
;
3642 reg_no
= XSCALE_CTRL
;
3645 reg_no
= XSCALE_TTB
;
3648 reg_no
= XSCALE_DAC
;
3651 reg_no
= XSCALE_FSR
;
3654 reg_no
= XSCALE_FAR
;
3657 reg_no
= XSCALE_PID
;
3660 reg_no
= XSCALE_CPACCESS
;
3663 command_print(cmd_ctx
, "invalid register number");
3664 return ERROR_INVALID_ARGUMENTS
;
3666 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3673 /* read cp15 control register */
3674 xscale_get_reg(reg
);
3675 value
= buf_get_u32(reg
->value
, 0, 32);
3676 command_print(cmd_ctx
, "%s (/%i): 0x%x", reg
->name
, reg
->size
, value
);
3681 u32 value
= strtoul(args
[1], NULL
, 0);
3683 /* send CP write request (command 0x41) */
3684 xscale_send_u32(target
, 0x41);
3686 /* send CP register number */
3687 xscale_send_u32(target
, reg_no
);
3689 /* send CP register value */
3690 xscale_send_u32(target
, value
);
3692 /* execute cpwait to ensure outstanding operations complete */
3693 xscale_send_u32(target
, 0x53);
3697 command_print(cmd_ctx
, "usage: cp15 [register]<, [value]>");
3703 int xscale_register_commands(struct command_context_s
*cmd_ctx
)
3705 command_t
*xscale_cmd
;
3707 xscale_cmd
= register_command(cmd_ctx
, NULL
, "xscale", NULL
, COMMAND_ANY
, "xscale specific commands");
3709 register_command(cmd_ctx
, xscale_cmd
, "debug_handler", xscale_handle_debug_handler_command
, COMMAND_ANY
, "'xscale debug_handler <target#> <address>' command takes two required operands");
3710 register_command(cmd_ctx
, xscale_cmd
, "cache_clean_address", xscale_handle_cache_clean_address_command
, COMMAND_ANY
, NULL
);
3712 register_command(cmd_ctx
, xscale_cmd
, "cache_info", xscale_handle_cache_info_command
, COMMAND_EXEC
, NULL
);
3713 register_command(cmd_ctx
, xscale_cmd
, "mmu", xscale_handle_mmu_command
, COMMAND_EXEC
, "['enable'|'disable'] the MMU");
3714 register_command(cmd_ctx
, xscale_cmd
, "icache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the ICache");
3715 register_command(cmd_ctx
, xscale_cmd
, "dcache", xscale_handle_idcache_command
, COMMAND_EXEC
, "['enable'|'disable'] the DCache");
3717 register_command(cmd_ctx
, xscale_cmd
, "vector_catch", xscale_handle_idcache_command
, COMMAND_EXEC
, "<mask> of vectors that should be catched");
3719 register_command(cmd_ctx
, xscale_cmd
, "trace_buffer", xscale_handle_trace_buffer_command
, COMMAND_EXEC
, "<enable|disable> ['fill' [n]|'wrap']");
3721 register_command(cmd_ctx
, xscale_cmd
, "dump_trace", xscale_handle_dump_trace_command
, COMMAND_EXEC
, "dump content of trace buffer to <file>");
3722 register_command(cmd_ctx
, xscale_cmd
, "analyze_trace", xscale_handle_analyze_trace_buffer_command
, COMMAND_EXEC
, "analyze content of trace buffer");
3723 register_command(cmd_ctx
, xscale_cmd
, "trace_image", xscale_handle_trace_image_command
,
3724 COMMAND_EXEC
, "load image from <file> [base address]");
3726 register_command(cmd_ctx
, xscale_cmd
, "cp15", xscale_handle_cp15
, COMMAND_EXEC
, "access coproc 15 <register> [value]");
3728 armv4_5_register_commands(cmd_ctx
);
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