1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2009 Michael Schwingen *
9 * michael@schwingen.org *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
30 #include "breakpoints.h"
32 #include "target_type.h"
34 #include "arm_simulator.h"
35 #include "arm_disassembler.h"
36 #include "time_support.h"
42 * Important XScale documents available as of October 2009 include:
44 * Intel XScale® Core Developer’s Manual, January 2004
45 * Order Number: 273473-002
46 * This has a chapter detailing debug facilities, and punts some
47 * details to chip-specific microarchitecture documents.
49 * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
50 * Document Number: 273539-005
51 * Less detailed than the developer's manual, but summarizes those
52 * missing details (for most XScales) and gives LOTS of notes about
53 * debugger/handler interaction issues. Presents a simpler reset
54 * and load-handler sequence than the arch doc. (Note, OpenOCD
55 * doesn't currently support "Hot-Debug" as defined there.)
57 * Chip-specific microarchitecture documents may also be useful.
61 /* forward declarations */
62 static int xscale_resume(struct target
*, int current
,
63 uint32_t address
, int handle_breakpoints
, int debug_execution
);
64 static int xscale_debug_entry(struct target
*);
65 static int xscale_restore_context(struct target
*);
66 static int xscale_get_reg(struct reg
*reg
);
67 static int xscale_set_reg(struct reg
*reg
, uint8_t *buf
);
68 static int xscale_set_breakpoint(struct target
*, struct breakpoint
*);
69 static int xscale_set_watchpoint(struct target
*, struct watchpoint
*);
70 static int xscale_unset_breakpoint(struct target
*, struct breakpoint
*);
71 static int xscale_read_trace(struct target
*);
74 /* This XScale "debug handler" is loaded into the processor's
75 * mini-ICache, which is 2K of code writable only via JTAG.
77 * FIXME the OpenOCD "bin2char" utility currently doesn't handle
78 * binary files cleanly. It's string oriented, and terminates them
79 * with a NUL character. Better would be to generate the constants
80 * and let other code decide names, scoping, and other housekeeping.
82 static /* unsigned const char xscale_debug_handler[] = ... */
83 #include "xscale_debug.h"
85 static char *const xscale_reg_list
[] =
87 "XSCALE_MAINID", /* 0 */
97 "XSCALE_IBCR0", /* 10 */
107 "XSCALE_RX", /* 20 */
111 static const struct xscale_reg xscale_reg_arch_info
[] =
113 {XSCALE_MAINID
, NULL
},
114 {XSCALE_CACHETYPE
, NULL
},
116 {XSCALE_AUXCTRL
, NULL
},
122 {XSCALE_CPACCESS
, NULL
},
123 {XSCALE_IBCR0
, NULL
},
124 {XSCALE_IBCR1
, NULL
},
127 {XSCALE_DBCON
, NULL
},
128 {XSCALE_TBREG
, NULL
},
129 {XSCALE_CHKPT0
, NULL
},
130 {XSCALE_CHKPT1
, NULL
},
131 {XSCALE_DCSR
, NULL
}, /* DCSR accessed via JTAG or SW */
132 {-1, NULL
}, /* TX accessed via JTAG */
133 {-1, NULL
}, /* RX accessed via JTAG */
134 {-1, NULL
}, /* TXRXCTRL implicit access via JTAG */
137 /* convenience wrapper to access XScale specific registers */
138 static int xscale_set_reg_u32(struct reg
*reg
, uint32_t value
)
142 buf_set_u32(buf
, 0, 32, value
);
144 return xscale_set_reg(reg
, buf
);
147 static const char xscale_not
[] = "target is not an XScale";
149 static int xscale_verify_pointer(struct command_context
*cmd_ctx
,
150 struct xscale_common
*xscale
)
152 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
) {
153 command_print(cmd_ctx
, xscale_not
);
154 return ERROR_TARGET_INVALID
;
159 static int xscale_jtag_set_instr(struct jtag_tap
*tap
, uint32_t new_instr
)
164 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
166 struct scan_field field
;
169 memset(&field
, 0, sizeof field
);
171 field
.num_bits
= tap
->ir_length
;
172 field
.out_value
= scratch
;
173 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
175 jtag_add_ir_scan(1, &field
, jtag_get_end_state());
181 static int xscale_read_dcsr(struct target
*target
)
183 struct xscale_common
*xscale
= target_to_xscale(target
);
185 struct scan_field fields
[3];
186 uint8_t field0
= 0x0;
187 uint8_t field0_check_value
= 0x2;
188 uint8_t field0_check_mask
= 0x7;
189 uint8_t field2
= 0x0;
190 uint8_t field2_check_value
= 0x0;
191 uint8_t field2_check_mask
= 0x1;
193 jtag_set_end_state(TAP_DRPAUSE
);
194 xscale_jtag_set_instr(target
->tap
,
195 XSCALE_SELDCSR
<< xscale
->xscale_variant
);
197 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
198 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
200 memset(&fields
, 0, sizeof fields
);
202 fields
[0].tap
= target
->tap
;
203 fields
[0].num_bits
= 3;
204 fields
[0].out_value
= &field0
;
206 fields
[0].in_value
= &tmp
;
208 fields
[1].tap
= target
->tap
;
209 fields
[1].num_bits
= 32;
210 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
212 fields
[2].tap
= target
->tap
;
213 fields
[2].num_bits
= 1;
214 fields
[2].out_value
= &field2
;
216 fields
[2].in_value
= &tmp2
;
218 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
220 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
221 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
223 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
225 LOG_ERROR("JTAG error while reading DCSR");
229 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
230 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
232 /* write the register with the value we just read
233 * on this second pass, only the first bit of field0 is guaranteed to be 0)
235 field0_check_mask
= 0x1;
236 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
237 fields
[1].in_value
= NULL
;
239 jtag_set_end_state(TAP_IDLE
);
241 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
243 /* DANGER!!! this must be here. It will make sure that the arguments
244 * to jtag_set_check_value() does not go out of scope! */
245 return jtag_execute_queue();
249 static void xscale_getbuf(jtag_callback_data_t arg
)
251 uint8_t *in
= (uint8_t *)arg
;
252 *((uint32_t *)in
) = buf_get_u32(in
, 0, 32);
255 static int xscale_receive(struct target
*target
, uint32_t *buffer
, int num_words
)
258 return ERROR_INVALID_ARGUMENTS
;
260 struct xscale_common
*xscale
= target_to_xscale(target
);
261 int retval
= ERROR_OK
;
263 struct scan_field fields
[3];
264 uint8_t *field0
= malloc(num_words
* 1);
265 uint8_t field0_check_value
= 0x2;
266 uint8_t field0_check_mask
= 0x6;
267 uint32_t *field1
= malloc(num_words
* 4);
268 uint8_t field2_check_value
= 0x0;
269 uint8_t field2_check_mask
= 0x1;
271 int words_scheduled
= 0;
274 path
[0] = TAP_DRSELECT
;
275 path
[1] = TAP_DRCAPTURE
;
276 path
[2] = TAP_DRSHIFT
;
278 memset(&fields
, 0, sizeof fields
);
280 fields
[0].tap
= target
->tap
;
281 fields
[0].num_bits
= 3;
282 fields
[0].check_value
= &field0_check_value
;
283 fields
[0].check_mask
= &field0_check_mask
;
285 fields
[1].tap
= target
->tap
;
286 fields
[1].num_bits
= 32;
288 fields
[2].tap
= target
->tap
;
289 fields
[2].num_bits
= 1;
290 fields
[2].check_value
= &field2_check_value
;
291 fields
[2].check_mask
= &field2_check_mask
;
293 jtag_set_end_state(TAP_IDLE
);
294 xscale_jtag_set_instr(target
->tap
,
295 XSCALE_DBGTX
<< xscale
->xscale_variant
);
296 jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
298 /* repeat until all words have been collected */
300 while (words_done
< num_words
)
304 for (i
= words_done
; i
< num_words
; i
++)
306 fields
[0].in_value
= &field0
[i
];
308 jtag_add_pathmove(3, path
);
310 fields
[1].in_value
= (uint8_t *)(field1
+ i
);
312 jtag_add_dr_scan_check(3, fields
, jtag_set_end_state(TAP_IDLE
));
314 jtag_add_callback(xscale_getbuf
, (jtag_callback_data_t
)(field1
+ i
));
319 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
321 LOG_ERROR("JTAG error while receiving data from debug handler");
325 /* examine results */
326 for (i
= words_done
; i
< num_words
; i
++)
328 if (!(field0
[0] & 1))
330 /* move backwards if necessary */
332 for (j
= i
; j
< num_words
- 1; j
++)
334 field0
[j
] = field0
[j
+ 1];
335 field1
[j
] = field1
[j
+ 1];
340 if (words_scheduled
== 0)
342 if (attempts
++==1000)
344 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
345 retval
= ERROR_TARGET_TIMEOUT
;
350 words_done
+= words_scheduled
;
353 for (i
= 0; i
< num_words
; i
++)
354 *(buffer
++) = buf_get_u32((uint8_t*)&field1
[i
], 0, 32);
361 static int xscale_read_tx(struct target
*target
, int consume
)
363 struct xscale_common
*xscale
= target_to_xscale(target
);
365 tap_state_t noconsume_path
[6];
367 struct timeval timeout
, now
;
368 struct scan_field fields
[3];
369 uint8_t field0_in
= 0x0;
370 uint8_t field0_check_value
= 0x2;
371 uint8_t field0_check_mask
= 0x6;
372 uint8_t field2_check_value
= 0x0;
373 uint8_t field2_check_mask
= 0x1;
375 jtag_set_end_state(TAP_IDLE
);
377 xscale_jtag_set_instr(target
->tap
,
378 XSCALE_DBGTX
<< xscale
->xscale_variant
);
380 path
[0] = TAP_DRSELECT
;
381 path
[1] = TAP_DRCAPTURE
;
382 path
[2] = TAP_DRSHIFT
;
384 noconsume_path
[0] = TAP_DRSELECT
;
385 noconsume_path
[1] = TAP_DRCAPTURE
;
386 noconsume_path
[2] = TAP_DREXIT1
;
387 noconsume_path
[3] = TAP_DRPAUSE
;
388 noconsume_path
[4] = TAP_DREXIT2
;
389 noconsume_path
[5] = TAP_DRSHIFT
;
391 memset(&fields
, 0, sizeof fields
);
393 fields
[0].tap
= target
->tap
;
394 fields
[0].num_bits
= 3;
395 fields
[0].in_value
= &field0_in
;
397 fields
[1].tap
= target
->tap
;
398 fields
[1].num_bits
= 32;
399 fields
[1].in_value
= xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
;
401 fields
[2].tap
= target
->tap
;
402 fields
[2].num_bits
= 1;
404 fields
[2].in_value
= &tmp
;
406 gettimeofday(&timeout
, NULL
);
407 timeval_add_time(&timeout
, 1, 0);
411 /* if we want to consume the register content (i.e. clear TX_READY),
412 * we have to go straight from Capture-DR to Shift-DR
413 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
416 jtag_add_pathmove(3, path
);
419 jtag_add_pathmove(ARRAY_SIZE(noconsume_path
), noconsume_path
);
422 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
424 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
425 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
427 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
429 LOG_ERROR("JTAG error while reading TX");
430 return ERROR_TARGET_TIMEOUT
;
433 gettimeofday(&now
, NULL
);
434 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
436 LOG_ERROR("time out reading TX register");
437 return ERROR_TARGET_TIMEOUT
;
439 if (!((!(field0_in
& 1)) && consume
))
443 if (debug_level
>= 3)
445 LOG_DEBUG("waiting 100ms");
446 alive_sleep(100); /* avoid flooding the logs */
454 if (!(field0_in
& 1))
455 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
460 static int xscale_write_rx(struct target
*target
)
462 struct xscale_common
*xscale
= target_to_xscale(target
);
464 struct timeval timeout
, now
;
465 struct scan_field fields
[3];
466 uint8_t field0_out
= 0x0;
467 uint8_t field0_in
= 0x0;
468 uint8_t field0_check_value
= 0x2;
469 uint8_t field0_check_mask
= 0x6;
470 uint8_t field2
= 0x0;
471 uint8_t field2_check_value
= 0x0;
472 uint8_t field2_check_mask
= 0x1;
474 jtag_set_end_state(TAP_IDLE
);
476 xscale_jtag_set_instr(target
->tap
,
477 XSCALE_DBGRX
<< xscale
->xscale_variant
);
479 memset(&fields
, 0, sizeof fields
);
481 fields
[0].tap
= target
->tap
;
482 fields
[0].num_bits
= 3;
483 fields
[0].out_value
= &field0_out
;
484 fields
[0].in_value
= &field0_in
;
486 fields
[1].tap
= target
->tap
;
487 fields
[1].num_bits
= 32;
488 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
;
490 fields
[2].tap
= target
->tap
;
491 fields
[2].num_bits
= 1;
492 fields
[2].out_value
= &field2
;
494 fields
[2].in_value
= &tmp
;
496 gettimeofday(&timeout
, NULL
);
497 timeval_add_time(&timeout
, 1, 0);
499 /* poll until rx_read is low */
500 LOG_DEBUG("polling RX");
503 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
505 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
506 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
508 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
510 LOG_ERROR("JTAG error while writing RX");
514 gettimeofday(&now
, NULL
);
515 if ((now
.tv_sec
> timeout
.tv_sec
) || ((now
.tv_sec
== timeout
.tv_sec
)&& (now
.tv_usec
> timeout
.tv_usec
)))
517 LOG_ERROR("time out writing RX register");
518 return ERROR_TARGET_TIMEOUT
;
520 if (!(field0_in
& 1))
522 if (debug_level
>= 3)
524 LOG_DEBUG("waiting 100ms");
525 alive_sleep(100); /* avoid flooding the logs */
535 jtag_add_dr_scan(3, fields
, jtag_set_end_state(TAP_IDLE
));
537 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
539 LOG_ERROR("JTAG error while writing RX");
546 /* send count elements of size byte to the debug handler */
547 static int xscale_send(struct target
*target
, uint8_t *buffer
, int count
, int size
)
549 struct xscale_common
*xscale
= target_to_xscale(target
);
555 jtag_set_end_state(TAP_IDLE
);
557 xscale_jtag_set_instr(target
->tap
,
558 XSCALE_DBGRX
<< xscale
->xscale_variant
);
565 int endianness
= target
->endianness
;
566 while (done_count
++ < count
)
571 if (endianness
== TARGET_LITTLE_ENDIAN
)
573 t
[1]=le_to_h_u32(buffer
);
576 t
[1]=be_to_h_u32(buffer
);
580 if (endianness
== TARGET_LITTLE_ENDIAN
)
582 t
[1]=le_to_h_u16(buffer
);
585 t
[1]=be_to_h_u16(buffer
);
592 LOG_ERROR("BUG: size neither 4, 2 nor 1");
593 return ERROR_INVALID_ARGUMENTS
;
595 jtag_add_dr_out(target
->tap
,
599 jtag_set_end_state(TAP_IDLE
));
603 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
605 LOG_ERROR("JTAG error while sending data to debug handler");
612 static int xscale_send_u32(struct target
*target
, uint32_t value
)
614 struct xscale_common
*xscale
= target_to_xscale(target
);
616 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
617 return xscale_write_rx(target
);
620 static int xscale_write_dcsr(struct target
*target
, int hold_rst
, int ext_dbg_brk
)
622 struct xscale_common
*xscale
= target_to_xscale(target
);
624 struct scan_field fields
[3];
625 uint8_t field0
= 0x0;
626 uint8_t field0_check_value
= 0x2;
627 uint8_t field0_check_mask
= 0x7;
628 uint8_t field2
= 0x0;
629 uint8_t field2_check_value
= 0x0;
630 uint8_t field2_check_mask
= 0x1;
633 xscale
->hold_rst
= hold_rst
;
635 if (ext_dbg_brk
!= -1)
636 xscale
->external_debug_break
= ext_dbg_brk
;
638 jtag_set_end_state(TAP_IDLE
);
639 xscale_jtag_set_instr(target
->tap
,
640 XSCALE_SELDCSR
<< xscale
->xscale_variant
);
642 buf_set_u32(&field0
, 1, 1, xscale
->hold_rst
);
643 buf_set_u32(&field0
, 2, 1, xscale
->external_debug_break
);
645 memset(&fields
, 0, sizeof fields
);
647 fields
[0].tap
= target
->tap
;
648 fields
[0].num_bits
= 3;
649 fields
[0].out_value
= &field0
;
651 fields
[0].in_value
= &tmp
;
653 fields
[1].tap
= target
->tap
;
654 fields
[1].num_bits
= 32;
655 fields
[1].out_value
= xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
;
657 fields
[2].tap
= target
->tap
;
658 fields
[2].num_bits
= 1;
659 fields
[2].out_value
= &field2
;
661 fields
[2].in_value
= &tmp2
;
663 jtag_add_dr_scan(3, fields
, jtag_get_end_state());
665 jtag_check_value_mask(fields
+ 0, &field0_check_value
, &field0_check_mask
);
666 jtag_check_value_mask(fields
+ 2, &field2_check_value
, &field2_check_mask
);
668 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
670 LOG_ERROR("JTAG error while writing DCSR");
674 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].dirty
= 0;
675 xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].valid
= 1;
680 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
681 static unsigned int parity (unsigned int v
)
683 // unsigned int ov = v;
688 // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
689 return (0x6996 >> v
) & 1;
692 static int xscale_load_ic(struct target
*target
, uint32_t va
, uint32_t buffer
[8])
694 struct xscale_common
*xscale
= target_to_xscale(target
);
698 struct scan_field fields
[2];
700 LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32
"", va
);
703 jtag_set_end_state(TAP_IDLE
);
704 xscale_jtag_set_instr(target
->tap
,
705 XSCALE_LDIC
<< xscale
->xscale_variant
);
707 /* CMD is b011 to load a cacheline into the Mini ICache.
708 * Loading into the main ICache is deprecated, and unused.
709 * It's followed by three zero bits, and 27 address bits.
711 buf_set_u32(&cmd
, 0, 6, 0x3);
713 /* virtual address of desired cache line */
714 buf_set_u32(packet
, 0, 27, va
>> 5);
716 memset(&fields
, 0, sizeof fields
);
718 fields
[0].tap
= target
->tap
;
719 fields
[0].num_bits
= 6;
720 fields
[0].out_value
= &cmd
;
722 fields
[1].tap
= target
->tap
;
723 fields
[1].num_bits
= 27;
724 fields
[1].out_value
= packet
;
726 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
728 /* rest of packet is a cacheline: 8 instructions, with parity */
729 fields
[0].num_bits
= 32;
730 fields
[0].out_value
= packet
;
732 fields
[1].num_bits
= 1;
733 fields
[1].out_value
= &cmd
;
735 for (word
= 0; word
< 8; word
++)
737 buf_set_u32(packet
, 0, 32, buffer
[word
]);
740 memcpy(&value
, packet
, sizeof(uint32_t));
743 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
746 return jtag_execute_queue();
749 static int xscale_invalidate_ic_line(struct target
*target
, uint32_t va
)
751 struct xscale_common
*xscale
= target_to_xscale(target
);
754 struct scan_field fields
[2];
756 jtag_set_end_state(TAP_IDLE
);
757 xscale_jtag_set_instr(target
->tap
,
758 XSCALE_LDIC
<< xscale
->xscale_variant
);
760 /* CMD for invalidate IC line b000, bits [6:4] b000 */
761 buf_set_u32(&cmd
, 0, 6, 0x0);
763 /* virtual address of desired cache line */
764 buf_set_u32(packet
, 0, 27, va
>> 5);
766 memset(&fields
, 0, sizeof fields
);
768 fields
[0].tap
= target
->tap
;
769 fields
[0].num_bits
= 6;
770 fields
[0].out_value
= &cmd
;
772 fields
[1].tap
= target
->tap
;
773 fields
[1].num_bits
= 27;
774 fields
[1].out_value
= packet
;
776 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
781 static int xscale_update_vectors(struct target
*target
)
783 struct xscale_common
*xscale
= target_to_xscale(target
);
787 uint32_t low_reset_branch
, high_reset_branch
;
789 for (i
= 1; i
< 8; i
++)
791 /* if there's a static vector specified for this exception, override */
792 if (xscale
->static_high_vectors_set
& (1 << i
))
794 xscale
->high_vectors
[i
] = xscale
->static_high_vectors
[i
];
798 retval
= target_read_u32(target
, 0xffff0000 + 4*i
, &xscale
->high_vectors
[i
]);
799 if (retval
== ERROR_TARGET_TIMEOUT
)
801 if (retval
!= ERROR_OK
)
803 /* Some of these reads will fail as part of normal execution */
804 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
809 for (i
= 1; i
< 8; i
++)
811 if (xscale
->static_low_vectors_set
& (1 << i
))
813 xscale
->low_vectors
[i
] = xscale
->static_low_vectors
[i
];
817 retval
= target_read_u32(target
, 0x0 + 4*i
, &xscale
->low_vectors
[i
]);
818 if (retval
== ERROR_TARGET_TIMEOUT
)
820 if (retval
!= ERROR_OK
)
822 /* Some of these reads will fail as part of normal execution */
823 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
828 /* calculate branches to debug handler */
829 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
830 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
832 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
833 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
835 /* invalidate and load exception vectors in mini i-cache */
836 xscale_invalidate_ic_line(target
, 0x0);
837 xscale_invalidate_ic_line(target
, 0xffff0000);
839 xscale_load_ic(target
, 0x0, xscale
->low_vectors
);
840 xscale_load_ic(target
, 0xffff0000, xscale
->high_vectors
);
845 static int xscale_arch_state(struct target
*target
)
847 struct xscale_common
*xscale
= target_to_xscale(target
);
848 struct arm
*armv4_5
= &xscale
->armv4_5_common
;
850 static const char *state
[] =
852 "disabled", "enabled"
855 static const char *arch_dbg_reason
[] =
857 "", "\n(processor reset)", "\n(trace buffer full)"
860 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
862 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
863 return ERROR_INVALID_ARGUMENTS
;
866 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
867 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
868 "MMU: %s, D-Cache: %s, I-Cache: %s"
870 armv4_5_state_strings
[armv4_5
->core_state
],
871 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
872 arm_mode_name(armv4_5
->core_mode
),
873 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32),
874 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
875 state
[xscale
->armv4_5_mmu
.mmu_enabled
],
876 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
877 state
[xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
],
878 arch_dbg_reason
[xscale
->arch_debug_reason
]);
883 static int xscale_poll(struct target
*target
)
885 int retval
= ERROR_OK
;
887 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_DEBUG_RUNNING
))
889 enum target_state previous_state
= target
->state
;
890 if ((retval
= xscale_read_tx(target
, 0)) == ERROR_OK
)
893 /* there's data to read from the tx register, we entered debug state */
894 target
->state
= TARGET_HALTED
;
896 /* process debug entry, fetching current mode regs */
897 retval
= xscale_debug_entry(target
);
899 else if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
901 LOG_USER("error while polling TX register, reset CPU");
902 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
903 target
->state
= TARGET_HALTED
;
906 /* debug_entry could have overwritten target state (i.e. immediate resume)
907 * don't signal event handlers in that case
909 if (target
->state
!= TARGET_HALTED
)
912 /* if target was running, signal that we halted
913 * otherwise we reentered from debug execution */
914 if (previous_state
== TARGET_RUNNING
)
915 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
917 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
923 static int xscale_debug_entry(struct target
*target
)
925 struct xscale_common
*xscale
= target_to_xscale(target
);
926 struct arm
*armv4_5
= &xscale
->armv4_5_common
;
933 /* clear external dbg break (will be written on next DCSR read) */
934 xscale
->external_debug_break
= 0;
935 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
938 /* get r0, pc, r1 to r7 and cpsr */
939 if ((retval
= xscale_receive(target
, buffer
, 10)) != ERROR_OK
)
942 /* move r0 from buffer to register cache */
943 buf_set_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32, buffer
[0]);
944 armv4_5
->core_cache
->reg_list
[0].dirty
= 1;
945 armv4_5
->core_cache
->reg_list
[0].valid
= 1;
946 LOG_DEBUG("r0: 0x%8.8" PRIx32
"", buffer
[0]);
948 /* move pc from buffer to register cache */
949 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, buffer
[1]);
950 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
951 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
952 LOG_DEBUG("pc: 0x%8.8" PRIx32
"", buffer
[1]);
954 /* move data from buffer to register cache */
955 for (i
= 1; i
<= 7; i
++)
957 buf_set_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32, buffer
[1 + i
]);
958 armv4_5
->core_cache
->reg_list
[i
].dirty
= 1;
959 armv4_5
->core_cache
->reg_list
[i
].valid
= 1;
960 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, buffer
[i
+ 1]);
963 arm_set_cpsr(armv4_5
, buffer
[9]);
964 LOG_DEBUG("cpsr: 0x%8.8" PRIx32
"", buffer
[9]);
966 if (!is_arm_mode(armv4_5
->core_mode
))
968 target
->state
= TARGET_UNKNOWN
;
969 LOG_ERROR("cpsr contains invalid mode value - communication failure");
970 return ERROR_TARGET_FAILURE
;
972 LOG_DEBUG("target entered debug state in %s mode",
973 arm_mode_name(armv4_5
->core_mode
));
975 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
977 xscale_receive(target
, buffer
, 8);
978 buf_set_u32(armv4_5
->spsr
->value
, 0, 32, buffer
[7]);
979 armv4_5
->spsr
->dirty
= false;
980 armv4_5
->spsr
->valid
= true;
984 /* r8 to r14, but no spsr */
985 xscale_receive(target
, buffer
, 7);
988 /* move data from buffer to right banked register in cache */
989 for (i
= 8; i
<= 14; i
++)
991 struct reg
*r
= arm_reg_current(armv4_5
, i
);
993 buf_set_u32(r
->value
, 0, 32, buffer
[i
- 8]);
998 /* examine debug reason */
999 xscale_read_dcsr(target
);
1000 moe
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 2, 3);
1002 /* stored PC (for calculating fixup) */
1003 pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1007 case 0x0: /* Processor reset */
1008 target
->debug_reason
= DBG_REASON_DBGRQ
;
1009 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_RESET
;
1012 case 0x1: /* Instruction breakpoint hit */
1013 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1014 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1017 case 0x2: /* Data breakpoint hit */
1018 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1019 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1022 case 0x3: /* BKPT instruction executed */
1023 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1024 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1027 case 0x4: /* Ext. debug event */
1028 target
->debug_reason
= DBG_REASON_DBGRQ
;
1029 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1032 case 0x5: /* Vector trap occured */
1033 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1034 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_GENERIC
;
1037 case 0x6: /* Trace buffer full break */
1038 target
->debug_reason
= DBG_REASON_DBGRQ
;
1039 xscale
->arch_debug_reason
= XSCALE_DBG_REASON_TB_FULL
;
1042 case 0x7: /* Reserved (may flag Hot-Debug support) */
1044 LOG_ERROR("Method of Entry is 'Reserved'");
1049 /* apply PC fixup */
1050 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, pc
);
1052 /* on the first debug entry, identify cache type */
1053 if (xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
1055 uint32_t cache_type_reg
;
1057 /* read cp15 cache type register */
1058 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
]);
1059 cache_type_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CACHETYPE
].value
, 0, 32);
1061 armv4_5_identify_cache(cache_type_reg
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
1064 /* examine MMU and Cache settings */
1065 /* read cp15 control register */
1066 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
1067 xscale
->cp15_control_reg
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
1068 xscale
->armv4_5_mmu
.mmu_enabled
= (xscale
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1069 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (xscale
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1070 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (xscale
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1072 /* tracing enabled, read collected trace data */
1073 if (xscale
->trace
.buffer_enabled
)
1075 xscale_read_trace(target
);
1076 xscale
->trace
.buffer_fill
--;
1078 /* resume if we're still collecting trace data */
1079 if ((xscale
->arch_debug_reason
== XSCALE_DBG_REASON_TB_FULL
)
1080 && (xscale
->trace
.buffer_fill
> 0))
1082 xscale_resume(target
, 1, 0x0, 1, 0);
1086 xscale
->trace
.buffer_enabled
= 0;
1093 static int xscale_halt(struct target
*target
)
1095 struct xscale_common
*xscale
= target_to_xscale(target
);
1097 LOG_DEBUG("target->state: %s",
1098 target_state_name(target
));
1100 if (target
->state
== TARGET_HALTED
)
1102 LOG_DEBUG("target was already halted");
1105 else if (target
->state
== TARGET_UNKNOWN
)
1107 /* this must not happen for a xscale target */
1108 LOG_ERROR("target was in unknown state when halt was requested");
1109 return ERROR_TARGET_INVALID
;
1111 else if (target
->state
== TARGET_RESET
)
1113 LOG_DEBUG("target->state == TARGET_RESET");
1117 /* assert external dbg break */
1118 xscale
->external_debug_break
= 1;
1119 xscale_read_dcsr(target
);
1121 target
->debug_reason
= DBG_REASON_DBGRQ
;
1127 static int xscale_enable_single_step(struct target
*target
, uint32_t next_pc
)
1129 struct xscale_common
*xscale
= target_to_xscale(target
);
1130 struct reg
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1133 if (xscale
->ibcr0_used
)
1135 struct breakpoint
*ibcr0_bp
= breakpoint_find(target
, buf_get_u32(ibcr0
->value
, 0, 32) & 0xfffffffe);
1139 xscale_unset_breakpoint(target
, ibcr0_bp
);
1143 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1148 if ((retval
= xscale_set_reg_u32(ibcr0
, next_pc
| 0x1)) != ERROR_OK
)
1154 static int xscale_disable_single_step(struct target
*target
)
1156 struct xscale_common
*xscale
= target_to_xscale(target
);
1157 struct reg
*ibcr0
= &xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
];
1160 if ((retval
= xscale_set_reg_u32(ibcr0
, 0x0)) != ERROR_OK
)
1166 static void xscale_enable_watchpoints(struct target
*target
)
1168 struct watchpoint
*watchpoint
= target
->watchpoints
;
1172 if (watchpoint
->set
== 0)
1173 xscale_set_watchpoint(target
, watchpoint
);
1174 watchpoint
= watchpoint
->next
;
1178 static void xscale_enable_breakpoints(struct target
*target
)
1180 struct breakpoint
*breakpoint
= target
->breakpoints
;
1182 /* set any pending breakpoints */
1185 if (breakpoint
->set
== 0)
1186 xscale_set_breakpoint(target
, breakpoint
);
1187 breakpoint
= breakpoint
->next
;
1191 static int xscale_resume(struct target
*target
, int current
,
1192 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1194 struct xscale_common
*xscale
= target_to_xscale(target
);
1195 struct arm
*armv4_5
= &xscale
->armv4_5_common
;
1196 struct breakpoint
*breakpoint
= target
->breakpoints
;
1197 uint32_t current_pc
;
1203 if (target
->state
!= TARGET_HALTED
)
1205 LOG_WARNING("target not halted");
1206 return ERROR_TARGET_NOT_HALTED
;
1209 if (!debug_execution
)
1211 target_free_all_working_areas(target
);
1214 /* update vector tables */
1215 if ((retval
= xscale_update_vectors(target
)) != ERROR_OK
)
1218 /* current = 1: continue on current pc, otherwise continue at <address> */
1220 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1222 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1224 /* if we're at the reset vector, we have to simulate the branch */
1225 if (current_pc
== 0x0)
1227 arm_simulate_step(target
, NULL
);
1228 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1231 /* the front-end may request us not to handle breakpoints */
1232 if (handle_breakpoints
)
1234 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1238 /* there's a breakpoint at the current PC, we have to step over it */
1239 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1240 xscale_unset_breakpoint(target
, breakpoint
);
1242 /* calculate PC of next instruction */
1243 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1245 uint32_t current_opcode
;
1246 target_read_u32(target
, current_pc
, ¤t_opcode
);
1247 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1250 LOG_DEBUG("enable single-step");
1251 xscale_enable_single_step(target
, next_pc
);
1253 /* restore banked registers */
1254 xscale_restore_context(target
);
1256 /* send resume request (command 0x30 or 0x31)
1257 * clean the trace buffer if it is to be enabled (0x62) */
1258 if (xscale
->trace
.buffer_enabled
)
1260 xscale_send_u32(target
, 0x62);
1261 xscale_send_u32(target
, 0x31);
1264 xscale_send_u32(target
, 0x30);
1267 xscale_send_u32(target
,
1268 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32));
1269 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
,
1270 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32));
1272 for (i
= 7; i
>= 0; i
--)
1275 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1276 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1280 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1281 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1283 /* wait for and process debug entry */
1284 xscale_debug_entry(target
);
1286 LOG_DEBUG("disable single-step");
1287 xscale_disable_single_step(target
);
1289 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1290 xscale_set_breakpoint(target
, breakpoint
);
1294 /* enable any pending breakpoints and watchpoints */
1295 xscale_enable_breakpoints(target
);
1296 xscale_enable_watchpoints(target
);
1298 /* restore banked registers */
1299 xscale_restore_context(target
);
1301 /* send resume request (command 0x30 or 0x31)
1302 * clean the trace buffer if it is to be enabled (0x62) */
1303 if (xscale
->trace
.buffer_enabled
)
1305 xscale_send_u32(target
, 0x62);
1306 xscale_send_u32(target
, 0x31);
1309 xscale_send_u32(target
, 0x30);
1312 xscale_send_u32(target
, buf_get_u32(armv4_5
->cpsr
->value
, 0, 32));
1313 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
,
1314 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32));
1316 for (i
= 7; i
>= 0; i
--)
1319 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1320 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1324 xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1325 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1327 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1329 if (!debug_execution
)
1331 /* registers are now invalid */
1332 register_cache_invalidate(armv4_5
->core_cache
);
1333 target
->state
= TARGET_RUNNING
;
1334 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1338 target
->state
= TARGET_DEBUG_RUNNING
;
1339 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1342 LOG_DEBUG("target resumed");
1347 static int xscale_step_inner(struct target
*target
, int current
,
1348 uint32_t address
, int handle_breakpoints
)
1350 struct xscale_common
*xscale
= target_to_xscale(target
);
1351 struct arm
*armv4_5
= &xscale
->armv4_5_common
;
1356 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1358 /* calculate PC of next instruction */
1359 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1361 uint32_t current_opcode
, current_pc
;
1362 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1364 target_read_u32(target
, current_pc
, ¤t_opcode
);
1365 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1369 LOG_DEBUG("enable single-step");
1370 if ((retval
= xscale_enable_single_step(target
, next_pc
)) != ERROR_OK
)
1373 /* restore banked registers */
1374 if ((retval
= xscale_restore_context(target
)) != ERROR_OK
)
1377 /* send resume request (command 0x30 or 0x31)
1378 * clean the trace buffer if it is to be enabled (0x62) */
1379 if (xscale
->trace
.buffer_enabled
)
1381 if ((retval
= xscale_send_u32(target
, 0x62)) != ERROR_OK
)
1383 if ((retval
= xscale_send_u32(target
, 0x31)) != ERROR_OK
)
1387 if ((retval
= xscale_send_u32(target
, 0x30)) != ERROR_OK
)
1391 retval
= xscale_send_u32(target
,
1392 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32));
1393 if (retval
!= ERROR_OK
)
1395 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
,
1396 buf_get_u32(armv4_5
->cpsr
->value
, 0, 32));
1398 for (i
= 7; i
>= 0; i
--)
1401 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32))) != ERROR_OK
)
1403 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(armv4_5
->core_cache
->reg_list
[i
].value
, 0, 32));
1407 if ((retval
= xscale_send_u32(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))) != ERROR_OK
)
1409 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1411 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1413 /* registers are now invalid */
1414 register_cache_invalidate(armv4_5
->core_cache
);
1416 /* wait for and process debug entry */
1417 if ((retval
= xscale_debug_entry(target
)) != ERROR_OK
)
1420 LOG_DEBUG("disable single-step");
1421 if ((retval
= xscale_disable_single_step(target
)) != ERROR_OK
)
1424 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1429 static int xscale_step(struct target
*target
, int current
,
1430 uint32_t address
, int handle_breakpoints
)
1432 struct arm
*armv4_5
= target_to_armv4_5(target
);
1433 struct breakpoint
*breakpoint
= target
->breakpoints
;
1435 uint32_t current_pc
;
1438 if (target
->state
!= TARGET_HALTED
)
1440 LOG_WARNING("target not halted");
1441 return ERROR_TARGET_NOT_HALTED
;
1444 /* current = 1: continue on current pc, otherwise continue at <address> */
1446 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1448 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1450 /* if we're at the reset vector, we have to simulate the step */
1451 if (current_pc
== 0x0)
1453 if ((retval
= arm_simulate_step(target
, NULL
)) != ERROR_OK
)
1455 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1457 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1458 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1463 /* the front-end may request us not to handle breakpoints */
1464 if (handle_breakpoints
)
1465 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1467 if ((retval
= xscale_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1471 retval
= xscale_step_inner(target
, current
, address
, handle_breakpoints
);
1475 xscale_set_breakpoint(target
, breakpoint
);
1478 LOG_DEBUG("target stepped");
1484 static int xscale_assert_reset(struct target
*target
)
1486 struct xscale_common
*xscale
= target_to_xscale(target
);
1488 LOG_DEBUG("target->state: %s",
1489 target_state_name(target
));
1491 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1492 * end up in T-L-R, which would reset JTAG
1494 jtag_set_end_state(TAP_IDLE
);
1495 xscale_jtag_set_instr(target
->tap
,
1496 XSCALE_SELDCSR
<< xscale
->xscale_variant
);
1498 /* set Hold reset, Halt mode and Trap Reset */
1499 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1500 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1501 xscale_write_dcsr(target
, 1, 0);
1503 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1504 xscale_jtag_set_instr(target
->tap
, 0x7f);
1505 jtag_execute_queue();
1508 jtag_add_reset(0, 1);
1510 /* sleep 1ms, to be sure we fulfill any requirements */
1511 jtag_add_sleep(1000);
1512 jtag_execute_queue();
1514 target
->state
= TARGET_RESET
;
1516 if (target
->reset_halt
)
1519 if ((retval
= target_halt(target
)) != ERROR_OK
)
1526 static int xscale_deassert_reset(struct target
*target
)
1528 struct xscale_common
*xscale
= target_to_xscale(target
);
1529 struct breakpoint
*breakpoint
= target
->breakpoints
;
1533 xscale
->ibcr_available
= 2;
1534 xscale
->ibcr0_used
= 0;
1535 xscale
->ibcr1_used
= 0;
1537 xscale
->dbr_available
= 2;
1538 xscale
->dbr0_used
= 0;
1539 xscale
->dbr1_used
= 0;
1541 /* mark all hardware breakpoints as unset */
1544 if (breakpoint
->type
== BKPT_HARD
)
1546 breakpoint
->set
= 0;
1548 breakpoint
= breakpoint
->next
;
1551 register_cache_invalidate(xscale
->armv4_5_common
.core_cache
);
1553 /* FIXME mark hardware watchpoints got unset too. Also,
1554 * at least some of the XScale registers are invalid...
1558 * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
1559 * contents got invalidated. Safer to force that, so writing new
1560 * contents can't ever fail..
1565 const uint8_t *buffer
= xscale_debug_handler
;
1569 jtag_add_reset(0, 0);
1571 /* wait 300ms; 150 and 100ms were not enough */
1572 jtag_add_sleep(300*1000);
1574 jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE
));
1575 jtag_execute_queue();
1577 /* set Hold reset, Halt mode and Trap Reset */
1578 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1579 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1580 xscale_write_dcsr(target
, 1, 0);
1582 /* Load the debug handler into the mini-icache. Since
1583 * it's using halt mode (not monitor mode), it runs in
1584 * "Special Debug State" for access to registers, memory,
1585 * coprocessors, trace data, etc.
1587 address
= xscale
->handler_address
;
1588 for (unsigned binary_size
= sizeof xscale_debug_handler
- 1;
1590 binary_size
-= buf_cnt
, buffer
+= buf_cnt
)
1592 uint32_t cache_line
[8];
1595 buf_cnt
= binary_size
;
1599 for (i
= 0; i
< buf_cnt
; i
+= 4)
1601 /* convert LE buffer to host-endian uint32_t */
1602 cache_line
[i
/ 4] = le_to_h_u32(&buffer
[i
]);
1605 for (; i
< 32; i
+= 4)
1607 cache_line
[i
/ 4] = 0xe1a08008;
1610 /* only load addresses other than the reset vectors */
1611 if ((address
% 0x400) != 0x0)
1613 retval
= xscale_load_ic(target
, address
,
1615 if (retval
!= ERROR_OK
)
1622 retval
= xscale_load_ic(target
, 0x0,
1623 xscale
->low_vectors
);
1624 if (retval
!= ERROR_OK
)
1626 retval
= xscale_load_ic(target
, 0xffff0000,
1627 xscale
->high_vectors
);
1628 if (retval
!= ERROR_OK
)
1631 jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE
));
1633 jtag_add_sleep(100000);
1635 /* set Hold reset, Halt mode and Trap Reset */
1636 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 30, 1, 0x1);
1637 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 1, 0x1);
1638 xscale_write_dcsr(target
, 1, 0);
1640 /* clear Hold reset to let the target run (should enter debug handler) */
1641 xscale_write_dcsr(target
, 0, 1);
1642 target
->state
= TARGET_RUNNING
;
1644 if (!target
->reset_halt
)
1646 jtag_add_sleep(10000);
1648 /* we should have entered debug now */
1649 xscale_debug_entry(target
);
1650 target
->state
= TARGET_HALTED
;
1652 /* resume the target */
1653 xscale_resume(target
, 1, 0x0, 1, 0);
1660 static int xscale_read_core_reg(struct target
*target
, struct reg
*r
,
1661 int num
, enum armv4_5_mode mode
)
1663 /** \todo add debug handler support for core register reads */
1664 LOG_ERROR("not implemented");
1668 static int xscale_write_core_reg(struct target
*target
, struct reg
*r
,
1669 int num
, enum armv4_5_mode mode
, uint32_t value
)
1671 /** \todo add debug handler support for core register writes */
1672 LOG_ERROR("not implemented");
1676 static int xscale_full_context(struct target
*target
)
1678 struct arm
*armv4_5
= target_to_armv4_5(target
);
1686 if (target
->state
!= TARGET_HALTED
)
1688 LOG_WARNING("target not halted");
1689 return ERROR_TARGET_NOT_HALTED
;
1692 buffer
= malloc(4 * 8);
1694 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1695 * we can't enter User mode on an XScale (unpredictable),
1696 * but User shares registers with SYS
1698 for (i
= 1; i
< 7; i
++)
1700 enum armv4_5_mode mode
= armv4_5_number_to_mode(i
);
1704 if (mode
== ARMV4_5_MODE_USR
)
1707 /* check if there are invalid registers in the current mode
1709 for (j
= 0; valid
&& j
<= 16; j
++)
1711 if (!ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
,
1718 /* request banked registers */
1719 xscale_send_u32(target
, 0x0);
1721 /* send CPSR for desired bank mode */
1722 xscale_send_u32(target
, mode
| 0xc0 /* I/F bits */);
1724 /* get banked registers: r8 to r14; and SPSR
1725 * except in USR/SYS mode
1727 if (mode
!= ARMV4_5_MODE_SYS
) {
1729 r
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
,
1732 xscale_receive(target
, buffer
, 8);
1734 buf_set_u32(r
->value
, 0, 32, buffer
[7]);
1738 xscale_receive(target
, buffer
, 7);
1741 /* move data from buffer to register cache */
1742 for (j
= 8; j
<= 14; j
++)
1744 r
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
,
1747 buf_set_u32(r
->value
, 0, 32, buffer
[j
- 8]);
1758 static int xscale_restore_context(struct target
*target
)
1760 struct arm
*armv4_5
= target_to_armv4_5(target
);
1764 if (target
->state
!= TARGET_HALTED
)
1766 LOG_WARNING("target not halted");
1767 return ERROR_TARGET_NOT_HALTED
;
1770 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1771 * we can't enter User mode on an XScale (unpredictable),
1772 * but User shares registers with SYS
1774 for (i
= 1; i
< 7; i
++)
1778 /* check if there are invalid registers in the current mode
1780 for (j
= 8; j
<= 14; j
++)
1782 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
== 1)
1786 /* if not USR/SYS, check if the SPSR needs to be written */
1787 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1789 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
== 1)
1797 /* send banked registers */
1798 xscale_send_u32(target
, 0x1);
1801 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1802 tmp_cpsr
|= 0xc0; /* I/F bits */
1804 /* send CPSR for desired mode */
1805 xscale_send_u32(target
, tmp_cpsr
);
1807 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1808 for (j
= 8; j
<= 14; j
++)
1810 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, j
).value
, 0, 32));
1811 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1814 if ((armv4_5_number_to_mode(i
) != ARMV4_5_MODE_USR
) && (armv4_5_number_to_mode(i
) != ARMV4_5_MODE_SYS
))
1816 xscale_send_u32(target
, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32));
1817 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1825 static int xscale_read_memory(struct target
*target
, uint32_t address
,
1826 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1828 struct xscale_common
*xscale
= target_to_xscale(target
);
1833 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1835 if (target
->state
!= TARGET_HALTED
)
1837 LOG_WARNING("target not halted");
1838 return ERROR_TARGET_NOT_HALTED
;
1841 /* sanitize arguments */
1842 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1843 return ERROR_INVALID_ARGUMENTS
;
1845 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1846 return ERROR_TARGET_UNALIGNED_ACCESS
;
1848 /* send memory read request (command 0x1n, n: access size) */
1849 if ((retval
= xscale_send_u32(target
, 0x10 | size
)) != ERROR_OK
)
1852 /* send base address for read request */
1853 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1856 /* send number of requested data words */
1857 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1860 /* receive data from target (count times 32-bit words in host endianness) */
1861 buf32
= malloc(4 * count
);
1862 if ((retval
= xscale_receive(target
, buf32
, count
)) != ERROR_OK
)
1865 /* extract data from host-endian buffer into byte stream */
1866 for (i
= 0; i
< count
; i
++)
1871 target_buffer_set_u32(target
, buffer
, buf32
[i
]);
1875 target_buffer_set_u16(target
, buffer
, buf32
[i
] & 0xffff);
1879 *buffer
++ = buf32
[i
] & 0xff;
1882 LOG_ERROR("invalid read size");
1883 return ERROR_INVALID_ARGUMENTS
;
1889 /* examine DCSR, to see if Sticky Abort (SA) got set */
1890 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1892 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1895 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
1898 return ERROR_TARGET_DATA_ABORT
;
1904 static int xscale_read_phys_memory(struct target
*target
, uint32_t address
,
1905 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1907 /** \todo: provide a non-stub implementtion of this routine. */
1908 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1909 target_name(target
), __func__
);
1913 static int xscale_write_memory(struct target
*target
, uint32_t address
,
1914 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1916 struct xscale_common
*xscale
= target_to_xscale(target
);
1919 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1921 if (target
->state
!= TARGET_HALTED
)
1923 LOG_WARNING("target not halted");
1924 return ERROR_TARGET_NOT_HALTED
;
1927 /* sanitize arguments */
1928 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1929 return ERROR_INVALID_ARGUMENTS
;
1931 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1932 return ERROR_TARGET_UNALIGNED_ACCESS
;
1934 /* send memory write request (command 0x2n, n: access size) */
1935 if ((retval
= xscale_send_u32(target
, 0x20 | size
)) != ERROR_OK
)
1938 /* send base address for read request */
1939 if ((retval
= xscale_send_u32(target
, address
)) != ERROR_OK
)
1942 /* send number of requested data words to be written*/
1943 if ((retval
= xscale_send_u32(target
, count
)) != ERROR_OK
)
1946 /* extract data from host-endian buffer into byte stream */
1948 for (i
= 0; i
< count
; i
++)
1953 value
= target_buffer_get_u32(target
, buffer
);
1954 xscale_send_u32(target
, value
);
1958 value
= target_buffer_get_u16(target
, buffer
);
1959 xscale_send_u32(target
, value
);
1964 xscale_send_u32(target
, value
);
1968 LOG_ERROR("should never get here");
1973 if ((retval
= xscale_send(target
, buffer
, count
, size
)) != ERROR_OK
)
1976 /* examine DCSR, to see if Sticky Abort (SA) got set */
1977 if ((retval
= xscale_read_dcsr(target
)) != ERROR_OK
)
1979 if (buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 5, 1) == 1)
1982 if ((retval
= xscale_send_u32(target
, 0x60)) != ERROR_OK
)
1985 return ERROR_TARGET_DATA_ABORT
;
1991 static int xscale_write_phys_memory(struct target
*target
, uint32_t address
,
1992 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1994 /** \todo: provide a non-stub implementtion of this routine. */
1995 LOG_ERROR("%s: %s is not implemented. Disable MMU?",
1996 target_name(target
), __func__
);
2000 static int xscale_bulk_write_memory(struct target
*target
, uint32_t address
,
2001 uint32_t count
, uint8_t *buffer
)
2003 return xscale_write_memory(target
, address
, 4, count
, buffer
);
2006 static uint32_t xscale_get_ttb(struct target
*target
)
2008 struct xscale_common
*xscale
= target_to_xscale(target
);
2011 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_TTB
]);
2012 ttb
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_TTB
].value
, 0, 32);
2017 static void xscale_disable_mmu_caches(struct target
*target
, int mmu
,
2018 int d_u_cache
, int i_cache
)
2020 struct xscale_common
*xscale
= target_to_xscale(target
);
2021 uint32_t cp15_control
;
2023 /* read cp15 control register */
2024 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2025 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2028 cp15_control
&= ~0x1U
;
2033 xscale_send_u32(target
, 0x50);
2034 xscale_send_u32(target
, xscale
->cache_clean_address
);
2036 /* invalidate DCache */
2037 xscale_send_u32(target
, 0x51);
2039 cp15_control
&= ~0x4U
;
2044 /* invalidate ICache */
2045 xscale_send_u32(target
, 0x52);
2046 cp15_control
&= ~0x1000U
;
2049 /* write new cp15 control register */
2050 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2052 /* execute cpwait to ensure outstanding operations complete */
2053 xscale_send_u32(target
, 0x53);
2056 static void xscale_enable_mmu_caches(struct target
*target
, int mmu
,
2057 int d_u_cache
, int i_cache
)
2059 struct xscale_common
*xscale
= target_to_xscale(target
);
2060 uint32_t cp15_control
;
2062 /* read cp15 control register */
2063 xscale_get_reg(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
]);
2064 cp15_control
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_CTRL
].value
, 0, 32);
2067 cp15_control
|= 0x1U
;
2070 cp15_control
|= 0x4U
;
2073 cp15_control
|= 0x1000U
;
2075 /* write new cp15 control register */
2076 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_CTRL
], cp15_control
);
2078 /* execute cpwait to ensure outstanding operations complete */
2079 xscale_send_u32(target
, 0x53);
2082 static int xscale_set_breakpoint(struct target
*target
,
2083 struct breakpoint
*breakpoint
)
2086 struct xscale_common
*xscale
= target_to_xscale(target
);
2088 if (target
->state
!= TARGET_HALTED
)
2090 LOG_WARNING("target not halted");
2091 return ERROR_TARGET_NOT_HALTED
;
2094 if (breakpoint
->set
)
2096 LOG_WARNING("breakpoint already set");
2100 if (breakpoint
->type
== BKPT_HARD
)
2102 uint32_t value
= breakpoint
->address
| 1;
2103 if (!xscale
->ibcr0_used
)
2105 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], value
);
2106 xscale
->ibcr0_used
= 1;
2107 breakpoint
->set
= 1; /* breakpoint set on first breakpoint register */
2109 else if (!xscale
->ibcr1_used
)
2111 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], value
);
2112 xscale
->ibcr1_used
= 1;
2113 breakpoint
->set
= 2; /* breakpoint set on second breakpoint register */
2117 LOG_ERROR("BUG: no hardware comparator available");
2121 else if (breakpoint
->type
== BKPT_SOFT
)
2123 if (breakpoint
->length
== 4)
2125 /* keep the original instruction in target endianness */
2126 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2130 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2131 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->arm_bkpt
)) != ERROR_OK
)
2138 /* keep the original instruction in target endianness */
2139 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2143 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2144 if ((retval
= target_write_u32(target
, breakpoint
->address
, xscale
->thumb_bkpt
)) != ERROR_OK
)
2149 breakpoint
->set
= 1;
2155 static int xscale_add_breakpoint(struct target
*target
,
2156 struct breakpoint
*breakpoint
)
2158 struct xscale_common
*xscale
= target_to_xscale(target
);
2160 if ((breakpoint
->type
== BKPT_HARD
) && (xscale
->ibcr_available
< 1))
2162 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2163 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2166 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
2168 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2169 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2172 if (breakpoint
->type
== BKPT_HARD
)
2174 xscale
->ibcr_available
--;
2180 static int xscale_unset_breakpoint(struct target
*target
,
2181 struct breakpoint
*breakpoint
)
2184 struct xscale_common
*xscale
= target_to_xscale(target
);
2186 if (target
->state
!= TARGET_HALTED
)
2188 LOG_WARNING("target not halted");
2189 return ERROR_TARGET_NOT_HALTED
;
2192 if (!breakpoint
->set
)
2194 LOG_WARNING("breakpoint not set");
2198 if (breakpoint
->type
== BKPT_HARD
)
2200 if (breakpoint
->set
== 1)
2202 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR0
], 0x0);
2203 xscale
->ibcr0_used
= 0;
2205 else if (breakpoint
->set
== 2)
2207 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_IBCR1
], 0x0);
2208 xscale
->ibcr1_used
= 0;
2210 breakpoint
->set
= 0;
2214 /* restore original instruction (kept in target endianness) */
2215 if (breakpoint
->length
== 4)
2217 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2224 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
2229 breakpoint
->set
= 0;
2235 static int xscale_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
2237 struct xscale_common
*xscale
= target_to_xscale(target
);
2239 if (target
->state
!= TARGET_HALTED
)
2241 LOG_WARNING("target not halted");
2242 return ERROR_TARGET_NOT_HALTED
;
2245 if (breakpoint
->set
)
2247 xscale_unset_breakpoint(target
, breakpoint
);
2250 if (breakpoint
->type
== BKPT_HARD
)
2251 xscale
->ibcr_available
++;
2256 static int xscale_set_watchpoint(struct target
*target
,
2257 struct watchpoint
*watchpoint
)
2259 struct xscale_common
*xscale
= target_to_xscale(target
);
2261 struct reg
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2262 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2264 if (target
->state
!= TARGET_HALTED
)
2266 LOG_WARNING("target not halted");
2267 return ERROR_TARGET_NOT_HALTED
;
2270 xscale_get_reg(dbcon
);
2272 switch (watchpoint
->rw
)
2284 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2287 if (!xscale
->dbr0_used
)
2289 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR0
], watchpoint
->address
);
2290 dbcon_value
|= enable
;
2291 xscale_set_reg_u32(dbcon
, dbcon_value
);
2292 watchpoint
->set
= 1;
2293 xscale
->dbr0_used
= 1;
2295 else if (!xscale
->dbr1_used
)
2297 xscale_set_reg_u32(&xscale
->reg_cache
->reg_list
[XSCALE_DBR1
], watchpoint
->address
);
2298 dbcon_value
|= enable
<< 2;
2299 xscale_set_reg_u32(dbcon
, dbcon_value
);
2300 watchpoint
->set
= 2;
2301 xscale
->dbr1_used
= 1;
2305 LOG_ERROR("BUG: no hardware comparator available");
2312 static int xscale_add_watchpoint(struct target
*target
,
2313 struct watchpoint
*watchpoint
)
2315 struct xscale_common
*xscale
= target_to_xscale(target
);
2317 if (xscale
->dbr_available
< 1)
2319 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2322 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
2324 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2327 xscale
->dbr_available
--;
2332 static int xscale_unset_watchpoint(struct target
*target
,
2333 struct watchpoint
*watchpoint
)
2335 struct xscale_common
*xscale
= target_to_xscale(target
);
2336 struct reg
*dbcon
= &xscale
->reg_cache
->reg_list
[XSCALE_DBCON
];
2337 uint32_t dbcon_value
= buf_get_u32(dbcon
->value
, 0, 32);
2339 if (target
->state
!= TARGET_HALTED
)
2341 LOG_WARNING("target not halted");
2342 return ERROR_TARGET_NOT_HALTED
;
2345 if (!watchpoint
->set
)
2347 LOG_WARNING("breakpoint not set");
2351 if (watchpoint
->set
== 1)
2353 dbcon_value
&= ~0x3;
2354 xscale_set_reg_u32(dbcon
, dbcon_value
);
2355 xscale
->dbr0_used
= 0;
2357 else if (watchpoint
->set
== 2)
2359 dbcon_value
&= ~0xc;
2360 xscale_set_reg_u32(dbcon
, dbcon_value
);
2361 xscale
->dbr1_used
= 0;
2363 watchpoint
->set
= 0;
2368 static int xscale_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2370 struct xscale_common
*xscale
= target_to_xscale(target
);
2372 if (target
->state
!= TARGET_HALTED
)
2374 LOG_WARNING("target not halted");
2375 return ERROR_TARGET_NOT_HALTED
;
2378 if (watchpoint
->set
)
2380 xscale_unset_watchpoint(target
, watchpoint
);
2383 xscale
->dbr_available
++;
2388 static int xscale_get_reg(struct reg
*reg
)
2390 struct xscale_reg
*arch_info
= reg
->arch_info
;
2391 struct target
*target
= arch_info
->target
;
2392 struct xscale_common
*xscale
= target_to_xscale(target
);
2394 /* DCSR, TX and RX are accessible via JTAG */
2395 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2397 return xscale_read_dcsr(arch_info
->target
);
2399 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2401 /* 1 = consume register content */
2402 return xscale_read_tx(arch_info
->target
, 1);
2404 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2406 /* can't read from RX register (host -> debug handler) */
2409 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2411 /* can't (explicitly) read from TXRXCTRL register */
2414 else /* Other DBG registers have to be transfered by the debug handler */
2416 /* send CP read request (command 0x40) */
2417 xscale_send_u32(target
, 0x40);
2419 /* send CP register number */
2420 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2422 /* read register value */
2423 xscale_read_tx(target
, 1);
2424 buf_cpy(xscale
->reg_cache
->reg_list
[XSCALE_TX
].value
, reg
->value
, 32);
2433 static int xscale_set_reg(struct reg
*reg
, uint8_t* buf
)
2435 struct xscale_reg
*arch_info
= reg
->arch_info
;
2436 struct target
*target
= arch_info
->target
;
2437 struct xscale_common
*xscale
= target_to_xscale(target
);
2438 uint32_t value
= buf_get_u32(buf
, 0, 32);
2440 /* DCSR, TX and RX are accessible via JTAG */
2441 if (strcmp(reg
->name
, "XSCALE_DCSR") == 0)
2443 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32, value
);
2444 return xscale_write_dcsr(arch_info
->target
, -1, -1);
2446 else if (strcmp(reg
->name
, "XSCALE_RX") == 0)
2448 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_RX
].value
, 0, 32, value
);
2449 return xscale_write_rx(arch_info
->target
);
2451 else if (strcmp(reg
->name
, "XSCALE_TX") == 0)
2453 /* can't write to TX register (debug-handler -> host) */
2456 else if (strcmp(reg
->name
, "XSCALE_TXRXCTRL") == 0)
2458 /* can't (explicitly) write to TXRXCTRL register */
2461 else /* Other DBG registers have to be transfered by the debug handler */
2463 /* send CP write request (command 0x41) */
2464 xscale_send_u32(target
, 0x41);
2466 /* send CP register number */
2467 xscale_send_u32(target
, arch_info
->dbg_handler_number
);
2469 /* send CP register value */
2470 xscale_send_u32(target
, value
);
2471 buf_set_u32(reg
->value
, 0, 32, value
);
2477 static int xscale_write_dcsr_sw(struct target
*target
, uint32_t value
)
2479 struct xscale_common
*xscale
= target_to_xscale(target
);
2480 struct reg
*dcsr
= &xscale
->reg_cache
->reg_list
[XSCALE_DCSR
];
2481 struct xscale_reg
*dcsr_arch_info
= dcsr
->arch_info
;
2483 /* send CP write request (command 0x41) */
2484 xscale_send_u32(target
, 0x41);
2486 /* send CP register number */
2487 xscale_send_u32(target
, dcsr_arch_info
->dbg_handler_number
);
2489 /* send CP register value */
2490 xscale_send_u32(target
, value
);
2491 buf_set_u32(dcsr
->value
, 0, 32, value
);
2496 static int xscale_read_trace(struct target
*target
)
2498 struct xscale_common
*xscale
= target_to_xscale(target
);
2499 struct arm
*armv4_5
= &xscale
->armv4_5_common
;
2500 struct xscale_trace_data
**trace_data_p
;
2502 /* 258 words from debug handler
2503 * 256 trace buffer entries
2504 * 2 checkpoint addresses
2506 uint32_t trace_buffer
[258];
2507 int is_address
[256];
2510 if (target
->state
!= TARGET_HALTED
)
2512 LOG_WARNING("target must be stopped to read trace data");
2513 return ERROR_TARGET_NOT_HALTED
;
2516 /* send read trace buffer command (command 0x61) */
2517 xscale_send_u32(target
, 0x61);
2519 /* receive trace buffer content */
2520 xscale_receive(target
, trace_buffer
, 258);
2522 /* parse buffer backwards to identify address entries */
2523 for (i
= 255; i
>= 0; i
--)
2526 if (((trace_buffer
[i
] & 0xf0) == 0x90) ||
2527 ((trace_buffer
[i
] & 0xf0) == 0xd0))
2530 is_address
[--i
] = 1;
2532 is_address
[--i
] = 1;
2534 is_address
[--i
] = 1;
2536 is_address
[--i
] = 1;
2541 /* search first non-zero entry */
2542 for (j
= 0; (j
< 256) && (trace_buffer
[j
] == 0) && (!is_address
[j
]); j
++)
2547 LOG_DEBUG("no trace data collected");
2548 return ERROR_XSCALE_NO_TRACE_DATA
;
2551 for (trace_data_p
= &xscale
->trace
.data
; *trace_data_p
; trace_data_p
= &(*trace_data_p
)->next
)
2554 *trace_data_p
= malloc(sizeof(struct xscale_trace_data
));
2555 (*trace_data_p
)->next
= NULL
;
2556 (*trace_data_p
)->chkpt0
= trace_buffer
[256];
2557 (*trace_data_p
)->chkpt1
= trace_buffer
[257];
2558 (*trace_data_p
)->last_instruction
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2559 (*trace_data_p
)->entries
= malloc(sizeof(struct xscale_trace_entry
) * (256 - j
));
2560 (*trace_data_p
)->depth
= 256 - j
;
2562 for (i
= j
; i
< 256; i
++)
2564 (*trace_data_p
)->entries
[i
- j
].data
= trace_buffer
[i
];
2566 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_ADDRESS
;
2568 (*trace_data_p
)->entries
[i
- j
].type
= XSCALE_TRACE_MESSAGE
;
2574 static int xscale_read_instruction(struct target
*target
,
2575 struct arm_instruction
*instruction
)
2577 struct xscale_common
*xscale
= target_to_xscale(target
);
2584 if (!xscale
->trace
.image
)
2585 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
2587 /* search for the section the current instruction belongs to */
2588 for (i
= 0; i
< xscale
->trace
.image
->num_sections
; i
++)
2590 if ((xscale
->trace
.image
->sections
[i
].base_address
<= xscale
->trace
.current_pc
) &&
2591 (xscale
->trace
.image
->sections
[i
].base_address
+ xscale
->trace
.image
->sections
[i
].size
> xscale
->trace
.current_pc
))
2600 /* current instruction couldn't be found in the image */
2601 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2604 if (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
)
2607 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2608 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2609 4, buf
, &size_read
)) != ERROR_OK
)
2611 LOG_ERROR("error while reading instruction: %i", retval
);
2612 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2614 opcode
= target_buffer_get_u32(target
, buf
);
2615 arm_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2617 else if (xscale
->trace
.core_state
== ARMV4_5_STATE_THUMB
)
2620 if ((retval
= image_read_section(xscale
->trace
.image
, section
,
2621 xscale
->trace
.current_pc
- xscale
->trace
.image
->sections
[section
].base_address
,
2622 2, buf
, &size_read
)) != ERROR_OK
)
2624 LOG_ERROR("error while reading instruction: %i", retval
);
2625 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
2627 opcode
= target_buffer_get_u16(target
, buf
);
2628 thumb_evaluate_opcode(opcode
, xscale
->trace
.current_pc
, instruction
);
2632 LOG_ERROR("BUG: unknown core state encountered");
2639 static int xscale_branch_address(struct xscale_trace_data
*trace_data
,
2640 int i
, uint32_t *target
)
2642 /* if there are less than four entries prior to the indirect branch message
2643 * we can't extract the address */
2649 *target
= (trace_data
->entries
[i
-1].data
) | (trace_data
->entries
[i
-2].data
<< 8) |
2650 (trace_data
->entries
[i
-3].data
<< 16) | (trace_data
->entries
[i
-4].data
<< 24);
2655 static int xscale_analyze_trace(struct target
*target
, struct command_context
*cmd_ctx
)
2657 struct xscale_common
*xscale
= target_to_xscale(target
);
2659 uint32_t next_pc
= 0x0;
2660 struct xscale_trace_data
*trace_data
= xscale
->trace
.data
;
2669 xscale
->trace
.core_state
= ARMV4_5_STATE_ARM
;
2674 for (i
= 0; i
< trace_data
->depth
; i
++)
2680 if (trace_data
->entries
[i
].type
== XSCALE_TRACE_ADDRESS
)
2683 switch ((trace_data
->entries
[i
].data
& 0xf0) >> 4)
2685 case 0: /* Exceptions */
2693 exception
= (trace_data
->entries
[i
].data
& 0x70) >> 4;
2695 next_pc
= (trace_data
->entries
[i
].data
& 0xf0) >> 2;
2696 command_print(cmd_ctx
, "--- exception %i ---", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2698 case 8: /* Direct Branch */
2701 case 9: /* Indirect Branch */
2703 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2708 case 13: /* Checkpointed Indirect Branch */
2709 if (xscale_branch_address(trace_data
, i
, &next_pc
) == 0)
2712 if (((chkpt
== 0) && (next_pc
!= trace_data
->chkpt0
))
2713 || ((chkpt
== 1) && (next_pc
!= trace_data
->chkpt1
)))
2714 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2716 /* explicit fall-through */
2717 case 12: /* Checkpointed Direct Branch */
2722 next_pc
= trace_data
->chkpt0
;
2725 else if (chkpt
== 1)
2728 next_pc
= trace_data
->chkpt0
;
2733 LOG_WARNING("more than two checkpointed branches encountered");
2736 case 15: /* Roll-over */
2739 default: /* Reserved */
2740 command_print(cmd_ctx
, "--- reserved trace message ---");
2741 LOG_ERROR("BUG: trace message %i is reserved", (trace_data
->entries
[i
].data
& 0xf0) >> 4);
2745 if (xscale
->trace
.pc_ok
)
2747 int executed
= (trace_data
->entries
[i
].data
& 0xf) + rollover
* 16;
2748 struct arm_instruction instruction
;
2750 if ((exception
== 6) || (exception
== 7))
2752 /* IRQ or FIQ exception, no instruction executed */
2756 while (executed
-- >= 0)
2758 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2760 /* can't continue tracing with no image available */
2761 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2765 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2767 /* TODO: handle incomplete images */
2771 /* a precise abort on a load to the PC is included in the incremental
2772 * word count, other instructions causing data aborts are not included
2774 if ((executed
== 0) && (exception
== 4)
2775 && ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDM
)))
2777 if ((instruction
.type
== ARM_LDM
)
2778 && ((instruction
.info
.load_store_multiple
.register_list
& 0x8000) == 0))
2782 else if (((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_LDRSH
))
2783 && (instruction
.info
.load_store
.Rd
!= 15))
2789 /* only the last instruction executed
2790 * (the one that caused the control flow change)
2791 * could be a taken branch
2793 if (((executed
== -1) && (branch
== 1)) &&
2794 (((instruction
.type
== ARM_B
) ||
2795 (instruction
.type
== ARM_BL
) ||
2796 (instruction
.type
== ARM_BLX
)) &&
2797 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff)))
2799 xscale
->trace
.current_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
2803 xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
2805 command_print(cmd_ctx
, "%s", instruction
.text
);
2813 xscale
->trace
.current_pc
= next_pc
;
2814 xscale
->trace
.pc_ok
= 1;
2818 for (; xscale
->trace
.current_pc
< trace_data
->last_instruction
; xscale
->trace
.current_pc
+= (xscale
->trace
.core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2)
2820 struct arm_instruction instruction
;
2821 if ((retval
= xscale_read_instruction(target
, &instruction
)) != ERROR_OK
)
2823 /* can't continue tracing with no image available */
2824 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
2828 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
2830 /* TODO: handle incomplete images */
2833 command_print(cmd_ctx
, "%s", instruction
.text
);
2836 trace_data
= trace_data
->next
;
2842 static const struct reg_arch_type xscale_reg_type
= {
2843 .get
= xscale_get_reg
,
2844 .set
= xscale_set_reg
,
2847 static void xscale_build_reg_cache(struct target
*target
)
2849 struct xscale_common
*xscale
= target_to_xscale(target
);
2850 struct arm
*armv4_5
= &xscale
->armv4_5_common
;
2851 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
2852 struct xscale_reg
*arch_info
= malloc(sizeof(xscale_reg_arch_info
));
2854 int num_regs
= ARRAY_SIZE(xscale_reg_arch_info
);
2856 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
2858 (*cache_p
)->next
= malloc(sizeof(struct reg_cache
));
2859 cache_p
= &(*cache_p
)->next
;
2861 /* fill in values for the xscale reg cache */
2862 (*cache_p
)->name
= "XScale registers";
2863 (*cache_p
)->next
= NULL
;
2864 (*cache_p
)->reg_list
= malloc(num_regs
* sizeof(struct reg
));
2865 (*cache_p
)->num_regs
= num_regs
;
2867 for (i
= 0; i
< num_regs
; i
++)
2869 (*cache_p
)->reg_list
[i
].name
= xscale_reg_list
[i
];
2870 (*cache_p
)->reg_list
[i
].value
= calloc(4, 1);
2871 (*cache_p
)->reg_list
[i
].dirty
= 0;
2872 (*cache_p
)->reg_list
[i
].valid
= 0;
2873 (*cache_p
)->reg_list
[i
].size
= 32;
2874 (*cache_p
)->reg_list
[i
].arch_info
= &arch_info
[i
];
2875 (*cache_p
)->reg_list
[i
].type
= &xscale_reg_type
;
2876 arch_info
[i
] = xscale_reg_arch_info
[i
];
2877 arch_info
[i
].target
= target
;
2880 xscale
->reg_cache
= (*cache_p
);
2883 static int xscale_init_target(struct command_context
*cmd_ctx
,
2884 struct target
*target
)
2886 xscale_build_reg_cache(target
);
2890 static int xscale_init_arch_info(struct target
*target
,
2891 struct xscale_common
*xscale
, struct jtag_tap
*tap
, const char *variant
)
2893 struct arm
*armv4_5
;
2894 uint32_t high_reset_branch
, low_reset_branch
;
2897 armv4_5
= &xscale
->armv4_5_common
;
2899 /* store architecture specfic data */
2900 xscale
->common_magic
= XSCALE_COMMON_MAGIC
;
2902 /* we don't really *need* a variant param ... */
2906 if (strcmp(variant
, "pxa250") == 0
2907 || strcmp(variant
, "pxa255") == 0
2908 || strcmp(variant
, "pxa26x") == 0)
2910 else if (strcmp(variant
, "pxa27x") == 0
2911 || strcmp(variant
, "ixp42x") == 0
2912 || strcmp(variant
, "ixp45x") == 0
2913 || strcmp(variant
, "ixp46x") == 0)
2915 else if (strcmp(variant
, "pxa3xx") == 0)
2918 LOG_WARNING("%s: unrecognized variant %s",
2919 tap
->dotted_name
, variant
);
2921 if (ir_length
&& ir_length
!= tap
->ir_length
) {
2922 LOG_WARNING("%s: IR length for %s is %d; fixing",
2923 tap
->dotted_name
, variant
, ir_length
);
2924 tap
->ir_length
= ir_length
;
2928 /* PXA3xx shifts the JTAG instructions */
2929 if (tap
->ir_length
== 11)
2930 xscale
->xscale_variant
= XSCALE_PXA3XX
;
2932 xscale
->xscale_variant
= XSCALE_IXP4XX_PXA2XX
;
2934 /* the debug handler isn't installed (and thus not running) at this time */
2935 xscale
->handler_address
= 0xfe000800;
2937 /* clear the vectors we keep locally for reference */
2938 memset(xscale
->low_vectors
, 0, sizeof(xscale
->low_vectors
));
2939 memset(xscale
->high_vectors
, 0, sizeof(xscale
->high_vectors
));
2941 /* no user-specified vectors have been configured yet */
2942 xscale
->static_low_vectors_set
= 0x0;
2943 xscale
->static_high_vectors_set
= 0x0;
2945 /* calculate branches to debug handler */
2946 low_reset_branch
= (xscale
->handler_address
+ 0x20 - 0x0 - 0x8) >> 2;
2947 high_reset_branch
= (xscale
->handler_address
+ 0x20 - 0xffff0000 - 0x8) >> 2;
2949 xscale
->low_vectors
[0] = ARMV4_5_B((low_reset_branch
& 0xffffff), 0);
2950 xscale
->high_vectors
[0] = ARMV4_5_B((high_reset_branch
& 0xffffff), 0);
2952 for (i
= 1; i
<= 7; i
++)
2954 xscale
->low_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
2955 xscale
->high_vectors
[i
] = ARMV4_5_B(0xfffffe, 0);
2958 /* 64kB aligned region used for DCache cleaning */
2959 xscale
->cache_clean_address
= 0xfffe0000;
2961 xscale
->hold_rst
= 0;
2962 xscale
->external_debug_break
= 0;
2964 xscale
->ibcr_available
= 2;
2965 xscale
->ibcr0_used
= 0;
2966 xscale
->ibcr1_used
= 0;
2968 xscale
->dbr_available
= 2;
2969 xscale
->dbr0_used
= 0;
2970 xscale
->dbr1_used
= 0;
2972 xscale
->arm_bkpt
= ARMV5_BKPT(0x0);
2973 xscale
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
2975 xscale
->vector_catch
= 0x1;
2977 xscale
->trace
.capture_status
= TRACE_IDLE
;
2978 xscale
->trace
.data
= NULL
;
2979 xscale
->trace
.image
= NULL
;
2980 xscale
->trace
.buffer_enabled
= 0;
2981 xscale
->trace
.buffer_fill
= 0;
2983 /* prepare ARMv4/5 specific information */
2984 armv4_5
->arch_info
= xscale
;
2985 armv4_5
->read_core_reg
= xscale_read_core_reg
;
2986 armv4_5
->write_core_reg
= xscale_write_core_reg
;
2987 armv4_5
->full_context
= xscale_full_context
;
2989 armv4_5_init_arch_info(target
, armv4_5
);
2991 xscale
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
2992 xscale
->armv4_5_mmu
.get_ttb
= xscale_get_ttb
;
2993 xscale
->armv4_5_mmu
.read_memory
= xscale_read_memory
;
2994 xscale
->armv4_5_mmu
.write_memory
= xscale_write_memory
;
2995 xscale
->armv4_5_mmu
.disable_mmu_caches
= xscale_disable_mmu_caches
;
2996 xscale
->armv4_5_mmu
.enable_mmu_caches
= xscale_enable_mmu_caches
;
2997 xscale
->armv4_5_mmu
.has_tiny_pages
= 1;
2998 xscale
->armv4_5_mmu
.mmu_enabled
= 0;
3003 static int xscale_target_create(struct target
*target
, Jim_Interp
*interp
)
3005 struct xscale_common
*xscale
;
3007 if (sizeof xscale_debug_handler
- 1 > 0x800) {
3008 LOG_ERROR("debug_handler.bin: larger than 2kb");
3012 xscale
= calloc(1, sizeof(*xscale
));
3016 return xscale_init_arch_info(target
, xscale
, target
->tap
,
3020 COMMAND_HANDLER(xscale_handle_debug_handler_command
)
3022 struct target
*target
= NULL
;
3023 struct xscale_common
*xscale
;
3025 uint32_t handler_address
;
3029 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3033 if ((target
= get_target(CMD_ARGV
[0])) == NULL
)
3035 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
3039 xscale
= target_to_xscale(target
);
3040 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3041 if (retval
!= ERROR_OK
)
3044 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], handler_address
);
3046 if (((handler_address
>= 0x800) && (handler_address
<= 0x1fef800)) ||
3047 ((handler_address
>= 0xfe000800) && (handler_address
<= 0xfffff800)))
3049 xscale
->handler_address
= handler_address
;
3053 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3060 COMMAND_HANDLER(xscale_handle_cache_clean_address_command
)
3062 struct target
*target
= NULL
;
3063 struct xscale_common
*xscale
;
3065 uint32_t cache_clean_address
;
3069 return ERROR_COMMAND_SYNTAX_ERROR
;
3072 target
= get_target(CMD_ARGV
[0]);
3075 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
3078 xscale
= target_to_xscale(target
);
3079 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3080 if (retval
!= ERROR_OK
)
3083 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cache_clean_address
);
3085 if (cache_clean_address
& 0xffff)
3087 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3091 xscale
->cache_clean_address
= cache_clean_address
;
3097 COMMAND_HANDLER(xscale_handle_cache_info_command
)
3099 struct target
*target
= get_current_target(CMD_CTX
);
3100 struct xscale_common
*xscale
= target_to_xscale(target
);
3103 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3104 if (retval
!= ERROR_OK
)
3107 return armv4_5_handle_cache_info_command(CMD_CTX
, &xscale
->armv4_5_mmu
.armv4_5_cache
);
3110 static int xscale_virt2phys(struct target
*target
,
3111 uint32_t virtual, uint32_t *physical
)
3113 struct xscale_common
*xscale
= target_to_xscale(target
);
3119 if (xscale
->common_magic
!= XSCALE_COMMON_MAGIC
) {
3120 LOG_ERROR(xscale_not
);
3121 return ERROR_TARGET_INVALID
;
3124 uint32_t ret
= armv4_5_mmu_translate_va(target
, &xscale
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
3133 static int xscale_mmu(struct target
*target
, int *enabled
)
3135 struct xscale_common
*xscale
= target_to_xscale(target
);
3137 if (target
->state
!= TARGET_HALTED
)
3139 LOG_ERROR("Target not halted");
3140 return ERROR_TARGET_INVALID
;
3142 *enabled
= xscale
->armv4_5_mmu
.mmu_enabled
;
3146 COMMAND_HANDLER(xscale_handle_mmu_command
)
3148 struct target
*target
= get_current_target(CMD_CTX
);
3149 struct xscale_common
*xscale
= target_to_xscale(target
);
3152 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3153 if (retval
!= ERROR_OK
)
3156 if (target
->state
!= TARGET_HALTED
)
3158 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3165 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], enable
);
3167 xscale_enable_mmu_caches(target
, 1, 0, 0);
3169 xscale_disable_mmu_caches(target
, 1, 0, 0);
3170 xscale
->armv4_5_mmu
.mmu_enabled
= enable
;
3173 command_print(CMD_CTX
, "mmu %s", (xscale
->armv4_5_mmu
.mmu_enabled
) ? "enabled" : "disabled");
3178 COMMAND_HANDLER(xscale_handle_idcache_command
)
3180 struct target
*target
= get_current_target(CMD_CTX
);
3181 struct xscale_common
*xscale
= target_to_xscale(target
);
3183 int retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3184 if (retval
!= ERROR_OK
)
3187 if (target
->state
!= TARGET_HALTED
)
3189 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3194 COMMAND_PARSE_BOOL(CMD_NAME
, icache
, "icache", "dcache");
3199 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], enable
);
3201 xscale_enable_mmu_caches(target
, 1, 0, 0);
3203 xscale_disable_mmu_caches(target
, 1, 0, 0);
3205 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= enable
;
3207 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= enable
;
3210 bool enabled
= icache
?
3211 xscale
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
:
3212 xscale
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
;
3213 const char *msg
= enabled
? "enabled" : "disabled";
3214 command_print(CMD_CTX
, "%s %s", CMD_NAME
, msg
);
3219 COMMAND_HANDLER(xscale_handle_vector_catch_command
)
3221 struct target
*target
= get_current_target(CMD_CTX
);
3222 struct xscale_common
*xscale
= target_to_xscale(target
);
3225 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3226 if (retval
!= ERROR_OK
)
3231 command_print(CMD_CTX
, "usage: xscale vector_catch [mask]");
3235 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[0], xscale
->vector_catch
);
3236 buf_set_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 16, 8, xscale
->vector_catch
);
3237 xscale_write_dcsr(target
, -1, -1);
3240 command_print(CMD_CTX
, "vector catch mask: 0x%2.2x", xscale
->vector_catch
);
3246 COMMAND_HANDLER(xscale_handle_vector_table_command
)
3248 struct target
*target
= get_current_target(CMD_CTX
);
3249 struct xscale_common
*xscale
= target_to_xscale(target
);
3253 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3254 if (retval
!= ERROR_OK
)
3257 if (CMD_ARGC
== 0) /* print current settings */
3261 command_print(CMD_CTX
, "active user-set static vectors:");
3262 for (idx
= 1; idx
< 8; idx
++)
3263 if (xscale
->static_low_vectors_set
& (1 << idx
))
3264 command_print(CMD_CTX
, "low %d: 0x%" PRIx32
, idx
, xscale
->static_low_vectors
[idx
]);
3265 for (idx
= 1; idx
< 8; idx
++)
3266 if (xscale
->static_high_vectors_set
& (1 << idx
))
3267 command_print(CMD_CTX
, "high %d: 0x%" PRIx32
, idx
, xscale
->static_high_vectors
[idx
]);
3276 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], idx
);
3278 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], vec
);
3280 if (idx
< 1 || idx
>= 8)
3283 if (!err
&& strcmp(CMD_ARGV
[0], "low") == 0)
3285 xscale
->static_low_vectors_set
|= (1<<idx
);
3286 xscale
->static_low_vectors
[idx
] = vec
;
3288 else if (!err
&& (strcmp(CMD_ARGV
[0], "high") == 0))
3290 xscale
->static_high_vectors_set
|= (1<<idx
);
3291 xscale
->static_high_vectors
[idx
] = vec
;
3298 command_print(CMD_CTX
, "usage: xscale vector_table <high|low> <index> <code>");
3304 COMMAND_HANDLER(xscale_handle_trace_buffer_command
)
3306 struct target
*target
= get_current_target(CMD_CTX
);
3307 struct xscale_common
*xscale
= target_to_xscale(target
);
3308 struct arm
*armv4_5
= &xscale
->armv4_5_common
;
3309 uint32_t dcsr_value
;
3312 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3313 if (retval
!= ERROR_OK
)
3316 if (target
->state
!= TARGET_HALTED
)
3318 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3322 if ((CMD_ARGC
>= 1) && (strcmp("enable", CMD_ARGV
[0]) == 0))
3324 struct xscale_trace_data
*td
, *next_td
;
3325 xscale
->trace
.buffer_enabled
= 1;
3327 /* free old trace data */
3328 td
= xscale
->trace
.data
;
3338 xscale
->trace
.data
= NULL
;
3340 else if ((CMD_ARGC
>= 1) && (strcmp("disable", CMD_ARGV
[0]) == 0))
3342 xscale
->trace
.buffer_enabled
= 0;
3345 if ((CMD_ARGC
>= 2) && (strcmp("fill", CMD_ARGV
[1]) == 0))
3349 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], fill
);
3350 xscale
->trace
.buffer_fill
= fill
;
3352 else if ((CMD_ARGC
>= 2) && (strcmp("wrap", CMD_ARGV
[1]) == 0))
3354 xscale
->trace
.buffer_fill
= -1;
3357 if (xscale
->trace
.buffer_enabled
)
3359 /* if we enable the trace buffer in fill-once
3360 * mode we know the address of the first instruction */
3361 xscale
->trace
.pc_ok
= 1;
3362 xscale
->trace
.current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
3366 /* otherwise the address is unknown, and we have no known good PC */
3367 xscale
->trace
.pc_ok
= 0;
3370 command_print(CMD_CTX
, "trace buffer %s (%s)",
3371 (xscale
->trace
.buffer_enabled
) ? "enabled" : "disabled",
3372 (xscale
->trace
.buffer_fill
> 0) ? "fill" : "wrap");
3374 dcsr_value
= buf_get_u32(xscale
->reg_cache
->reg_list
[XSCALE_DCSR
].value
, 0, 32);
3375 if (xscale
->trace
.buffer_fill
>= 0)
3376 xscale_write_dcsr_sw(target
, (dcsr_value
& 0xfffffffc) | 2);
3378 xscale_write_dcsr_sw(target
, dcsr_value
& 0xfffffffc);
3383 COMMAND_HANDLER(xscale_handle_trace_image_command
)
3385 struct target
*target
= get_current_target(CMD_CTX
);
3386 struct xscale_common
*xscale
= target_to_xscale(target
);
3391 command_print(CMD_CTX
, "usage: xscale trace_image <file> [base address] [type]");
3395 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3396 if (retval
!= ERROR_OK
)
3399 if (xscale
->trace
.image
)
3401 image_close(xscale
->trace
.image
);
3402 free(xscale
->trace
.image
);
3403 command_print(CMD_CTX
, "previously loaded image found and closed");
3406 xscale
->trace
.image
= malloc(sizeof(struct image
));
3407 xscale
->trace
.image
->base_address_set
= 0;
3408 xscale
->trace
.image
->start_address_set
= 0;
3410 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3413 xscale
->trace
.image
->base_address_set
= 1;
3414 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], xscale
->trace
.image
->base_address
);
3418 xscale
->trace
.image
->base_address_set
= 0;
3421 if (image_open(xscale
->trace
.image
, CMD_ARGV
[0], (CMD_ARGC
>= 3) ? CMD_ARGV
[2] : NULL
) != ERROR_OK
)
3423 free(xscale
->trace
.image
);
3424 xscale
->trace
.image
= NULL
;
3431 COMMAND_HANDLER(xscale_handle_dump_trace_command
)
3433 struct target
*target
= get_current_target(CMD_CTX
);
3434 struct xscale_common
*xscale
= target_to_xscale(target
);
3435 struct xscale_trace_data
*trace_data
;
3439 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3440 if (retval
!= ERROR_OK
)
3443 if (target
->state
!= TARGET_HALTED
)
3445 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3451 command_print(CMD_CTX
, "usage: xscale dump_trace <file>");
3455 trace_data
= xscale
->trace
.data
;
3459 command_print(CMD_CTX
, "no trace data collected");
3463 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
3472 fileio_write_u32(&file
, trace_data
->chkpt0
);
3473 fileio_write_u32(&file
, trace_data
->chkpt1
);
3474 fileio_write_u32(&file
, trace_data
->last_instruction
);
3475 fileio_write_u32(&file
, trace_data
->depth
);
3477 for (i
= 0; i
< trace_data
->depth
; i
++)
3478 fileio_write_u32(&file
, trace_data
->entries
[i
].data
| ((trace_data
->entries
[i
].type
& 0xffff) << 16));
3480 trace_data
= trace_data
->next
;
3483 fileio_close(&file
);
3488 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command
)
3490 struct target
*target
= get_current_target(CMD_CTX
);
3491 struct xscale_common
*xscale
= target_to_xscale(target
);
3494 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3495 if (retval
!= ERROR_OK
)
3498 xscale_analyze_trace(target
, CMD_CTX
);
3503 COMMAND_HANDLER(xscale_handle_cp15
)
3505 struct target
*target
= get_current_target(CMD_CTX
);
3506 struct xscale_common
*xscale
= target_to_xscale(target
);
3509 retval
= xscale_verify_pointer(CMD_CTX
, xscale
);
3510 if (retval
!= ERROR_OK
)
3513 if (target
->state
!= TARGET_HALTED
)
3515 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3518 uint32_t reg_no
= 0;
3519 struct reg
*reg
= NULL
;
3522 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], reg_no
);
3523 /*translate from xscale cp15 register no to openocd register*/
3527 reg_no
= XSCALE_MAINID
;
3530 reg_no
= XSCALE_CTRL
;
3533 reg_no
= XSCALE_TTB
;
3536 reg_no
= XSCALE_DAC
;
3539 reg_no
= XSCALE_FSR
;
3542 reg_no
= XSCALE_FAR
;
3545 reg_no
= XSCALE_PID
;
3548 reg_no
= XSCALE_CPACCESS
;
3551 command_print(CMD_CTX
, "invalid register number");
3552 return ERROR_INVALID_ARGUMENTS
;
3554 reg
= &xscale
->reg_cache
->reg_list
[reg_no
];
3561 /* read cp15 control register */
3562 xscale_get_reg(reg
);
3563 value
= buf_get_u32(reg
->value
, 0, 32);
3564 command_print(CMD_CTX
, "%s (/%i): 0x%" PRIx32
"", reg
->name
, (int)(reg
->size
), value
);
3566 else if (CMD_ARGC
== 2)
3569 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
3571 /* send CP write request (command 0x41) */
3572 xscale_send_u32(target
, 0x41);
3574 /* send CP register number */
3575 xscale_send_u32(target
, reg_no
);
3577 /* send CP register value */
3578 xscale_send_u32(target
, value
);
3580 /* execute cpwait to ensure outstanding operations complete */
3581 xscale_send_u32(target
, 0x53);
3585 command_print(CMD_CTX
, "usage: cp15 [register]<, [value]>");
3591 static const struct command_registration xscale_exec_command_handlers
[] = {
3593 .name
= "cache_info",
3594 .handler
= &xscale_handle_cache_info_command
,
3595 .mode
= COMMAND_EXEC
, NULL
,
3600 .handler
= &xscale_handle_mmu_command
,
3601 .mode
= COMMAND_EXEC
,
3602 .usage
= "[enable|disable]",
3603 .help
= "enable or disable the MMU",
3607 .handler
= &xscale_handle_idcache_command
,
3608 .mode
= COMMAND_EXEC
,
3609 .usage
= "[enable|disable]",
3610 .help
= "enable or disable the ICache",
3614 .handler
= &xscale_handle_idcache_command
,
3615 .mode
= COMMAND_EXEC
,
3616 .usage
= "[enable|disable]",
3617 .help
= "enable or disable the DCache",
3621 .name
= "vector_catch",
3622 .handler
= &xscale_handle_vector_catch_command
,
3623 .mode
= COMMAND_EXEC
,
3624 .help
= "mask of vectors that should be caught",
3625 .usage
= "[<mask>]",
3628 .name
= "vector_table",
3629 .handler
= &xscale_handle_vector_table_command
,
3630 .mode
= COMMAND_EXEC
,
3631 .usage
= "<high|low> <index> <code>",
3632 .help
= "set static code for exception handler entry",
3636 .name
= "trace_buffer",
3637 .handler
= &xscale_handle_trace_buffer_command
,
3638 .mode
= COMMAND_EXEC
,
3639 .usage
= "<enable | disable> [fill [n]|wrap]",
3642 .name
= "dump_trace",
3643 .handler
= &xscale_handle_dump_trace_command
,
3644 .mode
= COMMAND_EXEC
,
3645 .help
= "dump content of trace buffer to <file>",
3649 .name
= "analyze_trace",
3650 .handler
= &xscale_handle_analyze_trace_buffer_command
,
3651 .mode
= COMMAND_EXEC
,
3652 .help
= "analyze content of trace buffer",
3655 .name
= "trace_image",
3656 .handler
= &xscale_handle_trace_image_command
,
3658 .help
= "load image from <file> [base address]",
3659 .usage
= "<file> [address] [type]",
3664 .handler
= &xscale_handle_cp15
,
3665 .mode
= COMMAND_EXEC
,
3666 .help
= "access coproc 15",
3667 .usage
= "<register> [value]",
3669 COMMAND_REGISTRATION_DONE
3671 static const struct command_registration xscale_any_command_handlers
[] = {
3673 .name
= "debug_handler",
3674 .handler
= &xscale_handle_debug_handler_command
,
3675 .mode
= COMMAND_ANY
,
3676 .usage
= "<target#> <address>",
3679 .name
= "cache_clean_address",
3680 .handler
= &xscale_handle_cache_clean_address_command
,
3681 .mode
= COMMAND_ANY
,
3684 .chain
= xscale_exec_command_handlers
,
3686 COMMAND_REGISTRATION_DONE
3688 static const struct command_registration xscale_command_handlers
[] = {
3690 .chain
= arm_command_handlers
,
3694 .mode
= COMMAND_ANY
,
3695 .help
= "xscale command group",
3696 .chain
= xscale_any_command_handlers
,
3698 COMMAND_REGISTRATION_DONE
3701 struct target_type xscale_target
=
3705 .poll
= xscale_poll
,
3706 .arch_state
= xscale_arch_state
,
3708 .target_request_data
= NULL
,
3710 .halt
= xscale_halt
,
3711 .resume
= xscale_resume
,
3712 .step
= xscale_step
,
3714 .assert_reset
= xscale_assert_reset
,
3715 .deassert_reset
= xscale_deassert_reset
,
3716 .soft_reset_halt
= NULL
,
3718 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
3720 .read_memory
= xscale_read_memory
,
3721 .read_phys_memory
= xscale_read_phys_memory
,
3722 .write_memory
= xscale_write_memory
,
3723 .write_phys_memory
= xscale_write_phys_memory
,
3724 .bulk_write_memory
= xscale_bulk_write_memory
,
3726 .checksum_memory
= arm_checksum_memory
,
3727 .blank_check_memory
= arm_blank_check_memory
,
3729 .run_algorithm
= armv4_5_run_algorithm
,
3731 .add_breakpoint
= xscale_add_breakpoint
,
3732 .remove_breakpoint
= xscale_remove_breakpoint
,
3733 .add_watchpoint
= xscale_add_watchpoint
,
3734 .remove_watchpoint
= xscale_remove_watchpoint
,
3736 .commands
= xscale_command_handlers
,
3737 .target_create
= xscale_target_create
,
3738 .init_target
= xscale_init_target
,
3740 .virt2phys
= xscale_virt2phys
,